JP2005157322A - Driving circuit, display device, driving method therefor, control method, and driving device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To display images having satisfactory gradation performance and high contrast, by securing a full D range of luminance, in a display device provided with a driving circuit using TFTs. <P>SOLUTION: A current-setting circuit 1 is arranged for each data line 11, a correction current is set from an image current of non-display in the blanking period, an image current for display is corrected by the correction current, and current is not supplied to an EL element during black display. The absolute value of the potential difference between a potential of the image signal, corresponding to black display which is applied after a threshold of a transistor, is reset by self-discharging of the transistor in a voltage/current conversion circuit, and the source potential of the transistor is made smaller than that between a potential of the image signal at the time of threshold reset and the source potential of the transistor. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a display device that displays an image based on a video signal and a drive circuit for the display device, and in particular, is configured using an electroluminescence (EL) element that includes the drive circuit and that emits light when a pixel injects current. The present invention relates to a display device.

  In a flat display device configured by using an EL element or a liquid crystal element, pixels arranged in a plurality of rows and a plurality of columns are commonly connected to a vertical scanning line for each row and to a data line for each column. In general, matrix driving is performed in which each vertical scanning line is selected by the scanning circuit, and at the same time, a predetermined display signal is applied to each data line from the horizontal scanning circuit to perform predetermined display on the selected pixels in the corresponding row. .

  For example, Patent Document 1 discloses an EL display device by active matrix driving.

  The light emission luminance of the EL element is controlled by the amount of current flowing through the element. Therefore, the display signal applied to each data line must have an accurate current value corresponding to the display level (gradation) of each pixel, and in order to achieve high contrast, the EL signal is displayed in black display. Ideally, the current flowing through the element is zero.

  In Patent Document 2, A and B two scanning lines are connected to each pixel row, and the signal current level captured from the data line by selection of the scanning line A is converted into a voltage level and held. A display device has been disclosed in which variations in TFTs for each pixel and variations in light emission luminance due to leakage currents are eliminated by supplying a current level corresponding to the voltage level as a drive current to an EL light emitting element to emit light.

US Pat. No. 6,373,454 JP 2001-147659 A

  It is an object of the present invention to control the magnitude of the current supplied when the lowest level video signal is input in a circuit that supplies a current corresponding to the level of the video signal to the supply target.

A first invention according to the present application includes an image display unit in which a plurality of pixels are arranged in a matrix, pixels in each row are commonly connected to a scanning line, and pixels in each column are commonly connected to a data line. In a display device that performs display by applying a video current of a level corresponding to the display of each pixel in the selected row to the data line to which the pixel is connected at the same time as selecting the line sequentially, for driving each pixel A drive circuit,
At least one current setting circuit is connected to each data line, the current setting circuit detects a current flowing through the data line during a period not involved in display, and the detected current is used as a correction current to display a current for display as data. In the driving circuit, the video current corrected by the correction current is applied to the data line in a period to be applied to the line.

  The second invention has a transistor for flowing the correction current in the first invention, and the transistor for flowing the correction current by a current flowing through the data line in a period not involved in the display. And a current obtained by subtracting a correction current flowing from the transistor from a video current before correction is supplied as a video current in a period in which the current for display is to be applied to a data line. It is.

  A third invention according to the present application is a display device including the drive circuit according to the first or second invention, wherein each pixel includes an element that emits light in response to an injection current. It is a display device.

  A fourth invention according to the present application is the display device according to the third invention, wherein the element is an electroluminescence element.

The fifth invention related to the present application is:
In a circuit including a transistor having a control electrode and first and second main electrodes, a control method for controlling a current flowing through the first main electrode,
The potential of the control electrode is brought close to the potential applied to the second main electrode, and the potential difference between the potential of the control electrode and the potential applied to the second main electrode is set to the threshold voltage of the transistor. A first step of approaching;
A second step of setting, as the potential of the control electrode, a potential obtained by adding a voltage corresponding to the potential amplitude of the video signal to the potential of the control electrode set in the first step;
Have
The absolute value of the difference between the potential set as the potential of the control electrode when the video signal is at the lowest level in the second step and the potential applied to the second main electrode in the second step Is smaller than the absolute value of the difference between the potential of the control electrode set in the first step and the potential applied to the second main electrode in the second step. It is invention of this.

  In a sixth aspect based on the fifth aspect, in the first step, the first main electrode and the control electrode are connected to each other, whereby the potential of the control electrode is set to the second level. It is an invention that requires close to the potential applied to the main electrode.

In addition, the seventh invention,
In a circuit including a transistor having a control electrode and first and second main electrodes, a control method for controlling a current flowing through the first main electrode,
A first step of bringing the control electrode and the first main electrode into a connected state, thereby bringing the potential of the control electrode close to the potential applied to the second main electrode;
A second step of setting, as the potential of the control electrode, a potential obtained by adding a voltage corresponding to the potential amplitude of the video signal to the potential of the control electrode set in the first step;
Have
The absolute value of the difference between the potential set as the potential of the control electrode when the video signal is at the lowest level in the second step and the potential applied to the second main electrode in the second step Is smaller than the absolute value of the difference between the potential of the control electrode set in the first step and the potential applied to the second main electrode in the second step. It is invention of this.

  In the present application, the potential amplitude of the video signal means a potential difference between the reference potential of the video signal and the modulation potential. The modulation potential is a potential set to a potential in the range from the lowest level to the highest level. The lowest level may be a lower potential than the highest level, and vice versa. The lowest level corresponds to a so-called black level in the detailed description below. The black level does not mean that the application target of the present invention is limited to a configuration using a video signal for monochrome display. That the video signal is at the lowest level means that the modulation potential of the video signal is the lowest potential that the modulation potential can take. In the following detailed description, the blanking level corresponds to the reference potential of the video signal.

  According to an eighth aspect of the present invention, in any one of the fifth to seventh aspects, before the first step, the potential of the control electrode is set higher than the potential of the control electrode set in the first step. The invention is characterized in that it has a step of setting the potential difference between the potential applied to the second main electrode to a large potential.

  A ninth invention is the invention according to any one of the fifth to eighth inventions, wherein the first main electrode is connected to an object through which the current flows. Specifically, the object through which current flows can be a wiring to which an element to be driven is connected. Further, a switch for controlling a connection relationship between the transistor and the object may be provided between the transistor and the object. While the first step and / or the second step are being performed, a current is applied to the object in a state in which the transistor and the object are not connected to each other and the appropriate setting is not made. Flowing can be suppressed.

  According to a tenth aspect of the present invention, in the fifth to ninth aspects, the video signal input section is connected to the control electrode through a capacitor in the first step. It is. By using the capacitor, it is possible to avoid setting the potential of the video signal as the potential of the control electrode as it is. Further, the relative potential difference between the potential of the control electrode set in the first step and the potential of the video signal can be held by the capacitor. In the first step, a configuration in which the video signal is set to a reference potential can be particularly preferably employed.

In an eleventh aspect based on the tenth aspect, in the second step, the control signal is connected to the input portion of the video signal via a capacitor.
The potential of the video signal at the lowest level is required to be closer to the potential applied to the second main electrode in the second step than the potential of the video signal in the first step. .

  Particularly preferably, the video signal is set as a reference potential in the first step, and a voltage (capacitance) corresponding to the potential difference (corresponding to the potential amplitude of the video signal) between the modulation potential of the video signal and the reference potential in the second step. Since the video signal input section is connected to the control electrode via the control voltage, the voltage difference is not the same as the potential difference between the modulation potential and the reference potential.) Is added to the control electrode potential set in the first step. It is good to do so.

  A twelfth aspect of the invention is the invention according to any of the fifth to eleventh aspects, wherein the transistor is an FET and the control electrode is a gate of the FET. A configuration in which the transistor is a thin film transistor (TFT) can be suitably employed.

The thirteenth invention
A driving method for driving a display device in which a display element is connected to a wiring,
It is an invention of a driving method of a display device, characterized by having a step of causing a current controlled by the control method of any of the fifth to twelfth inventions to flow through the wiring.

In addition, the fourteenth invention
A transistor having a control electrode and first and second main electrodes;
A first switch for controlling a connection between the control electrode and the first main electrode; and
A capacitor connected to the control electrode;
A current signal output circuit for passing a current having a magnitude corresponding to the potential of the video signal to the first main electrode of the transistor;
A video signal supply circuit for supplying the video signal;
A control circuit for supplying a control signal for controlling the first switch;
Have
The control electrode is connected to the input portion of the video signal supplied by the control circuit via the capacitor, and is configured to be supplied with a predetermined potential to the second main electrode.
The control circuit outputs a control signal for controlling the first switch so as to switch from a state in which the control electrode and the first main electrode are connected to a state in which the control electrode is disconnected, as a reference potential. Is supplied to the first switch during a period in which the video signal is supplied to the input unit,
The video signal supply circuit supplies a video signal having a modulation potential related to video display when the first switch cuts off between the control electrode and the first main electrode. And the absolute value of the potential difference between the lowest potential of the modulation potential related to the video display and the predetermined potential supplied to the second main electrode is the reference potential and the second potential. It is smaller than the absolute value of the potential difference from the predetermined potential supplied to the main electrode.
It is an invention of a drive device characterized by this.

  According to a fifteenth aspect, in the fourteenth aspect, a charging path is provided to further keep the potential of the control electrode away from the potential supplied to the second main electrode without passing through the capacitor. It is an invention. Specifically, this charging path corresponds to a path for supplying a power supply potential (Vcc in the detailed description below) and a switch (transistors M4 and M10 in the detailed description below) provided on the path. .

  According to a sixteenth aspect of the present invention, in the fourteenth or fifteenth aspect, the first main electrode is connected to an object through which the current flows.

In addition, the seventeenth invention
A display device,
The driving device according to any one of the fourteenth to sixteenth inventions;
Wiring connected to the first main electrode;
A display element connected to the wiring;
It is invention of the display apparatus which has this.

  According to the driving circuit of the present invention, good gradation display is realized in the display device.

  FIG. 1 is a block diagram of a display panel of an embodiment of an EL display device using the drive circuit of the present invention. The display device supplies a control signal for controlling each switch of the driving circuit, such as a column scanning control signal, a row scanning control signal, and a horizontal synchronization signal, which is input to the display panel to the outside of the display panel. And a control device 1001 including a supply circuit for supplying the video signal Video. As described above, the control device is composed of an inexpensive circuit with a low driving voltage.

  In the figure, 1 is a current setting circuit, 2 is a pixel, 3 is a column control circuit, 4 is a shift register, 4a is a register, 4b is a sampling signal generation circuit, 5 and 5 'are shift registers, 6 and 7 are gate circuits, 8 to 10 are input circuits, 11 is a data line, 12 and 12 'are scanning lines, 21 is an image display unit, and 22 is a drive circuit.

  One embodiment of the invention according to the present application is the data line that is the line to which the magnitude of the current signal generated by the column control circuit 3 which is a circuit for outputting a current signal and the EL element and the pixel circuit which are display elements are connected. 11 is made different from the magnitude of the current flowing through the current setting circuit 1, whereby the magnitude of the current flowing through the data wiring 11 which is a wiring to which the EL element and the pixel circuit as the display elements are connected is an appropriate value. It is a form to become.

  In another embodiment of the present invention related to the present application, the magnitude of the current signal itself generated by the column control circuit 3 which is a circuit for outputting a current signal is different from the reference potential of the video signal and the black level of the video signal. It is the form which makes it an appropriate value by doing. In this embodiment, the current setting circuit 1 is not necessary.

  These forms can also be used in combination.

  First, an embodiment using the current setting circuit 1 will be described.

  In the display panel of FIG. 1, the image display unit 21 arranges a plurality of pixels 2 in a plurality of rows and a plurality of columns, connects the pixels 2 in each row to the scanning line 12 in common, and connects the pixels 2 in each column to the data line in common. 11 is connected. Note that a set of three pixels 2 each having an EL element that emits R (red), G (green), and B (blue) in the row direction is set as a minimum image display unit.

  The input video information VID includes a video signal Video and a reference signal REF, and includes RGB information. Color information corresponding to the display color of the pixel column is input to the column control circuit 3. The video signal Video has a modulation potential for realizing a desired gradation in a range from luminance 0 corresponding to the lowest level to the highest level with the blanking level as a reference potential. The column control signal HS is composed of a clock signal and a scanning start signal, and is subjected to level conversion in the input circuit 8 and then input to the register 4a of the shift register 4 arranged corresponding to each pixel column.

  The horizontal synchronization signal HD is level-converted in the input circuit 10 and then input to the gate circuits 6 and 7, and control signals are output from the gate circuits 6 and 7, respectively, to the column control circuit 3 and the sampling signal generation circuit 4b. Entered.

  The register 4a outputs a shift pulse in response to the input column control signal HS, and the subsequent sampling signal generation circuit 4b generates a sampling signal in accordance with the input shift pulse and the control signal. The sampling signal output from the sampling signal generation circuit 4b is input to the column control circuit 3 arranged corresponding to each pixel column.

  In the column control circuit 3, the video current i (data) of a predetermined pixel 2 is sampled and held from the video information VID by the input control signal and sampling signal, and the current setting circuit 1 arranged for each data line 11. Supply.

  The row control signal VS is composed of a clock signal and a row scanning start signal, and is subjected to level conversion in the input circuit 9 and then sent to the first stage of the shift register group. In the present embodiment, the row control signal VS is sent to the current setting circuit 1. Since the shift register 5 ′ for sending the control signal VS is arranged in the preceding stage of the shift register 5 corresponding to the first pixel row, the level-converted row control signal VS is input to the shift register 5 ′. The In the shift register group to which the row control signal VS is input, the current setting control signal is output from the shift register 5 ′ to the scanning line 12 ′, and then the scanning signal is sequentially output from the subsequent shift register 5 to the scanning line 12. The

  A feature of the present embodiment is that a current setting circuit 1 is arranged for each data line 11 to correct the video current i (data) applied to each data line 11. 2 and 3 show a configuration example of the current setting circuit 1 used in the present invention. In the figure, P1, P2, and Z are control signals included in the current setting control signal output from the shift register 5 '. Further, i (data) 1 is a video current sampled and held from the video signal Video in the column control circuit 3 in the previous stage, and i (data) 2 is a video current output from the circuit. i (Z) is a correction current. M1 to M5 are transistors. In FIG. 2, M1 to M3 are p-type, M4 and M5 are n-type, and in FIG. 3, M1, M2, and M4 are p-type, and M3 and M5 are n-type. C1 is a capacitor and VCC is a power source.

  FIG. 4 shows a timing chart of the operation of the above circuit.

  In the circuit of FIG. 2, when P1 = H, P2 = L, and Z = L at time t0, M3 and M4 are turned on simultaneously, and M5 is turned off. I (Z) flows through M4 and M3 as the video current i (data) 1 at that time, and the gate capacities and capacitors C1 of M1 and M2 are charged according to the level of the I (Z). Become. Before time t1, P2 = H and when M3 is turned off, the gate voltages of M1 and M2 are fixed. At time t1, when P1 = L and Z = H, M4 is turned off and M5 is turned on. Thus, the pull-up current I (Z) is supplied to the data line 11 as the correction current i (Z) by the gate voltage of M1 held after time t1.

  The basic operation of the circuit of FIG. 3 is the same as that of FIG. 2. When P1 = H, P2 = L, and Z = L at time t0, M2 and M3 are turned on simultaneously, and M4 and M5 are turned off. It becomes. I (Z) flows through M4 and M3, and the gate capacitance and the capacitance C1 of M1 are charged according to the level of I (Z) to become a predetermined voltage. Prior to time t1, when P2 = H and M2 is turned off, the gate voltage of M1 is fixed. At time t1, when P1 = L and Z = H, M3 is turned off and M4 and M5 are turned on. Thus, the pull-up current I (Z) is supplied to the data line 11 by the gate voltage of M1 held after time t1.

  The video signal Video includes non-display data related to display and display data related to display. In FIG. 4, .about.t1 is a blanking period, and the video current i (data) 1 output from the column control circuit 3 in this period is a current I (Z) that is not related to display. After time t1, a current having a value corresponding to the display data of the pixels in each row is output. In t1 to t2, t2 to t3, t3 to t4..., currents I (1), I (2) corresponding to display data corresponding to the pixels 21 in the first row, the second row, the third row,. I (3)... Is output. Incidentally, I (3) is a current corresponding to display data for black display.

  In FIG. 4A, the current I (3) corresponding to the black level is preferably set to 0, and according to another embodiment described later, this can be set to 0. In this embodiment, Because of the characteristics of the voltage-current converter included in the column control circuit 3, it cannot be zero. Therefore, if the video current i (data) 1 output from the column control circuit 3 is applied to the data line 11 as it is, I (3) for black display in the period t3 to t4 cannot be set to 0, and The EL element cannot be completely turned off. For this reason, the brightness of the black level of the display image increases, and the D range of the display image cannot be secured.

  In the present embodiment, the current setting circuit 1 as illustrated in FIGS. 2 and 3 is arranged, and as shown in FIG. 4A, in the current setting circuit 1 at t0 to t1 during the blanking period. By programming the current I (Z) corresponding to the non-display data, the correction current i (Z) is set to I (Z), and the correction current I (Z) is supplied to the data line 11 after time t1. Is done. As a result, the video current i (data) 2 output from the current setting circuit 1 to the data line 11 is derived from the video current i (data) 1 output from the column control circuit 3 except for the period from t0 to t1. The current is obtained by subtracting I (Z). Therefore, the video current i (data) 2 for black display during the period from t3 to t4 can be made 0 or remarkably close to 0, and the D range of the display image can be improved.

  FIG. 4B shows a case where the level of non-display data in the blanking period is set higher than the level of black display data in advance. In this case, the correction current I (Z set at t0 to t1 is set. ) Also increases and becomes higher than the video current I (3) for black display, so that the video current i (data) 2 in the period from t3 to t4 becomes a pull-up current. As a result, the supply of current to the EL element of the black display pixel 2 can be reliably cut off. In the current programming operation in the current setting circuit 1, the correction current I (Z) may not be accurately extracted as the drive current, and the correction current I (Z) may cause an error. As shown in FIG. 4B, by setting I (Z) high, even when an error occurs, the current supply to the EL element of the black display pixel 2 can be made zero.

  In this embodiment, the current setting circuit 1 described above is used, and it is not necessary to adjust the output itself from the column control circuit, which is a circuit that outputs a current having a value corresponding to the level of the video signal. There is no need to increase the amplitude to achieve black display. Further, since the current setting circuit 1 has a simple and small-scale configuration that is almost the same as the circuit configuration of the pixel 2 described later, the display panel is not increased in size.

  As the column control circuit 3, in the circuit configuration used conventionally, the voltage / current circuit included in the circuit is composed of TFTs having a large variation in the threshold voltage Vth of the transistor. Is difficult. In the present invention, the circuit configuration shown in FIG. 5 is preferably used as the column control circuit 3.

  In FIG. 5, P3 to P8 are control signals, SPa and SPb are sampling signals, M1 to M12 are transistors, M5 and M11 are p-type, and the others are n-type. C1 to C4 are capacitors, and VCC is a power source. In the following description, the source and drain that are the two main electrodes of the transistor and the gate that is the control electrode are denoted as / S, / D, and / G, respectively.

  Since the column control circuit 3 corresponding to each data wiring adopts a configuration in which each of the column sequential input video signals is converted into a current signal and is simultaneously output from each column control circuit 3, two voltage-current conversion circuits are provided. Have. Specifically, in the circuit of FIG. 5, a first voltage-current conversion circuit composed of transistors M1 to M6 and capacitors C1 and C2, and a second voltage composed of transistors M7 to M12 and capacitors C3 and C4. It has a current conversion circuit.

  In the circuit of FIG. 5, the video signal Video is input to M1 / S and M7 / S, and the sampling signals SPa and SPb are input to M1 / G and M7 / G, respectively. M1 / D is connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to the other end of the capacitor C2 whose one end is grounded, and M3 / G, and M3 / S is grounded. M3 / D and M3 / G are connected to M2 / D and M2 / S, and P3 is input to M2 / G. M3 / D is connected to M4 / S, M4 / D is connected to M5 / D, M5 / S is connected to VCC, and M5 / D and M5 / G are short-circuited. P4 is input to M4 / G. Further, M6 / S is connected to M3 / D, M6 / D is connected to the video current i (data) terminal, and P5 is input to M6 / G.

  On the other hand, M7 / D is connected to one end of the capacitor C3, the other end of the capacitor C3 is connected to the other end of C4 whose one end is grounded and M9 / G, and M9 / S is grounded. M9 / D and M9 / G are connected to M8 / D and M8 / S, and P6 is input to M8 / G. M9 / D is connected to M10 / S, M10 / D is connected to M11 / D, M11 / S is connected to VCC, and M11 / D and M11 / G are short-circuited. P7 is input to M10 / G. Further, M9 / D is connected to M12 / S, M12 / D is connected to the video current i (data) terminal, and P8 is input to M12 / G. The gate size (width: W, length: L) and capacitance of each transistor are as follows: M1 = M7, M2 = M8, M3 = M9, M4 = M10, M5 = M11, M6 = M12, C1 = C3, C2 = C4 relationship.

  Since the first voltage-current conversion circuit and the second voltage-current conversion circuit perform a common operation except that they are operated alternately, the first voltage-current conversion circuit is taken as an example, and the main functions of each component Will be described.

  The transistor M3 is a transistor that causes a current corresponding to the potential set at the gate, which is the control electrode, to flow to the drain, which is the first main electrode. A data line is connected to the first main electrode via a transistor M6 that is a switch, and a current corresponding to the gate potential of the transistor M3 flows through the data line.

  The transistor M2 is a switch that controls the connection relationship between the gate that is the control electrode of the transistor M3 and the drain that is the first main electrode, and the transistor M3 that is charged via the transistors M4 and M5 that are charging paths from the VCC. By connecting the gate and drain of the transistor M3, the gate potential of the transistor M3 is brought close to the potential (here, ground) supplied to the source which is the second main electrode of the transistor M3. As a result, the gate potential and the source potential of M3 approach the threshold voltage of the transistor M3. Thereafter, the transistor M2 is disconnected.

  At this time, the transistor M1, which is a switch for controlling the connection relationship between the input portion of the video signal Video and the control electrode of the transistor M3, is in a connected state, and the video signal is at a blanking level that is a reference potential.

  Thereafter, when a video signal having a necessary modulation potential is input, a voltage corresponding to the potential difference between the blanking level which is the reference potential and the modulation potential is applied to the gate potential of the transistor M3. Thereby, the gate potential of the transistor M3 corresponding to the modulation potential is set.

  FIG. 6 shows a timing chart of the operation of the circuit of FIG. In the figure, M3 / G and M9 / G indicate gate voltages of M3 and M9, respectively. FIG. 6 shows the operation related to the video signals for two rows.

Just before time t1, SPa = L, SPb = L,
P3 = L, P4 = L, P5 = H, P6 = L, P7 = H, P8 = L
It is. Therefore, each transistor
M1: off, M2: off, M4: off, M6: on,
M7: off, M8: off, M10: on, M12: off. At this time, M3 and M9 are driven by the holding voltages Va1 and Vb1 charged in the capacities associated with the respective gates, and the M3 / D current Ia1 is output as the video current i (data). The M9 / D current is supplied to M11 / D and M11 / G and becomes a constant value.

Time t1
SPa = H, P4 = H, P5 = L, P7 = L, and P8 = H, and the video signal Video is the blanking signal VBL in the blanking period. Therefore, each transistor
M1: on, M2: off, M4: on, M6: off,
M7: off, M8: off, M10: off, M12: on. At this time, the M9 / D current Ib1 driven by the Mb / G voltage Vb1 is output as the video current i (data) instead of the M3 / D current Ia1. Since the video current i (data) passes through the column length of the image display unit 21 and is connected to EL elements corresponding to a large number of pixels in each column, a large parasitic capacitance must be driven, so that the effective current supply transition Ia1 → Ib1 takes time. Before time t2, P3 = H and M2: is turned on, and M3 / G is charged by M5 in a short period from this time to time t2.

Time t2
Since P4 = L and M4 is turned off, the charging operation of M3 / G by M5 is stopped. At this time, M2 is in a connected state, and M3 / G is asymptotic to its own threshold voltage Vth. Self-discharge operation is performed.

Time t3
SPa = L and M1 is turned off. Prior to time t4, P3 = L and M2 = off, and at this point, the self-discharge operation of M3 ends. During this period from time t4 to time t4, both M2 and M4 are turned off, and the M3 / D current rapidly changes to the L level. Therefore, M3 / G has a slight voltage as shown in FIG. Causes a descent.

Time t4
Since P4 = H and M4: is turned on, the M3 / D current rises again, and M3 / G rises again to almost return to the original state (Vrsa). Since M3 / G is near the threshold voltage Vth of itself at this time, M3 / D is almost zero.

~ Time t7
During the period from time t4 to t7, the sampling signal SPa corresponding to each column is generated. SPb is not generated. At time t5 to t6, the M3 / G voltage generated near the threshold voltage Vth after the sampling signal of the corresponding pixel column is generated and the blanking level (VBL) as a reference at this time The transition voltage ΔV1 is changed according to the signal level d1. ΔV1 is schematically represented by the following equation.

    ΔV1 = d1 × C1 / (C1 + C2 + C (M3))

  C (M3) indicates an input capacity of M3 / G.

  When the corresponding SPa is changed to L, M1: is turned off, and the voltage M3 / G is again held by changing to Va2 which is slightly dropped due to the parasitic capacitance operation of M1.

Time t7
SPb = H, P4 = L, P5 = H, P7 = H, P8 = L, and the video signal Video is the blanking signal VBL in the blanking period. Therefore, each transistor
M1: off, M2: off, M4: off, M6: on M7: on, M8: off, M10: on, M12: off,
It becomes. At this time, the M3 / D current Ia2 driven by the Va2 of the M3 / G voltage is output as the video current i (data) instead of the M9 / D current Ib1. Since the video current i (data) passes through the column length of the image display unit 21 and is connected to the EL elements corresponding to a large number of pixels in each column, a large parasitic capacitance must be driven, so that the effective current supply transition Ib1 → Ia2 takes time. Prior to time t8, P6 = H, M8: is turned on, and M9 / G is charged by M11 in a short period from this time to time t8.

Time t8
Since P7 = L and M10 is turned off, the charging operation by M11 of M9 / G is stopped, and M9 / G performs a self-discharge operation so as to approach the threshold voltage Vth of itself.

Time t9
SPb = L and M7 is turned off. Prior to time t10, P6 = L and M8 = off, and at this point, the self-discharge operation of M9 ends. During the period from this time to time t10, both M8 and M10 are turned off, and the M9 / D current rapidly changes to the L level. Therefore, M9 / G has a slight voltage as shown in FIG. Causes a descent.

Time t10
Since P5 = H and M10: is turned on, the M9 / D current rises again, and M9 / G rises again to almost return to the original state (Vrsb). At this time point, M9 / D is almost 0 because M9 / G is near its own threshold voltage Vth.

~ Time t13
During the period from time t10 to t13, the sampling signal SPb corresponding to each column is generated. SPa is not generated. From time t11 to t12, a sampling signal of the corresponding pixel column is generated, and the M9 / G voltage held near its threshold voltage Vth is an image based on the blanking level (VBL) at this time. The transition voltage ΔV2 is changed according to the signal level d2. ΔV2 is schematically represented by the following equation.

    ΔV2 = d2 × C3 / (C3 + C4 + C (M9))

  C (M9) indicates an input capacity of M9 / G.

  When the corresponding SPb is changed to L, M7 is turned off, and the voltage M9 / G is again held by changing to Vb2 which is slightly lowered by the parasitic capacitance operation of M7. Further, immediately before time t13, the video signal Video returns to the blanking level VBL.

  Thereafter, the operation from t1 to t12 is repeated with t13 as a new t1.

  In the circuit of FIG. 5, the capacitors C2 and C4 may be realized only by the gate input capacitors (channel capacitors) of M3 and M9. In this case, the capacitors C2 and C4 may not be provided. In FIG. 6, the change timings of P3 and P4 may be equal to SPa at times t1 and t3. Further, the change timings of P6 and P7 may be equal to SPb at times t8 and t11. In FIG. 5, there may be no M3 / D and M9 / D bias circuits and M3 / G and M9 / G charging circuits composed of P4, M4, M5 and P7, M10 and M11.

  With the above circuit and operation, the video signal Video can be converted into a line-sequential video current i (data).

  In the circuit configuration of FIG. 5, in the case where the transistors M1 to M12 are configured by TFTs, it has been difficult in the past to reduce the current at the time of black display to 0 due to variations in the threshold voltage Vth of the TFTs.

  FIG. 7 shows the Vgs (gate-source voltage) -Id (drain voltage) characteristics of the n-type transistor. In the figure, the vertical axis is indicated by a logarithmic axis.

  When M3 and M9 in FIG. 5 are M3 / G and M9 / G voltages V0 at the threshold voltage Vth reset completion timing shown at times t3 and t9 in FIG. 6 and the output current at this time is I0, I0 cannot be zero. The reason is that M3 and M9 are not ideal transistors having the characteristics shown by the broken lines in FIG. 7, so that the threshold voltage Vth is not clear and has the characteristics of the subthreshold region [2]. Because.

  In the present embodiment, by correcting the video current i (data) using the current setting circuit 1, it is possible to perform black display without reducing the minimum level of the video signal Video with respect to the blanking level VBL. The supply current to the data line 11 can be suppressed to 0 or close to 0. (FIG. 8B). Further, as shown in FIG. 8C, by supplying a signal input to the current setting circuit 1 larger than the blanking signal VBL during the current programming period, the supply current to the data line 11 at the time of black display Becomes a pull-up current (negative current), and the current supply to the EL element is surely zero in the corresponding pixel, and is turned off.

  In the above embodiment, the configuration in which one current setting circuit 1 is arranged for each data line is shown. However, the present invention is not limited to this, and if a predetermined correction can be performed, Two or more circuits may be arranged. Further, the current setting circuit 1 may be installed outside the image display unit 21 in the vertical scanning direction. In an apparatus capable of selecting the vertical scanning direction, the current setting circuit 1 may be installed outside the top and bottom of the image display unit 21. good.

As described above, the corrected video current i (data) 2 is supplied to each data line 11 and input to the pixels in the selected pixel row, and the EL elements of each pixel emit light at a predetermined level.
Next, another embodiment of the invention will be described.

  Specifically, as described at the beginning, the light emission at the black level can be suppressed without using the current setting circuit 1 employed in the above embodiment.

  The configuration of the column control circuit 3 which is a voltage-current conversion circuit used in this embodiment is the same as that in the above embodiment. The difference is that by making the black level of the video signal different from the blanking level which is the reference potential, the voltage-current conversion circuit makes the current output corresponding to the black level modulation potential close to zero. Specifically, the absolute value of the potential difference between the black level potential of the video signal and the source potential of the transistors M3 and M9 that performs voltage-current conversion is the source of the transistors M3 and M9 that perform voltage-current conversion with the blanking level potential. The absolute value of the potential difference from the potential is made smaller. Here, in particular, the minimum level of the modulation potential of the video signal is lower than the level of the video signal (the reference potential, which is the blanking level here) when the threshold values of the transistors M3 and M9 of the voltage-current converter circuit are reset. As a result, the voltage between the source and gate of the transistors M3 and M9 set when the modulation potential of the video signal is at the lowest level is made smaller than the voltage between the source and gate at the end of the threshold reset. ing.

  FIG. 8A shows the signal waveform of the video signal Video at this time. ΔV in the figure is the amplitude of the video signal Video.

  Hereinafter, a configuration of a pixel circuit that can be adopted in any of the above-described embodiments (a mode in which the current setting circuit 1 is used and a mode in which the minimum level of the video signal is lower than the reference level) will be described.

  9 and 10 show examples of the circuit configuration of the pixel, and FIG. 11 shows a timing chart of the operation of the circuit. In the figure, M1 to M4 are transistors. In FIG. 9, M1 to M3 are p-type and M4 is n-type. In the following description, the source, drain, and gate of the transistor will be referred to as / S, / D, and / G, respectively. In FIG. 10, M1, M2, and M4 are p-type and M3 is n-type. Further, C1 is a capacitor, VCC is a power source, 91 is an EL element, and P9 and P10 are scanning signals. The pixel corresponds to a pixel on the m-th row.

  In the circuit of FIG. 9, at time t0, P9 = H and P10 = L, both M3 and M4 are turned on, i (m) supplied to the data line 11 flows to M2, and M2 / G becomes i (m ) Is set to a voltage according to the level. At time t1, P10 = H, M3 is turned off, and the M2 / G voltage is held by the capacitor C1. At time t2, P9 = L, M4 is turned off, no current is supplied from the data line 11 to the circuit, and the supply is switched to the pixel of the (m + 1) th row. At the same time, the M1 / G voltage is held at C1, and a current of i (m) level from VCC is supplied to the EL element 91 to continue light emission.

  In the circuit of FIG. 10, at time t0, P9 = H and P10 = L, both M2 and M3 are turned on, i (m) supplied to the data line 11 flows to M2, and M1 / G is i ( The voltage is set according to the level of m). At time t1, P10 = H, M2 is turned off, and the M1 / G voltage is held by the capacitor C1. At time t2, P9 = L, M3 is turned off, no current is supplied from the data line 11 to the circuit, and the supply is switched to the pixels of the (m + 1) th row. At the same time, M4 is turned on, and the M1 / G voltage is held at C1, so that an i (m) level current is supplied from VCC to the EL element 91, and light emission continues.

  The transistor constituting the driving circuit of the present invention is usually a TFT, and the transistor shown in the above embodiment is generally a TFT. However, a field effect transistor other than a TFT may be used. Is possible.

It is a block diagram of the display panel of one Embodiment of EL display apparatus of this invention. It is an example of a structure of the current setting circuit used for the drive circuit of this invention. It is another example of a structure of the current setting circuit used for the drive circuit of this invention. 4 is a timing chart of the operation of the current setting circuit of FIGS. 2 and 3. It is a structural example of the column control circuit used for the drive circuit of this invention. 6 is a timing chart of the operation of the column control circuit of FIG. It is a figure which shows the Vgs-Id characteristic of an n-type transistor. It is a figure which shows the signal waveform of the video signal Video in this invention and the conventional apparatus. 2 is a circuit configuration example of a pixel used in an EL display device of the present invention. 6 is another circuit configuration example of a pixel used in the EL display device of the present invention. 12 is a timing chart of the operation of the pixel circuit in FIGS. 9 and 11.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Current setting circuit 2 Pixel 3 Column control circuit 4 Shift register 4a Register 4b Sampling signal generation circuit 5, 5 'Shift register 6, 7 Gate circuit 8-10 Input circuit 11 Data line 12, 12' Scan line 21 Image display part 22 Drive circuit unit 91 EL element 1001 Controller HD Horizontal synchronization signal HS Column control signal i (data) Video current M1 to M12 Transistors P1 to P8 Control signal P9 and P10 Scan signal REF Reference signal SPa, SPb Sampling signal VB Reference current setting bias VCC power supply VID video information Video video signal VS row control signal Z control signal

Claims (17)

A plurality of pixels are arranged in a matrix, an image display unit is provided in which pixels in each row are connected to a scanning line in common, and pixels in each column are connected to a data line in common. In a display device that performs display by applying a video current of a level corresponding to the display of each pixel in a row to a data line to which the pixel is connected, a drive circuit for driving each pixel,
At least one current setting circuit is connected to each data line. In the current setting circuit, a current flowing through the data line is detected in a period not involved in display, and the detected current is used as a correction current, and the current applied to display is data. A drive circuit, wherein a video current corrected by the correction current is applied to a data line during a period to be applied to the line.   A transistor for supplying the correction current is provided, and a gate voltage of the transistor for supplying the correction current is set by a current flowing through the data line in a period not related to the display. 2. The drive circuit according to claim 1, wherein a current obtained by subtracting a correction current supplied from the transistor from a video current before correction is supplied as a video current in a period to be applied to the data line.   3. A display device comprising the drive circuit according to claim 1 or 2, wherein each pixel includes an element that emits light in response to an injection current.   The display device according to claim 3, wherein the element is an electroluminescence element. In a circuit including a transistor having a control electrode and first and second main electrodes, a control method for controlling a current flowing through the first main electrode,
The potential of the control electrode is brought close to the potential applied to the second main electrode, and the potential difference between the potential of the control electrode and the potential applied to the second main electrode is set to the threshold voltage of the transistor. A first step of approaching;
A second step of setting, as the potential of the control electrode, a potential obtained by adding a voltage corresponding to the potential amplitude of the video signal to the potential of the control electrode set in the first step;
Have
The absolute value of the difference between the potential set as the potential of the control electrode when the video signal is at the lowest level in the second step and the potential applied to the second main electrode in the second step Is smaller than the absolute value of the difference between the potential of the control electrode set in the first step and the potential applied to the second main electrode in the second step. .   The said 1st step WHEREIN: The electric potential of the said control electrode is brought close to the electric potential applied to a said 2nd main electrode by making the said 1st main electrode and the said control electrode into a connection state. Control method. In a circuit including a transistor having a control electrode and first and second main electrodes, a control method for controlling a current flowing through the first main electrode,
A first step of bringing the control electrode and the first main electrode into a connected state, thereby bringing the potential of the control electrode close to the potential applied to the second main electrode;
A second step of setting, as the potential of the control electrode, a potential obtained by adding a voltage corresponding to the potential amplitude of the video signal to the potential of the control electrode set in the first step;
Have
The absolute value of the difference between the potential set as the potential of the control electrode when the video signal is at the lowest level in the second step and the potential applied to the second main electrode in the second step Is smaller than the absolute value of the difference between the potential of the control electrode set in the first step and the potential applied to the second main electrode in the second step. .   Prior to the first step, the potential of the control electrode is larger than the potential of the control electrode set in the first step and the potential applied to the second main electrode is larger. The control method according to claim 5, further comprising a step of setting to:   The control method according to claim 5, wherein an object through which the current flows is connected to the first main electrode.   10. The control method according to claim 5, wherein in the first step, an input portion of the video signal is connected to the control electrode through a capacitor. In the second step, the input portion of the video signal is connected to the control electrode through a capacitor,
The control method according to claim 10, wherein the potential of the video signal at the lowest level is closer to the potential applied to the second main electrode in the second step than the potential of the video signal in the first step. .   The control method according to claim 5, wherein the transistor is an FET, and the control electrode is a gate of the FET. A driving method for driving a display device in which a display element is connected to a wiring,
13. A method for driving a display device, comprising the step of flowing a current controlled by the control method according to claim 5 through the wiring. A transistor having a control electrode and first and second main electrodes;
A first switch for controlling a connection between the control electrode and the first main electrode; and
A capacitor connected to the control electrode;
A current signal output circuit for passing a current having a magnitude corresponding to the potential of the video signal to the first main electrode of the transistor;
A video signal supply circuit for supplying the video signal;
A control circuit for supplying a control signal for controlling the first switch;
Have
The control electrode is connected to the input portion of the video signal supplied by the control circuit via the capacitor, and is configured to be supplied with a predetermined potential to the second main electrode.
The control circuit outputs a control signal for controlling the first switch so as to switch from a state in which the control electrode and the first main electrode are connected to a state in which the control electrode is disconnected, as a reference potential. Is supplied to the first switch during a period in which the video signal is supplied to the input unit,
The video signal supply circuit supplies a video signal having a modulation potential related to video display when the first switch cuts off between the control electrode and the first main electrode. And the absolute value of the potential difference between the lowest potential of the modulation potential relating to the video display and the predetermined potential supplied to the second main electrode is the reference potential and the second potential. It is smaller than the absolute value of the potential difference from the predetermined potential supplied to the main electrode.
A drive device characterized by that.   The drive device according to claim 14, further comprising a charging path for keeping the potential of the control electrode away from the potential supplied to the second main electrode without passing through the capacitor.   The drive device according to claim 14 or 15, wherein an object through which the current flows is connected to the first main electrode. A display device,
A driving device according to any one of claims 14 to 16,
Wiring connected to the first main electrode;
A display element connected to the wiring;
A display device.

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