JP2005143197A - PWM signal duty ratio control method, duty ratio control circuit, and DC-DC converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PWM signal time ratio control method and a time ratio control circuit capable of limiting an on-time ratio with high accuracy.
A duty ratio control circuit unit of a DC-DC converter includes an error amplifier 11 that generates an error output signal Vfb, and a comparator that generates a PWM signal Vpwm1 by comparing the error output signal Vfb with a triangular wave signal Vosc1 having a predetermined period. 12, a triangular wave signal Vosc1 having a predetermined period and a triangular wave oscillation circuit 13 for generating a first pulse signal Vosc2 synchronized with the triangular wave signal Vosc1, and a second delay time td with respect to the first pulse signal Vosc2 A delay circuit 14 for generating a pulse signal Vd, a logic circuit 15 for forcibly turning off the PWM signal Vpwm1 by the first pulse signal Vosc2, and forcibly turning off the PWM signal Vpwm1 by the second pulse signal Vd, and an output buffer 16.
[Selection] Figure 1

Description

  The present invention relates to a PWM signal time ratio setting method for generating a PWM signal in which the maximum value of the on-time ratio is limited, and a time ratio control circuit that enables PWM signal time ratio control in a DC-DC converter or the like. And a DC-DC converter.

  A DC-DC converter that can convert a DC voltage into a voltage of an arbitrary DC level is used in power supply devices for various electronic devices with a reduction in size and efficiency, and the use range thereof is expanded. Therefore, there is a demand for a DC-DC converter with a wider operating range and output setting voltage range.

  FIG. 6 is a circuit diagram showing a conventional PWM (Pulse Width Modulation) step-up DC-DC converter. The DC-DC converter circuit unit 51 that boosts the DC input voltage Vin and outputs it as an output voltage Vout includes an output transistor M1, a reactor L1, a diode D1, and a capacitor C1 as switching elements made of N-channel MOS transistors. A DC input voltage Vin is applied to the drain of the output transistor M1 through the reactor L1. The source of the output transistor M1 is connected to the ground. The diode D1 has an anode connected to the drain of the output transistor M1, and a cathode connected to the output terminal P0. The capacitor C1 is connected between the output terminal P0 and the ground.

  In the DC-DC converter circuit unit 51, the output transistor M1 is controlled to be turned on / off, whereby the output voltage Vout output from the output terminal P0 is boosted to a voltage higher than the input voltage Vin. By changing the ratio of the on time Ton and the off time Toff of the output transistor M1, the output voltage Vout can be controlled to a predetermined set voltage.

Here, regarding the relationship of the output voltage Vout with respect to the input voltage Vin,
Vout = {(Ton + Toff) / Toff} Vin
= Vin / Doff
It can be expressed as Doff is an off-duty ratio, and can be defined as the reciprocal of (Ton + Toff) / Toff, that is, Toff / (Ton + Toff).

The on-duty ratio Don is defined as Ton / (Ton + Toff). Therefore, since Doff + Don = 1,
Vout = Vin / Doff = Vin / (1-Don)
It becomes.

  The DC-DC converter shown in FIG. 6 includes an output voltage detection circuit unit 52 and a time ratio control circuit unit 53 in order to control the output voltage Vout from the DC-DC converter circuit unit 51 to a predetermined set voltage. ing.

  The output voltage detection circuit unit 52 includes detection resistors R1 and R2. The detection resistors R1 and R2 are connected in series, and the series circuit is connected between the output terminal P0 and the ground. The detection resistors R1 and R2 connected in series divide the output voltage Vout and feed back the divided voltage (detection voltage) Vf to the time ratio control circuit unit 53.

  The time ratio control circuit unit 53 includes an error amplifier circuit 54, a reference voltage circuit E1, a triangular wave oscillation circuit 56, a dead time voltage circuit E2, a PWM comparator 58, and an output buffer 59.

  In the error amplifying circuit 54, the detection voltage Vf obtained by dividing the output voltage Vout at a constant voltage dividing ratio is compared with a predetermined reference voltage Vref1 output from the reference voltage circuit E1, and the difference voltage between the two voltages Vf and Vref is compared. Is output to the PWM comparator 58.

  FIG. 7 is a waveform diagram showing each voltage signal waveform of the duty ratio control circuit unit 53. As shown here, the triangular wave oscillation circuit 56 outputs a triangular wave signal Vosc1 having an amplitude within a range of a constant voltage value to the PWM comparator 58. The dead time voltage circuit E2 outputs the maximum duty setting voltage Vdmax1 to the PWM comparator 58. The maximum duty setting voltage Vdmax1 is a voltage that sets the maximum value of the on-time ratio (on-duty ratio) when the output transistor M1 is on / off-controlled.

  The PWM comparator 58 receives the error output voltage Vfb, the triangular wave signal Vosc1 and the maximum duty setting voltage Vdmax1. The PWM comparator 58 compares the smaller value of the error output voltage Vfb and the maximum duty setting voltage Vdmax1 with the value of the triangular wave signal Vosc1. In the DC-DC converter shown in FIG. 6, normally, the error output voltage Vfb is smaller than the maximum duty setting voltage Vdmax1, and therefore the PWM comparator 58 compares between the error output voltage Vfb and the triangular wave signal Vosc1.

  As shown in FIG. 7A, an H level signal is output as the PWM signal Vpwm during a period in which the triangular wave signal Vosc1 is smaller than the error output voltage Vfb. However, when the triangular wave signal Vosc1 becomes larger than the error output voltage Vfb, The signal Vpwm becomes L level.

  As described above, the error output voltage Vfb increases as the detection voltage Vf becomes lower than the preset reference voltage Vref1, and the period in which the PWM signal Vpwm is in the H level state (ON time: Ton) is in the L level state (OFF). The on-duty ratio Don (= Ton / (Ton + Toff)) increases as the time becomes longer than time (Toff). On the other hand, when the error output voltage Vfb is small, the detection voltage Vf is larger than the preset reference voltage Vref1, the ratio of the L level state of the PWM signal Vpwm is larger than that in the H level state, and the on-duty ratio Don is Get smaller.

  The PWM signal Vpwm output from the PWM comparator 58 is output to the gate of the output transistor M1 via the output buffer 59. The output transistor M1 is turned on / off according to the waveform of the PWM signal Vpwm, the AC voltage generated at the connection point between the output transistor M1 and the diode D1 is smoothed by the inductor L1 and the capacitor C1, and a predetermined output voltage Vout is output from the output terminal P0. Supplied to the load.

  Incidentally, as shown in FIG. 7B, the error output voltage Vfb of the error amplifier circuit 54 may be larger than the maximum duty setting voltage Vdmax1 depending on the load state of the output terminal P0. In such a case, if the PWM signal Vpwm becomes a duty cycle of 100% and the output transistor M1 is always turned on, the output transistor M1 is destroyed and the function as the converter circuit unit 51 is stopped. Therefore, the PWM comparator 58 compares the maximum duty setting voltage Vdmax1 and the triangular wave signal Vosc1, and even when the error output voltage Vfb is larger than the maximum duty setting voltage Vdmax1, the PWM signal Vpwm is in the H level state. The period of time (ON time: Ton) is limited to a rate of less than 100%, for example, about 80%.

  Thus, in the DC-DC converter shown in FIG. 6, the maximum on-duty ratio Don is determined by the maximum duty setting voltage Vdmax1, but since this maximum value is determined by the maximum duty setting voltage Vdmax1, The value of the maximum duty setting voltage Vdmax1 is preferably smaller than the maximum value of the triangular wave signal Vosc1 and as close as possible to the maximum value. However, the maximum value of the triangular wave signal Vosc1 may fall below the maximum duty setting voltage Vdmax1 due to variations in the peak value of the triangular wave signal Vosc1, the input offset voltage of the PWM comparator 58, and the like.

  The DC-DC converter shown in FIG. 8 is configured by replacing the PWM comparator 58 with first and second comparators 60 and 61 and an AND circuit 62. When configured in this way, the maximum duty setting voltage Vdmax1 and the triangular wave signal Vosc1 are compared by the second comparator 61, and narrow so as to have a predetermined maximum on-time ratio in advance (off time: Toff = t). The pulse signal Vdmax can be generated. The maximum on-time ratio is set based on the pulse width of the pulse signal Vdmax, and the maximum on-time ratio does not fluctuate from time to time without being affected by the level of other signals. Can be set.

  Here, as shown in FIG. 9, the AND circuit 62 compares the pulse signal Vdmax and the PWM signal Vpwm1 from the PWM comparator 60, and outputs the shorter one of the high level (High) period from the AND circuit 62. Therefore, the maximum on-time ratio is limited.

  However, this method does not solve the problem that the accuracy of the maximum duty limit value deteriorates due to the peak value of the triangular wave signal Vosc1, the offset voltage of the comparator 61, and the like, as in FIG.

  To solve such a problem, the invention described in Patent Document 1 does not use the maximum duty setting voltage Vdmax1 but uses the pulse signal Vps synchronized with the triangular wave signal Vosc1 as shown in FIG. There has been proposed a duty ratio setting circuit that does not fluctuate the on-time ratio and can obtain a large maximum on-time ratio. FIG. 11 shows the voltage waveform of each part of the duty ratio setting circuit shown in FIG.

In this duty ratio setting circuit, since the maximum value of the on-time ratio is set by the pulse width t of the pulse signal Vps output from the pulse generation circuit 63, the pulse generation circuit 63 only adjusts the pulse width t. It is possible to easily adjust the maximum value of the on-time ratio. Further, in the pulse signal Vps having a narrow width (ON time: Ton = t), the pulse width t is not affected by the level fluctuation of other signals, so that the maximum value of the ON time ratio does not fluctuate from time to time. .
JP 2000-217340 A (paragraph numbers [0061] to [0062], FIG. 1)

  However, the duty ratio setting circuit shown in FIG. 10 uses the pulse signal Vps when the switching frequency is a high frequency in the MHz band, or when the on-time ratio (on-duty ratio) is set to 90% or more. Therefore, it is necessary to generate a pulse width t with a narrow width of nanosecond class.

  However, in order to generate the pulse signal Vps with a pulse width of nanosecond class, the pulse is transmitted from the triangular wave oscillation circuit 56 that generates the triangular wave signal Vosc1 through many stages of gate circuits and the like. However, there is a problem that the pulse width is changed in the middle or the pulse itself disappears in the worst case. In addition, once a narrow pulse is generated, there is a problem that an accurate pulse synchronized with the triangular wave signal Vosc1 cannot be generated unless all the logic circuits in the subsequent stages are made to respond at high speed.

  The present invention has been made in view of such a point, and a PWM signal that limits the on-time ratio with high accuracy without generating a maximum duty ratio setting voltage or a duty ratio setting pulse signal. It is an object of the present invention to provide a time ratio control method and a time ratio control circuit.

  In order to solve the above problem, the present invention sets the maximum value of the on-time ratio at which the PWM signal changes when the PWM signal is generated by comparing the error output signal with a triangular wave signal having a predetermined period. In the PWM signal duty ratio setting method, based on the first pulse signal generated in synchronization with the triangular wave signal and the second pulse signal generated with a predetermined delay time with respect to the first pulse signal, The maximum value of the on-time ratio is limited.

  The duty ratio control circuit according to the present invention includes an error amplifier that generates an error output signal, a comparator that generates a PWM signal by comparing the error output signal with a triangular wave signal having a predetermined period, a triangular wave signal having the predetermined period, And a triangular wave oscillation circuit that generates a first pulse signal synchronized with the triangular wave signal, a delay circuit that generates a second pulse signal having a predetermined delay time with respect to the first pulse signal, and the first circuit The PWM signal is forcibly turned off by a pulse signal, and a logic circuit for canceling the forced off of the PWM signal by the second pulse signal is provided.

  Furthermore, the DC-DC converter according to the present invention includes a switching element, and the switching element is controlled by a duty ratio, thereby converting an input voltage into an output voltage having a voltage value different from the input voltage. An output voltage detection circuit unit that detects a voltage value of the output voltage, an error amplifier that generates an error output signal based on the detection voltage from the detection circuit unit, and a triangular wave signal having a predetermined cycle as the error output signal In comparison, a comparator that generates a PWM signal for controlling the duty ratio of the switching element, a triangular wave signal having a predetermined period, and a triangular wave oscillation circuit that generates a first pulse signal synchronized with the triangular wave signal; A delay circuit for generating a second pulse signal having a predetermined delay time with respect to one pulse signal, and the first pulse Wherein together to force off the PWM signal, it is constituted by a logic circuit for releasing the forced off of the PWM signal by the second pulse signal by No..

  According to the present invention, without using the maximum duty ratio setting voltage or the pulse signal for setting the duty ratio, the on-time ratio can be set with a predetermined delay time set between the first pulse signal and the second pulse signal. A maximum value can be set.

  Therefore, even when the set frequency of the PWM signal is a high frequency such as the MHz band, the on-time ratio can be limited with high accuracy. Further, since the maximum on-time ratio does not fluctuate from time to time without being influenced by the level of other signals, a large maximum on-time ratio can be set.

  Further, according to the present invention, since the on-time ratio is limited at the final stage of the control circuit that controls the DC-DC converter circuit, the pulse width may change in the middle or the pulse itself may disappear. There is no fear.

  Therefore, even when applied to a high-frequency switching power supply, the on-time ratio can be limited with high accuracy.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing the basic configuration of a DC-DC converter according to the present invention.
In the DC-DC converter shown in FIG. 1, the duty ratio control circuit unit generates the PWM signal Vpwm1 by comparing the error amplifier 11 that generates the error output signal Vfb and the error output signal Vfb with the triangular wave signal Vosc1 having a predetermined period. The comparator 12, the triangular wave signal Vosc1 having a predetermined period and a triangular wave oscillation circuit 13 for generating a first pulse signal Vosc2 synchronized with the triangular wave signal Vosc1, and a second delay time td with respect to the first pulse signal Vosc2 A delay circuit 14 that generates the pulse signal Vd of the first pulse signal, a logic circuit 15 that forcibly turns off the PWM signal Vpwm1 by the first pulse signal Vosc2, and cancels the forced off of the PWM signal Vpwm1 by the second pulse signal Vd, and an output And a buffer 16.

  This DC-DC converter is characterized by the configuration of such a time ratio control circuit unit, and includes a DC-DC converter circuit unit comprising an output transistor M1, a reactor L1, a diode D1 and a capacitor C1, and an output comprising detection resistors R1 and R2. About a voltage detection circuit part, it is the same as the structure of the conventional DC-DC converter (FIG. 6). Therefore, in the following, the duty ratio control circuit unit will be described in detail, and the other components will be denoted by the same reference numerals as those used in the DC-DC converter shown in FIG. 6, and detailed description thereof will be omitted.

  The error amplifier 11 receives a voltage (detection voltage) Vf from the output voltage detection circuit unit and a predetermined reference voltage Vref1 output from the reference voltage circuit E1. The reference voltage Vref1 output from the reference voltage circuit E1 is equal to the value of the detection voltage Vf output from the output voltage detection circuit unit when the output voltage Vout output from the output terminal P0 outputs a predetermined set voltage. Matching voltage value is set.

  The error amplifier 11 compares the detection voltage Vf and the reference voltage Vref1, and outputs an error output signal Vfb as a control voltage obtained by amplifying the difference voltage between the two voltages Vf and Vref1 to the comparator 12. The error amplifier 11 outputs the error output signal Vfb so that the detection voltage Vf becomes a value that matches the reference voltage Vref1 (that is, the output voltage Vout becomes a predetermined set voltage). Then, the error amplifier 11 outputs an error output signal Vfb that becomes smaller than the reference value as the detection voltage Vf becomes larger than the reference voltage Vref1. On the contrary, the error amplifier 11 outputs an error output signal Vfb that becomes larger than the reference value as the detection voltage Vf becomes smaller than the reference voltage Vref1.

  The triangular wave oscillating circuit 13 includes a triangular wave signal Vosc1 as a triangular wave oscillating signal having a constant voltage value range with a predetermined period T, and a first pulse generated as a rectangular wave in synchronization with the triangular wave signal Vosc1. The signal Vosc2 is output.

  FIG. 2 is a circuit diagram showing an example of the triangular wave oscillation circuit 13. This triangular wave oscillation circuit 13 is provided between the power supply voltage Vdd and the ground, between the series circuit of the constant current source IB1, the switch elements S1 and S2, and the constant current source IB2, and the connection point between the switch elements S1 and S2 and the ground. A charging / discharging capacitor C2 and a hysteresis comparator 21 for controlling the switching elements S1, S2 are provided.

  Here, when the switch elements S1 and S2 are alternately turned on and off, the capacitor C2 oscillates between the upper limit voltage Voscp and the lower limit voltage Voscm at the connection point of the switch elements S1 and S2 by repeating the charging operation and the discharging operation. A triangular wave signal Vosc1 is generated. The triangular wave signal Vosc1 is fed back to the negative input terminal of the hysteresis comparator 21, and the hysteresis comparator 21 compares the triangular wave signal Vosc1 between the upper limit voltage Voscp and the lower limit voltage Voscm applied to the two positive input terminals, respectively. A first pulse signal Vosc2 as a rectangular wave is output.

  Returning to FIG. 1, the triangular wave signal Vosc1 of the triangular wave oscillation circuit 13 and the error output signal Vfb of the error amplifier 11 are input to the comparator 12, and the magnitude of the error output signal Vfb is compared with the value of the triangular wave signal Vosc1. Is done. When the triangular wave signal Vosc1 is smaller than the error output signal Vfb, the PWM signal Vpwm1 is output which is at H level, and when the triangular wave signal Vosc1 is larger than the error output signal Vfb, the PWM signal Vpwm1 is output. The delay circuit 14 receives the first pulse signal Vosc2 from the triangular wave oscillation circuit 13 and generates a second pulse signal Vd delayed by a predetermined delay time td. As the delay circuit 14, for example, several stages of inverters connected in series, or a circuit in which a CR time constant circuit is inserted in the middle thereof can be applied, but the invention is not limited thereto.

  The logic circuit 15 is connected to the comparator 12, the triangular wave oscillation circuit 13, and the delay circuit 14, and receives the PWM signal Vpwm1, the first pulse signal Vosc2, and the second pulse signal Vd, respectively. The logic circuit 15 operates to forcibly turn off the PWM signal Vpwm1 when the first pulse signal Vosc2 switches from high to low, and to cancel the forced off of the PWM signal Vpwm1 by the second pulse signal Vd. To do.

  FIG. 3 is a circuit diagram illustrating an example of the logic circuit 15. Here, the first AND circuit 31 that performs a logical product operation of the PWM signal Vpwm1 and the first pulse signal Vosc2, and the second logical product operation of the PWM signal Vpwm1 and the inverted signal of the second pulse signal Vd. The AND circuit 32 and the OR circuit 33 that performs an OR operation on the output signal VA of the first AND circuit 31 and the output signal VB of the second AND circuit 32 constitute the logic circuit 15.

  The output signal Vpwm of the logic circuit 15 is output through the output buffer 16 to the gate of the output transistor M1 as a switching element of the DC-DC converter circuit unit. The output transistor M1 is turned on when the output signal Vpwm is at the H level, and is turned off when the output signal Vpwm is at the L level. That is, when the output transistor M1 is duty-controlled based on the output signal Vpwm, the DC-DC converter circuit unit performs step-up control so that the output voltage Vout becomes a predetermined set voltage based on the DC input voltage Vin. .

Next, the operation of the DC-DC converter configured as described above will be described. FIG. 4 is a waveform diagram showing each voltage signal waveform of the control circuit section in the converter of FIG.
The comparator 12 compares the error output signal Vfb with the triangular wave signal Vosc1. The comparison result in the comparator 12 is output to the logic circuit 15 as the PWM signal Vpwm1. At this time, the first pulse signal Vosc2 is generated as a rectangular wave that turns on and off in synchronization with the peak of the triangular wave signal Vosc1. The second pulse signal Vd is also generated as a rectangular wave that is synchronized with the triangular wave signal Vosc1 and that is turned on / off with a delay of time td from the first pulse signal Vosc2.

  FIG. 4A shows a signal waveform when the on-time ratio has not yet reached the limit value and the on-time ratio is 50%. In this case, when the first pulse signal Vosc2 is switched from high to low and when the second pulse signal Vd is switched from high to low, the PWM signal Vpwm1 is low, so that the output signal Vpwm of the logic circuit 15 Becomes equal to the PWM signal Vpwm1 which is the output of the comparator 12.

  As shown in FIG. 4B, when the on-time ratio reaches the limit value, the PWM signal Vpwm1 is always high, and the output signal Vpwm of the logic circuit 15 has a delay time td of the second pulse signal Vd. An off period (Toff) corresponding to is forced.

  FIG. 5 is a waveform diagram showing an example of input / output signal waveforms in the logic circuit 15 of FIG. FIG. 6A shows the case where the on-time ratio is not limited, and FIG. 10B shows the case where the on-time ratio is limited. The first pulse signal Vosc2 and the second pulse signal Vd are shown. The PWM signal Vpwm1 is input to the first and second AND circuits 31 and 32. When the on-time ratio is not limited as shown in FIG. 5A, the output signal Vpwm of the logic circuit 15 is output from the OR circuit 33 with the same waveform as the PWM signal Vpwm1. However, when the on-time ratio is limited as shown in FIG. 5B, when the first pulse signal Vosc2 switches from high to low, the output signal VA of the first AND circuit 31 is forcibly set to the low signal. Next, when the second pulse signal Vd is switched from high to low, the output signal VB of the second AND circuit 32 is made high. Thus, the output signal Vpwm output from the OR circuit 33 is latched by the first pulse signal Vosc2 and is unlatched by the second pulse signal Vd, so that the delay time td set by the delay circuit 14 is reached. An equal off period will be forced.

In addition, since the narrow pulse is generated for the first time in the final stage of the logic circuit 15, it becomes easy to maintain the accuracy of the narrow pulse.
Here, since the maximum value of the on-time ratio is limited only by the delay time td set by the delay circuit 14 without using the maximum duty ratio setting voltage or the pulse signal for setting the duty ratio, the on-state is accurately turned on. You can limit the time ratio.

  In addition, as for the high level and low level of each of the above pulse signals Vosc2 and Vd, inversion signals may be used as long as their logics can be matched.

  In the above-described embodiment, the comparator 12 compares the error output signal Vfb and the triangular wave signal Vosc1 and outputs the PWM signal Vpwm1, but instead of the triangular wave signal Vosc1, a sawtooth wave signal or sign (or sine) This can be implemented by appropriately changing to an oscillation signal having a constant amplitude value and a constant period, such as a cosine wave signal.

  In the above-described embodiment, the case where the duty ratio control circuit is used in the step-up DC-DC converter has been described. However, the present invention can also be applied to a step-down DC-DC converter or a step-up / step-down DC-DC converter.

  Furthermore, in the above-described embodiment, not only the duty ratio control circuit is used in the DC-DC converter, but also a drive control device that drives the motor, for example, and the voltage applied to the motor is controlled by duty-controlling the switching element. Thus, the present invention can be applied to a speed control device that controls the rotation speed.

It is a circuit diagram which shows the fundamental structure of the DC-DC converter of this invention. FIG. 2 is a circuit diagram illustrating an example of a triangular wave oscillation circuit in the converter of FIG. 1. It is a circuit diagram which shows an example of the logic circuit in the converter of FIG. It is a wave form diagram which shows each voltage signal waveform of the control circuit part in the converter of FIG. FIG. 4 is a waveform diagram showing an example of input / output signal waveforms in the logic circuit of FIG. 3. It is a circuit diagram showing a conventional PWM step-up DC-DC converter. It is a wave form diagram which shows each voltage signal waveform of the control circuit part in the converter of FIG. It is a circuit diagram which shows the conventional DC-DC converter different from FIG. It is a wave form diagram which shows each voltage signal waveform of the control circuit part in the converter of FIG. FIG. 7 is a circuit diagram showing another conventional DC-DC converter different from FIG. 6. It is a wave form diagram which shows each voltage signal waveform of the control circuit part in the converter of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Error amplifier 12 Comparator 13 Triangular wave oscillation circuit 14 Delay circuit 15 Logic circuit 16 Output buffer

Claims (13)

In the PWM signal time ratio setting method, when the error output signal is compared with a triangular wave signal having a predetermined period to generate a PWM signal, the maximum value of the on-time ratio at which the PWM signal changes is set.
The maximum value of the on-time ratio is limited based on a first pulse signal generated in synchronization with the triangular wave signal and a second pulse signal generated with a predetermined delay time with respect to the first pulse signal. A method for setting a duty ratio of a PWM signal, characterized in that:   2. The PWM signal time ratio setting method according to claim 1, wherein the maximum value of the on-time ratio is set by the predetermined delay time.   The PWM signal generated by comparing the error output signal with the triangular wave signal having the predetermined period is output as it is when the OFF time of the PWM signal is longer than the predetermined delay time. PWM signal duty ratio setting method. An error amplifier for generating an error output signal;
A comparator that compares the error output signal with a triangular wave signal of a predetermined period to generate a PWM signal;
A triangular wave oscillation circuit for generating a triangular wave signal of the predetermined period and a first pulse signal synchronized with the triangular wave signal;
A delay circuit for generating a second pulse signal having a predetermined delay time with respect to the first pulse signal;
A time ratio control circuit comprising: a logic circuit for forcibly turning off the PWM signal by the first pulse signal and releasing the forced off of the PWM signal by the second pulse signal.   The logic circuit forcibly turns off the PWM signal when the first pulse signal switches from high to low, and cancels the forced off state of the PWM signal when the second pulse signal switches from high to low. 5. The duty ratio control circuit according to claim 4, wherein the duty ratio control circuit operates as described above.   The logic circuit forcibly turns off the PWM signal when the first pulse signal switches from low to high, and cancels the forced off state of the PWM signal when the second pulse signal switches from low to high. 5. The duty ratio control circuit according to claim 4, wherein the duty ratio control circuit operates as described above.   The logic circuit forcibly turns off the PWM signal when the first pulse signal switches from high to low, and cancels the forced off state of the PWM signal when the second pulse signal switches from low to high. 5. The duty ratio control circuit according to claim 4, wherein the duty ratio control circuit operates as described above.   The logic circuit forcibly turns off the PWM signal when the first pulse signal switches from low to high, and cancels the forced off state of the PWM signal when the second pulse signal switches from high to low. 5. The duty ratio control circuit according to claim 4, wherein the duty ratio control circuit operates as described above.   9. The time ratio according to claim 4, wherein the triangular wave oscillation circuit generates the first pulse signal so as to be turned on and off in synchronization with a peak of the triangular wave signal having the predetermined period. Control circuit.   A first AND circuit that performs a logical product operation of the PWM signal and the first pulse signal, and a logical product operation of the PWM signal and an inverted signal of the second pulse signal. 10. An AND circuit according to any one of claims 4 to 9, characterized by comprising: an AND circuit of 2; and an OR circuit that performs an OR operation on the output signal of the first AND circuit and the output signal of the second AND circuit. The ratio control circuit according to the above. A DC-DC converter circuit unit that includes a switching element and converts the input voltage into an output voltage having a voltage value different from the input voltage by controlling the duty ratio of the switching element;
An output voltage detection circuit unit for detecting a voltage value of the output voltage;
An error amplifier that generates an error output signal based on a detection voltage from the detection circuit unit;
A comparator that generates a PWM signal for controlling the duty ratio of the switching element by comparing the error output signal with a triangular wave signal having a predetermined period;
A triangular wave oscillation circuit for generating a triangular wave signal of the predetermined period and a first pulse signal synchronized with the triangular wave signal;
A delay circuit for generating a second pulse signal having a predetermined delay time with respect to the first pulse signal;
A DC-DC converter comprising: a logic circuit for forcibly turning off the PWM signal by the first pulse signal and releasing the forced off of the PWM signal by the second pulse signal.   The DC-DC converter according to claim 11, wherein the DC-DC converter circuit unit is a circuit that converts the input voltage into an output voltage having a voltage value higher than the input voltage.   The DC-DC converter according to claim 11, wherein the DC-DC converter circuit unit is a circuit that converts the input voltage into an output voltage having a voltage value lower than the input voltage.

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