JP2005142706A - Imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging apparatus capable of starting display on a monitor just after still picture photographing. <P>SOLUTION: The imaging apparatus is provided with a control circuit for controlling mode switching between a register group for a monitor mode and a register group for a still mode, and alternately switches the monitor mode and the still mode according to the progress of capturing a monitor image to alternately process a monitor image and a still image. Since the imaging apparatus can process the monitor image without the need for awaiting the completion of the processing of the still image, the imaging apparatus carries out the processing of the monitor image in parallel with the processing of the still image just after still picture photographing to thereby be able to start monitor display at an earlier point of time. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a digital camera with improved subject visibility.

  Digital cameras have a function of displaying an image captured by an image sensor on an LCD panel, and many digital cameras do not have an optical viewfinder. Instead of looking through the viewfinder and pressing the shutter like a silver halide camera, the shooting style is generally that you press the shutter while looking at the LCD panel, so that the display quality of the LCD panel affects the success or failure of shooting. It is becoming.

  Hereinafter, as an example of a conventional imaging apparatus, a digital still camera described in Patent Document 1 will be taken and an outline will be described with reference to FIG. FIG. 4 is a block diagram showing a simplified configuration of the digital still camera described in Patent Document 1. In FIG. In FIG. 4, 11 is an imaging circuit, 12 is an image processing circuit, 13 is a display system bus, 14 is a main bus, 15 is a display memory, 16 is a main memory, 17 is a display circuit, 18 is a compression / expansion circuit, and 19 is recording. A reproduction circuit.

  The image pickup circuit 12 includes an image pickup device such as a CCD and an A / D converter. The image of incident light is separated into RGB three primary colors, digitized, and output as RGB format image data. An imaging circuit of a digital still camera has a monitor mode and a still mode, and the operation differs depending on the mode. In the monitor mode, input image data for one screen is output every 1 / 60th of a second, but the number of output pixels is small and the resolution is the same as that of a video camera. On the other hand, in the still mode, image data with higher resolution and higher pixels is output. However, since the number of pixels is large, a relatively long time is required for output. In the following description, an output image in the still mode is called a still image, and an output image in the monitor mode is called a still image.

  Since the RGB format image data output from the imaging circuit 11 is not suitable for display or compression, the imaging circuit 12 converts the RGB format image data into YC format image data and outputs it.

  The feature of the device described in Patent Document 1 is that the two buses of the display bus 13 and the main bus 14 are independent, the display memory 14 is on the display bus 12, and the main bus is on the main bus. That is, the memories 15 are provided independently. Therefore, the image processing circuit 12 writes the monitor image to the display memory 14 via the display bus 12 and outputs the still image to the main memory 15 via the main bus 13 when outputting the still image.

  The display circuit 17 accesses the display memory 14 via the display system bus 12, reads a monitor image in YC format, and displays it on the LCD. Normally, the imaging circuit 11 operates in the monitor mode, and outputs a monitor image every 1/60 second in the monitor mode. Similarly, the image processing circuit 12 and the display circuit 17 each repeat the processing every 1/60 second to update the LCD display, so that the angle of view can be adjusted by looking at the LCD.

  In still image shooting, the operation of the imaging circuit 11 is switched to the still mode, and the output of the image processing circuit 12 is switched to the main bus 13 side. The compression / decompression circuit 18 accesses the main memory 15 via the main bus 13, converts the read YC format still image into compressed data and writes it into the main memory 15, and the recording / reproducing circuit 19 further receives the compressed data from the main memory 15. Read and record to media such as flash memory. Since the output of the monitor image is interrupted while the imaging circuit 11 is in the still mode, the LCD display must be stopped. This display stop period is called a blackout period, and the subject cannot be followed on the LCD during this period.

According to the configuration of FIG. 4, by providing the display system bus independently of the main bus, access to the monitor image and access to the still image can be performed independently without interfering with each other. Therefore, the monitor image can be converted from the RGB format to the YC format and displayed on the LCD while the compression / decompression circuit 18 performs the compression conversion of the still image, and the blackout period of the LCD after shooting is displayed. There is an effect that it can be shortened. In addition, since memory access is distributed between the main bus and the display bus, the entire circuit can be operated with a relatively low clock, and power consumption can be reduced.
JP 2000-278589 A

  However, the above-described conventional configuration has a problem that it does not work efficiently when the imaging circuit is not a progressive system.

  A CCD widely used in digital still cameras has a structure in which light receiving elements are arranged in a grid, a line-shaped transfer unit is provided between the light receiving elements, and a color filter that transmits RGB three primary colors is arranged on the light receiving elements. Take. Progressive CCDs have one row of transfer units for each line of the light receiving element, and sequentially read out for each line. The progressive CCD has an advantage that the subsequent processing is simple because the pixel data is read in the order of the pixel positions.

  On the other hand, there is an interlaced CCD that reads out pixel data divided into two or three fields. This is a structure in which one transfer unit is provided for two light receiving element rows or one for three line light receiving element rows, and a plurality of light receiving element rows share one transfer unit. By reducing the ratio, the light receiving element is enlarged and the sensitivity of the CCD is improved. Since these CCD pixel data are output with one line skipping or two line skipping, it is necessary to arrange the pixel data in the order of the original pixel positions using a field memory before image processing. As described above, the interlaced CCD is complicated in later signal processing, but is widely used in the digital still camera because the sensitivity of the CCD can be improved.

  FIG. 5 is a diagram showing the output of the imaging circuit and the operation of the signal processing circuit. 5A, 5 </ b> B, and 5 </ b> C, the upper 61 is a bar graph showing the time change of the output state of the imaging circuit, and the lower 62 is the time change of the operation of the signal processing circuit. It is a bar graph.

  FIG. 5A shows the operation when a progressive CCD is used. When the image pickup circuit outputs a still image, the signal processing circuit processes the still image, and the image pickup circuit displays the monitor image. When outputting, the signal processing circuit processes the monitor image. As described above, when the progressive CCD is used, the operation of the image pickup circuit and the operation of the signal processing circuit are integrated, and the monitor image can be processed immediately after the still image is taken.

  FIG. 5B shows the operation when a three-field output type CCD is used. Still 1, still 2, and still 3 of the bar graph 61 represent output periods of the first field, the second field, and the third field, respectively, in which still images are divided into three fields and output. While the image pickup circuit is outputting the first field and the second field, the pixel processing continuous in the vertical direction is not complete and the signal processing circuit cannot perform the signal processing, so the RGB data is temporarily written in the main memory. In the third field, when the pixel data of the first field and the second field are read back from the main memory, the pixel data in the vertical direction is not obtained until the signal processing circuit can convert the data from the RGB format to the YC format.

  Here, as apparent from a comparison of FIG. 5B with FIG. 5A, in order to start the monitor image signal processing at the same time as the CCD still image output, 3 in the case of the progressive method is used. Still images need to be processed at twice the speed. In addition, in the third field, reading of the pixel data of the first field and the second field and writing of the processed YC data are simultaneously performed, so that access is concentrated in the main memory. In order to obtain such signal processing speed and memory access speed, it is necessary to increase the speed or scale of the circuit, and an increase in power consumption cannot be avoided.

  FIG. 5C is a graph showing the operation when the signal processing speed is the same as when a progressive CCD is used. In this case, since the pixel data of the third field cannot be processed in real time by the signal processing circuit, like the first field and the second field of pixel data, the pixel data is once written into the main memory and then read out again before being processed. As is apparent from the graph, if the signal processing speed is set to be the same with the increase in power consumption, the start of processing of the monitor image is delayed because the start of processing is delayed by two fields.

  The white balance may be off due to the color temperature of the light source when shooting with flash or twilight. To correct the white balance correctly, the RGB data for one screen is statistically evaluated before the signal is received. Ideally, the process begins. However, in such a case, the processing start of the still image is further delayed by one field, and the processing start of the monitor image is also delayed. As described above, in the conventional configuration, since the monitor image processing start time depends on the still image processing end time, there is a problem that the monitor display cannot be started at an early time point.

  In the configuration of the conventional example, a display memory is provided separately from the main memory. Since the display memory is always accessed, it is more advantageous in terms of power consumption to be incorporated in the signal processing LSI as an SRAM. However, in a general configuration example, a capacity of 2 megabits is required, so the cost of the LSI is reduced. It becomes a factor to increase.

  The image pickup apparatus of the present invention includes a monitor mode register group, a still mode register group, and a control circuit for controlling mode switching, and most importantly processes a monitor image and a still image in parallel by time division multiplexing. Features.

  In the imaging device of the present invention, the imaging circuit immediately shifts to the monitor mode after outputting the still image, and the signal processing circuit processes the monitor image according to the monitor image output of the imaging circuit even during the still image processing. Therefore, there is an advantage that the LCD display can be resumed immediately after still photography. Further, since the display memory only needs to have a capacity for maintaining the display output only while the signal processing circuit processes the still image between the monitor image processes, there is an advantage that the capacity of the display memory can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.

  FIG. 1 is a block diagram illustrating the configuration of a digital still camera according to the present invention. In FIG. 1, 11 is an imaging circuit, 14 is a main bus, 15 is a display memory, 16 is a main memory, 17 is a display circuit, 18 is a compression / decompression circuit, 19 is a recording / reproducing circuit, 21 is an image processing unit, and 22 is a line. The number signal 23 is a mode switching signal.

  The imaging circuit 12 decomposes the incident light image into RGB three primary colors and converts them into digitized RGB image data. The photoelectric conversion element is a three-field interlace readout type CCD, and the operation is different between a monitor mode for outputting a monitor image and a still mode for outputting a still image. The still image is divided into three fields and output. The output of each field requires 6/60 seconds, and the total of the three fields requires 18/60 seconds. On the other hand, the monitor image outputs one screen every 1/60 second.

  The imaging circuit 11 writes the input image into the main memory 16 via the main bus 14. At that time, the imaging circuit 11 notifies the control circuit 20 of the number of lines written as a line number signal 22. The main memory 16 has a still image area and a monitor image area, and the imaging circuit 11 selects an area to be written according to the image.

  The image processing unit 21 reads out RGB format image data from the main memory 16 and converts it into YC format image data. The image processing unit 21 has two modes, a monitor mode and a still mode, and the mode is switched by a mode switching signal 23. In the still mode, the RGB image data is read from the still image area of the main memory 16, and the YC image data is written back to the YC data area of the main memory. Conversely, in the monitor mode, RGB image data is read from the monitor image area of the main memory 16 and YC image data is written to the display memory 15.

  The display memory 15 is a FIFO memory, and the written YC data is read in the same order as at the time of writing. The writing side and reading side clocks are independent, the image processing unit 21 writes in synchronization with the 27 MHz clock, and the display circuit 17 reads in synchronization with the 13.5 MHz clock. Therefore, even if the output from the image processing unit 21 to the display memory 15 is intermittent, if the ratio of the interruption period is less than half and the length of the interruption period is sufficiently short, the FIFO memory will be empty. No.

  The display circuit 17 reads YC data from the display memory 15, converts it into a video signal, and displays it on the LCD. When the monitor image input is interrupted to shoot a still image, the LCD is set to a black screen. The compression / decompression circuit 18 reads the YC data from the main memory 16, converts it into sub-compression data with a reduced capacity, and writes it back to the main memory 16. The recording / reproducing circuit 19 reads the compressed data from the main memory 16 and writes it into the flash memory.

  Next, the configuration of the image processing unit 21 will be described with reference to FIG. FIG. 2 is a block diagram illustrating a configuration example of the image processing unit 21.

  In FIG. 2, 12 is an image processing circuit, 21 is an image processing unit, 23 is a mode switching signal, 24 is a selector, 25 is a gate circuit, 26 is an output switching circuit, 27 is a register F group, 28 is a register B group, and 29 is It is a trigger pulse group. The mode switching signal 23 switches the operation of the image processing unit 21 and controls the selector 24, the gate circuit 25, and the output switching circuit 26. The register F group 27 and the register B group 28 each instruct the operation of the image processing circuit 12, and the contents of the instruction include the start address of the RGB data area and the start address of the YC data area. The outputs of the registers F and B are selected by the selector 24, and only one instruction is given to the image processing circuit 12. The image processing circuit 12 reads the RGB data, converts the data, and writes the YC data according to the instruction, and outputs the trigger pulse group 29 in synchronization with the reading and writing. The trigger pulse group 29 is a pulse for updating the leading address of RGB data and the leading address of YC data in accordance with the progress of writing and reading. The gate circuit 25 operates to select the selector among the register F group and the register B group. It is given only to the register group selected in 24, and the value of each register is updated. The output switching circuit 26 switches the output destination of the image processing circuit 12 according to the mode switching signal 23.

  Here, the operation in mode switching will be described. In the still mode, the register B group is selected, and the leading address of the RGB data and the leading address of the YC data in the register B group are incremented as the processing proceeds. When the mode switching signal 23 changes at a certain point and the monitor mode is switched, the register F group is selected instead of the register B group, and the register B group does not change. When the mode switching signal 23 changes again and switches to the still mode, the start address of the RGB data and the start address of the YC data in the register B group are kept in a state immediately before the still image processing is stopped. No. 12 can restart the still image processing from the interrupted location.

  Next, the operation when shifting from still image shooting to monitor display will be described with reference to FIG. FIG. 3 is a diagram illustrating operations of the imaging circuit 11, the control circuit 20, the signal processing unit 21, and the display unit. In FIG. 3, 41 is a bar graph showing the time change of the output state of the imaging circuit 11, 42 is the waveform of the mode switching signal 23 that is the output of the control circuit 20, and 43 is the time of the still processing in the signal processing unit 21. A bar graph showing the change, 44 is a bar graph showing the time change of the monitor processing in the signal processing unit 21, and 43 is a bar graph showing the time change of the LCD display in the display circuit 17.

  When still image shooting is started, the imaging circuit 11 divides and outputs the still image into three fields as indicated by 41 and 43 in FIG. 3, so that the signal processing unit 21 operates between the first field and the second field. The image cannot be processed. Further, as shown in 44 and 45 in FIG. 3, since the output of the monitor image is stopped, the signal processing unit 21 cannot output the monitor image, and the LCD display must be blacked out.

  When the imaging circuit 11 starts outputting the RGB data of the third field, the control circuit 20 changes the mode switching signal of 42 in FIG. 3 in accordance with the line number signal output from the imaging circuit 11, and the signal processing unit 21 is turned on. Enter mode. Then, as indicated by 43 in FIG. 3, the signal processing unit 21 converts the RGB data of the still image into YC data and outputs it to the main memory 16.

  When the imaging circuit 11 finishes outputting the RGB data of the third field and starts outputting the RGB data of the monitor image, the control circuit 20 switches the mode switching signal 42 in FIG. 3 according to the line number signal output by the imaging circuit 11. To change the signal processing unit 21 to the monitor mode. Then, as shown at 44 in FIG. 3, the signal processing unit 21 converts the RGB data of the monitor image into YC data and outputs it to the display memory 15. As shown at 45 in FIG. 3, the display circuit 17 starts monitor display from this point in time, and the blackout period since the start of still photography ends.

  When the signal processing unit 21 processes a certain amount of monitor image, the control circuit 20 changes the mode switching signal as shown at 42 in FIG. 3, and sets the signal processing unit 21 to the still mode again. Then, as indicated by 44 in FIG. 3, the signal processing unit 21 interrupts the processing of the monitor image, and the output of the YC data to the display memory 15 is stopped. However, since the display memory 15 stores YC data written at double the speed on the reading side, the monitor display is not immediately interrupted as indicated by 45 in FIG.

  When the imaging circuit 11 further advances the output of the RGB data of the monitor image, the control circuit 20 changes the mode switching signal of 42 in FIG. 3 according to the line number signal output by the imaging circuit 11, and the signal processing unit 21 is turned on again. Set to monitor mode. Then, the signal processing unit 21 resumes YC data output to the display memory 15 as indicated by 44 in FIG.

  Assuming that the monitor image processing is intermittently performed and the monitor image of one screen is divided into eight processes, the sum of one YC data output period to the display memory 15 and one output interruption period is 1. This is one eighth of the display period of the monitor image on the screen. Since the ratio of one output period to one stop period is 1: 1, the length of one interruption period is 1/16 of the display period of one screen. Therefore, if the monitor image of one screen is processed in 8 steps and the display memory 15 has a capacity of 1/16 or more of the monitor image, the monitor image processing is intermittent. Even LCD output is not interrupted.

  As described above, the mode switching means is provided in the signal processing unit, and the still display and the monitor processing are executed in a time division manner, so that the monitor display can be resumed immediately after the still image shooting. Since the completion of the still process is not a condition for starting the monitor process as in the conventional configuration, there is no need to increase the signal processing speed in order to speed up the start of the monitor process, and therefore it is not necessary to increase the power consumption. For the same reason, the start of the still process may be after the reading of the RGB data of the entire image is completed, so it is not necessary to delay the start of the monitor display even if a procedure for adjusting the white balance after evaluating the entire image is taken. No. In addition, since the capacity of the display memory 15 can be reduced by executing the monitor process in accordance with the input of RGB data of the monitor image, this can reduce the circuit cost and also reduce the power consumption.

  The image pickup apparatus of the present invention is provided with a mode switching means in the signal processing unit, and can execute monitor processing and time-division processing in a time-sharing manner so that monitor display can be resumed immediately after still image shooting. Applicable to mobile phone terminals with

1 is a block diagram illustrating the configuration of a digital still camera according to the present invention. Explanatory drawing which showed the implementation method of the hand scanner in Embodiment 2 of this invention The figure explaining the operation at the time of shifting from still image shooting to monitor display Block diagram illustrating the configuration of a conventional digital still camera Diagram showing the output of the imaging circuit and the operation of the signal processing circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Image pick-up circuit 12 Image processing circuit 13 Display system bus 14 Main bus 15 Memory for display 16 Main memory 17 Display circuit 18 Compression / decompression circuit 19 Recording / reproduction circuit 21 Image processing part 22 Line number signal 23 Mode switching signal 24 Selector 25 Gate circuit 26 Output switching circuit 27 Register F group 28 Register B group 29 Trigger pulse group 41 Bar graph showing time change of output state of imaging circuit 42 Waveform of mode switching signal 43 Bar graph showing time change of still processing in signal processing unit 44 Signal processing 45 A bar graph representing the time change of the LCD display in the display circuit 61 A bar graph representing the time change in the output state of the imaging circuit 62 A bar graph representing the time change in the operation of the signal processing circuit

Claims (6)

An imaging apparatus comprising an imaging circuit, a storage means, a signal processing circuit, a display circuit, and a control circuit, wherein the imaging circuit has a function of outputting still image data or moving image data, and the storage means The image processing circuit has a function of storing still image data or moving image data, the signal processing circuit has a function of processing still image data or moving image data, and the display circuit is processed by the signal processing circuit Moving image data is displayed, and the control circuit controls the imaging circuit and the signal processing circuit, and monitors the data output progress of the imaging circuit and the data processing of the signal processing circuit. Means for monitoring progress, and the signal processing circuit outputs a predetermined amount of moving image data even when the signal processing circuit is processing still image data. Controlled by processing moving image data, the image pickup apparatus the signal processing circuit is characterized by controlling the signal processing circuit to be processed still image data again when processing a predetermined amount of video data. 2. The imaging apparatus according to claim 1, further comprising a display memory, wherein the capacity of the display memory is smaller than an amount of display data of one frame. The imaging apparatus according to claim 1, further comprising a still image register group and a moving image register group, wherein the control circuit selects an effective register group, and the signal processing circuit includes: An image pickup apparatus that performs processing according to an instruction of a selected register group. 3. The imaging apparatus according to claim 1, further comprising a register group and a saving unit, wherein the saving unit stores contents of the register group, and the signal processing is performed according to an instruction from the control circuit. An image pickup apparatus characterized in that when a circuit switches processing from a still image to a moving image or from a moving image to a still image, the contents of the register group and the contents of the saving means are interchanged with each other. 5. The imaging apparatus according to claim 1, wherein the imaging circuit includes means for notifying a control circuit of an output data amount. 5. The imaging apparatus according to claim 1, further comprising a timer, and monitoring a progress of data output of the imaging circuit by monitoring a time after the imaging circuit starts outputting moving image data. An imaging device characterized by

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