JP2005123247A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a gold bump capable of securing a necessary bump height and saving a great amount of gold without impairing reliability, and a manufacturing method thereof.
A base metal layer is formed on an Al pad and on a passivation film on the periphery of the Al pad. A bump base member other than Au, for example, a Cu post 15 by Cu plating is formed on the base metal layer 14. An Au plating layer 16 is formed on the Cu post 15. The Cu post 15 occupies a thickness of about 2/3 of the entire bump. The Au plating layer 16 is less than half the thickness of the Cu post 15. Further, an Au plating layer 17 that covers the entire surface of the Cu post 15 and the Au plating layer 16 is formed.
[Selection] Figure 1

Description

  The present invention relates to a bump structure of a semiconductor device, and more particularly, to a semiconductor device having a gold bump with a focus on economy, and a manufacturing method thereof.

The gold bump formed on the pad of the IC chip is first formed by sputtering UBM (under bump metal) on the pad formed on the semiconductor wafer. The UBM includes a barrier metal and a metal layer that enhances adhesion. Next, a photoresist pattern having an opening on the pad is formed on the UBM. Thereafter, the semiconductor wafer is brought into contact with a plating solution, and gold is plated on the pad by, for example, electrolytic plating. The gold plating solution uses a special and expensive sulfite compound as the gold compound in order to maintain the photoresist pattern (see, for example, Patent Document 1).
JP 2000-340595 A

  In general, the height of the entire bump of the IC chip needs to be 15 to 25 μm. The same applies to the gold bumps as described above. However, when bonding inner leads such as circuit boards to these bumps, the height of the entire bumps needs to be 15 to 25 μm, but there is room for studying whether it is necessary to make all of them gold. Recent IC chips are required to have a narrow pitch bump array, and the number of bumps per chip has increased considerably. Therefore, forming the entire bump height with gold leads to an increase in bump cost.

  The present invention has been made in consideration of the above-described circumstances, and provides a semiconductor device having a gold bump that can secure a necessary bump height and can save a large amount of gold without impairing reliability, and a method for manufacturing the same. It is something to be offered.

  The semiconductor device according to the present invention is formed around the electrical connection region including a pad member connected to a path into the integrated circuit and having an electrical connection region with the outside, and a peripheral portion on the pad member. One or more insulating films, a base metal layer coated on the pad member and the surrounding insulating film, a bump base member other than gold provided on the base metal layer, and a gold plating layer thereon A bump electrode formed of a laminate of

According to the semiconductor device of the present invention, as long as the gold thickness substantially required as the bump electrode is secured, the underlying metal may be a substance other than gold as the bump base member. This can save a lot of money.
The semiconductor device according to the present invention preferably has at least one of the following characteristics.
The gold plating layer has a thickness of 1/3 or less of the height of the bump electrode.
The bump base member contains either Cu or Ag.

  The semiconductor device according to the present invention is formed around the electrical connection region including a pad member connected to a path into the integrated circuit and having an electrical connection region with the outside, and a peripheral portion on the pad member. One or more insulating films, a base metal layer coated on the pad member and the surrounding insulating film, a bump base member containing Cu, and an upper part of the bump base member provided on the base metal layer A bump electrode made of a laminate of gold plating layers with thicker side portions and thinner side portions.

According to the semiconductor device of the present invention, a gold thickness substantially necessary as a bump electrode is ensured, and the underlying metal uses Cu as a bump base member. Further, the entire bump electrode is improved in reliability by covering Cu with a gold plating layer. This provides high reliability and significant savings in gold.
Preferably, the gold plating layer has a thickness of 1/3 or less of the height of the bump electrode.

  The semiconductor device according to the present invention is formed around the electrical connection region including a pad member connected to a path into the integrated circuit and having an electrical connection region with the outside, and a peripheral portion on the pad member. One or more insulating films, a base metal layer coated on the pad member and the surrounding insulating film, a bump base member containing Ag, and an upper part of the bump base member provided on the base metal layer A bump electrode made of a laminate of gold plating layers with thicker side portions and thinner side portions.

According to the semiconductor device of the present invention, a gold thickness substantially necessary as a bump electrode is ensured, and the underlying metal uses Ag as a bump base member. Further, the entire bump electrode is improved in reliability by covering Ag with a gold plating layer. This provides high reliability and significant savings in gold.
Preferably, the gold plating layer has a thickness of 1/3 or less of the height of the bump electrode.

  The method of manufacturing a semiconductor device according to the present invention includes a step of selectively forming a pad member on a substrate, a step of forming one or more insulating films so as to cover the pad member, and the pad on the insulating film. Selectively opening on the electrical connection region of the member to expose the surface of the electrical connection region in the pad member; depositing at least one underlying metal layer on the pad member; and A step of forming a resist pattern for bumps excluding the electrical connection region and its periphery, and plating a bump base member other than gold on the base metal layer according to the resist pattern to a height in the middle of the resist pattern Removing the resist pattern, a step of gold plating on the bump base member with a thickness less than half of the bump base member according to the resist pattern, And including a step of etching the underlying metal layer as the mask a laminated shape of the bump base member and gold plating.

According to the method for manufacturing a semiconductor device of the present invention, after plating a bump base member other than gold, gold plating is performed on the bump base member with a thickness less than half of the bump base member. If the gold thickness substantially necessary for the bump electrode is secured, the underlying metal may be a substance other than gold as the bump base member. This can save a lot of money.
Preferably, the bump base member is selected from metals whose hardness is closer to that of gold.

  The method of manufacturing a semiconductor device according to the present invention includes a step of selectively forming a pad member on a substrate, a step of forming one or more insulating films so as to cover the pad member, and the pad on the insulating film. Selectively opening on the electrical connection region of the member to expose the surface of the electrical connection region in the pad member; depositing at least one underlying metal layer on the pad member; and A step of forming a resist pattern for bumps excluding the electrical connection region and its periphery, a first plating step of plating a Cu member to a height in the middle of the resist pattern according to the resist pattern, and according to the resist pattern A second plating step of plating an Au member on the Cu member with a thickness of half or less of the Cu member, and removing the resist pattern to remove the Cu member and The laminate shape of Au member comprises etching the underlying metal layer as a mask, a third plating step of coating the exposed surface of at least the Cu member and Au member Au member.

According to the semiconductor device manufacturing method of the present invention, after the Cu member is plated in the first plating step, gold plating is performed on the Cu member with a thickness less than half of the Cu member (second plating step). Furthermore, reliability is improved by covering the whole bump electrode surface including Cu by a 3rd plating process with a gold plating layer. That is, a gold thickness substantially necessary as a bump electrode is secured, and the underlying metal is replaced with a Cu member. Furthermore, the entire bump electrode is plated with gold. This provides high reliability and significant savings in gold.
Preferably, the first and second plating steps are achieved using an electrolytic plating method, and the third plating step is accomplished using an electroless plating method.

  The method of manufacturing a semiconductor device according to the present invention includes a step of selectively forming a pad member on a substrate, a step of forming one or more insulating films so as to cover the pad member, and the pad on the insulating film. Selectively opening on the electrical connection region of the member to expose the surface of the electrical connection region in the pad member; depositing at least one underlying metal layer on the pad member; and A step of forming a resist pattern for bumps excluding the electrical connection region and its periphery, a first plating step of plating an Ag member to a height in the middle of the resist pattern according to the resist pattern, and according to the resist pattern A second plating step of plating an Au member on the Ag member with a thickness less than half that of the Ag member, and removing the resist pattern to form the Ag member and The laminate shape of Au member comprises etching the underlying metal layer as a mask, a third plating step of coating the exposed surface of at least the Ag member and Au member Au member.

According to the semiconductor device manufacturing method of the present invention, after the Ag member is plated in the first plating step, gold plating is performed on the Ag member with a thickness less than half of the Ag member (second plating step). Furthermore, reliability is improved by covering the whole bump electrode surface including Ag by a 3rd plating process with a gold plating layer. That is, a gold thickness substantially necessary as a bump electrode is secured, and the underlying metal is replaced with an Ag member. Furthermore, the entire bump electrode is plated with gold. This provides high reliability and significant savings in gold.
Preferably, the first and second plating steps are achieved using an electrolytic plating method, and the third plating step is accomplished using an electroless plating method.

BEST MODE FOR CARRYING OUT THE INVENTION

  FIG. 1 is a cross-sectional view showing the configuration of bumps provided on a pad, which is a main part of the semiconductor device according to the first embodiment of the present invention. An Al pad 12 is formed on the insulating film 11 on the semiconductor substrate. The Al pad 12 is connected to a path into the integrated circuit (not shown). A passivation film 13 is formed on the insulating film 11 and on the periphery of the Al pad 12. A base metal layer 14 that functions as a barrier metal or a protective metal layer for adhesion is formed on the Al pad 12 and the passivation film 13 on the periphery thereof. The underlayer metal layer 14 is also referred to as an under bump metal (UBM) and has, for example, a laminated structure of TiW / Cu and also serves as a plating metal layer. In addition, the structure containing Ti and Pd is also conceivable. A bump base member other than Au, for example, a Cu post 15 by Cu plating is formed on the base metal layer 14. An Au plating layer 16 is formed on the Cu post 15. Further, an Au plating layer 17 that covers the entire surface of the Cu post 15 and the Au plating layer 16 is formed.

  The Cu post 15 occupies a thickness of about 2/3 of the entire bump. The Au plating layer 16 is less than half the thickness of the Cu post 15. For example, when the height of the entire bump is 15 to 25 μm, it is sufficient that the thickness of the Au portion is 5 to 10 μm. As a result, a Cu post 15 having a hardness close to Au is formed in a thickness of about 10 to 15 μm to form a bump base member. An Au plating layer 16 and further an Au plating layer 17 are formed thereon.

  According to the structure of the said embodiment, if the thickness of Au substantially required as a bump electrode is ensured, there will be no problem even if the metal under it is a substance other than Au as a bump base member. This can save a lot of money. The bump base member is the Cu post 15, but it is also possible to use a Cu alloy material, a material other than Cu, or an alloy material. It is also conceivable to omit the Au plating layer 17. However, a configuration in a limited environment is possible, for example, when the Cu post 15 is used in an environment in which it is difficult to change or corrode, or in an environment in which there is no problem even with some deterioration.

2 to 4 are cross-sectional views showing the main part of the method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps. The same parts as those in the first embodiment will be described with the same reference numerals as those in FIG.
As shown in FIG. 2, an Al pad 12 connected to a path (not shown) to the inside of the integrated circuit is formed on the insulating film 11 on the semiconductor substrate. A passivation film 13 is formed on the insulating film 11 and on the periphery of the Al pad 12. TiW and Cu are sequentially sputtered on the Al pad 12 and the passivation film 13 to form a base metal layer (UBM) 14.

  Next, a resist pattern 21 is formed on the underlying metal layer 14 so as to open the Al pad 12 and its upper periphery. Next, Cu is plated and grown to an intermediate height of the resist pattern 21 by an electrolytic plating method. Thereby, the Cu post 15 is formed. The height of the Cu post 15 is approximately 2/3 of the height of the entire bump. As the electrolytic plating solution, for example, a copper sulfate plating solution or a copper pyrophosphate plating solution is used. Next, Au is grown according to the resist pattern 21 by electrolytic plating. Thereby, the Au plating layer 16 is formed. The height of the Au plating layer 16 is approximately half of the height of the Cu post 15. A gold plating solution composed of a sulfite compound is used as the electrolytic plating solution. The amount of precipitation in each plating step is controlled by the plating time.

  Next, as shown in FIG. 3, the resist pattern 21 is peeled off. Next, the base metal layer 14 is removed by wet etching using the laminated shape of the Cu post 15 and the Au plating layer 16 as a mask.

  Next, as shown in FIG. 4, it is immersed in an electroless gold plating solution containing Au ions, a reducing agent, a stabilizer, a buffering agent, etc., and electroless Au plating is performed. For example, the plating time is controlled until the amount of self-deposition of Au reaches about 0.3 to 1.0 μm. Thereby, the exposed metal surface including the laminated shape of the base metal layer 14, the Cu post 15 and the Au plating layer 16 is coated with a thin gold plating. Thereby, the Au plating layer 17 is formed, and the configuration as shown in FIG. 1 can be obtained.

  According to the method of the above embodiment, the Cu post 15 is formed in the first electrolytic plating process. Next, the Au plating layer 16 is formed on the Cu post 15 with a thickness less than half of this Cu by a second electrolytic plating process. Furthermore, the reliability is improved by covering the entire bump electrode surface with the Au plating layer 17 through an electroless plating process. That is, the thickness of Au substantially required as a bump electrode is ensured, and the underlying metal is replaced with a Cu member. Further, the entire bump electrode is covered with Au. This provides high reliability and significant savings in gold.

  FIG. 5 is a cross-sectional view showing the configuration of the bumps provided on the pad, which is a main part of the semiconductor device according to the third embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals. An Al pad 12 is formed on the insulating film 11 on the semiconductor substrate. The Al pad 12 is connected to a path into the integrated circuit (not shown). A passivation film 13 is formed on the insulating film 11 and on the periphery of the Al pad 12. A base metal layer 34 that functions as a barrier metal or a protective metal layer for adhesion is formed on the Al pad 12 and the passivation film 13 on the periphery thereof. That is, it is an under bump metal (UBM), for example, a laminated structure of TiW / Ag, and also serves as a metal layer for plating. In addition, the structure containing Ti and Pd is also conceivable. A bump base member other than Au, for example, an Ag post 35 by Ag plating is formed on the base metal layer 34. An Au plating layer 16 is formed on the Ag post 35.

  The Ag post 35 occupies a thickness of about 2/3 of the entire bump. The Au plating layer 16 is less than half the thickness of the Ag post 35. For example, when the height of the entire bump is 15 to 25 μm, it is sufficient that the thickness of the Au portion is 5 to 10 μm. Therefore, an Ag post 35 is formed to have a thickness of about 10 to 15 μm and used as a bump base member. An Au plating layer 16 is formed thereon.

  According to the structure of the said embodiment, if the thickness of Au substantially required as a bump electrode is ensured, there will be no problem even if the metal under it is a substance other than Au as a bump base member. This can save a lot of money. Further, when the Ag post 35 is used in an environment in which the Ag post 35 is easily altered or corroded, or in an environment that is hindered by slight alteration, the Au plating layer 17 may be configured as a bump surface as in FIG. (FIG. 8).

6 and 7 are cross-sectional views showing the main part of the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention in order of steps. The same parts as those in the third embodiment will be described with the same reference numerals as those in FIG.
As shown in FIG. 6, an Al pad 12 connected to a path (not shown) to the inside of the integrated circuit is formed on the insulating film 11 on the semiconductor substrate. A passivation film 13 is formed on the insulating film 11 and on the periphery of the Al pad 12. TiW and Ag are sequentially laminated on the Al pad 12 and the passivation film 13 to form a base metal layer (UBM) 34.

  Next, a resist pattern 21 is formed on the underlying metal layer 34 so as to open the Al pad 12 and its upper periphery. Next, Ag is plated and grown to an intermediate height of the resist pattern 21 by electrolytic plating. Thereby, the Ag post 35 is formed. The height of the Ag post 35 is approximately 2/3 of the height of the entire bump. As the electrolytic plating solution, for example, a low-purity, weak alkaline high-purity silver plating solution is used. Next, Au is grown according to the resist pattern 21 by electrolytic plating. Thereby, the Au plating layer 16 is formed. The height of the Au plating layer 16 is approximately half the height of the Ag post 35. A gold plating solution composed of a sulfite compound is used as the electrolytic plating solution. The amount of precipitation in each plating step is controlled by the plating time.

  Next, as shown in FIG. 7, the resist pattern 21 is peeled off. Next, the base metal layer 34 is removed by wet etching using the laminated shape of the Ag post 35 and the Au plating layer 16 as a mask. Thereby, the configuration as shown in FIG. 5 is obtained.

  FIG. 8 shows the main part of the semiconductor device according to the fifth embodiment of the present invention, which is configured by adding an Au plating layer 17 to the third embodiment in the same manner as in the first embodiment. That is, in the structure of FIG. 7, the electroless Au plating is performed by immersing in an electroless gold plating solution containing Au ions, a reducing agent, a stabilizer, a buffering agent and the like. For example, the plating time is controlled until the amount of self-deposition of Au reaches about 0.3 to 1.0 μm. As a result, the exposed metal surface including the laminated shape of the base metal layer 34, the Ag post 35 and the Au plating layer 16 is covered with a thin gold plating, thereby forming the Au plating layer 17.

  According to the above embodiments and methods, the Ag post 35 is formed in the first electrolytic plating process. Next, the Au plating layer 16 is formed on the Ag post 35 with a thickness less than half of this Ag by a second electrolytic plating process. That is, the thickness of Au substantially necessary as a bump electrode is ensured, and the underlying metal is replaced with an Ag member. Furthermore, reliability can be improved by covering the whole bump electrode surface with the Au plating layer 17 through an electroless plating process. This provides high reliability and significant savings in gold.

  As described above, according to the present invention, if a gold thickness substantially necessary as a bump electrode is ensured, the underlying metal can be replaced with a material other than gold as a bump base member. As a result, the overall bump shape and height are adjusted, which contributes to a significant reduction in bump cost. As a result, it is possible to provide a semiconductor device having a gold bump that can secure a necessary bump height and can save a large amount of gold without impairing reliability, and a manufacturing method thereof.

FIG. 3 is a cross-sectional view showing the main configuration of the semiconductor device according to the first embodiment. The 1st sectional view showing the manufacturing method of the semiconductor device concerning a 2nd embodiment in order of a process. The 2nd sectional view following Drawing 2. FIG. 4 is a third sectional view following FIG. 3. Sectional drawing which shows the principal part structure of the semiconductor device which concerns on 3rd Embodiment. The 1st sectional view showing the manufacturing method of the semiconductor device concerning a 4th embodiment in order of a process. The 2nd sectional view following Drawing 6. Sectional drawing which shows the principal part structure of the semiconductor device which concerns on 5th Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Insulating film, 12 ... Al pad, 13 ... Passivation film, 14, 34 ... Metal layer for base | substrate, 15 ... Cu post, 16, 17 ... Au plating layer, 21 ... Resist pattern, 35 ... Ag post | mailbox.

Claims (11)

A pad member connected to a path to the inside of the integrated circuit and having an electrical connection region with the outside;
One or more insulating films formed around the electrical connection region including a peripheral portion on the pad member;
A base metal layer coated on the pad member and the insulating film around the pad member;
A semiconductor device comprising: a bump base member other than gold provided on the base metal layer and a bump electrode formed by stacking a gold plating layer thereon. The semiconductor device according to claim 1, wherein the gold plating layer has a thickness of 1/3 or less of the height of the bump electrode. The semiconductor device according to claim 1, wherein the bump base member contains either Cu or Ag. A pad member connected to a path to the inside of the integrated circuit and having an electrical connection region with the outside;
One or more insulating films formed around the electrical connection region including a peripheral portion on the pad member;
A base metal layer coated on the pad member and the insulating film around the pad member;
A semiconductor device comprising: a bump base member including Cu provided on the base metal layer; and a bump electrode formed by stacking a gold plating layer in which an upper part of the bump base member is thick and a side part is thin. A pad member connected to a path to the inside of the integrated circuit and having an electrical connection region with the outside;
One or more insulating films formed around the electrical connection region including a peripheral portion on the pad member;
A base metal layer coated on the pad member and the insulating film around the pad member;
A semiconductor device comprising: a bump base member including Ag provided on the base metal layer; and a bump electrode formed by stacking a gold plating layer in which an upper part of the bump base member is thick and a side part is thin. 6. The semiconductor device according to claim 4, wherein the gold plating layer on the bump base member has a thickness of 1/3 or less of the height of the bump electrode. Forming a pad member selectively on the substrate;
Forming one or more insulating films so as to cover the pad member;
Selectively opening the electrical connection region of the pad member on the insulating film, and exposing the electrical connection region surface of the pad member;
Depositing at least one underlying metal layer on the pad member;
Forming a resist pattern for bumps excluding the electrical connection region and its periphery; and
Plating a bump base member other than gold up to a height in the middle of the resist pattern on the base metal layer according to the resist pattern;
A step of gold plating on the bump base member according to the resist pattern with a thickness of half or less of the bump base member;
Removing the resist pattern, and etching the base metal layer using the bump base member and the gold-plated laminated shape as a mask. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the bump base member is made of a metal whose hardness is closer to that of gold. Forming a pad member selectively on the substrate;
Forming one or more insulating films so as to cover the pad member;
Selectively opening the electrical connection region of the pad member on the insulating film, and exposing the electrical connection region surface of the pad member;
Depositing at least one underlying metal layer on the pad member;
Forming a resist pattern for bumps excluding the electrical connection region and its periphery; and
A first plating step of plating a Cu member to a height in the middle of the resist pattern according to the resist pattern;
A second plating step of plating an Au member on the Cu member in a thickness less than half of the Cu member according to the resist pattern;
Removing the resist pattern and etching the underlying metal layer using the stacked shape of the Cu member and Au member as a mask;
And a third plating step of covering at least the exposed surfaces of the Cu member and Au member with the Au member. Selectively forming a pad member on the substrate;
Forming one or more insulating films so as to cover the pad member;
Selectively opening the electrical connection region of the pad member on the insulating film, and exposing the electrical connection region surface of the pad member;
Depositing at least one underlying metal layer on the pad member;
Forming a resist pattern for bumps excluding the electrical connection region and its periphery; and
A first plating step of plating the Ag member to a height in the middle of the resist pattern according to the resist pattern;
A second plating step of plating an Au member on the Ag member according to the resist pattern with a thickness of half or less of the Ag member;
Removing the resist pattern and etching the underlying metal layer using the laminated shape of the Ag member and Au member as a mask;
A third plating step of covering at least the exposed surfaces of the Ag member and the Au member with an Au member. 11. The method of manufacturing a semiconductor device according to claim 9, wherein the first and second plating steps are achieved by using an electrolytic plating method, and the third plating step is performed by using an electroless plating method. .

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