JP2005122498A - Timing library creation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate a highly precise timing library by suppressing a delay time from deviating beyond a delay table parameter even when there is delay calculation error in an area where the inclination of signal waveform, incapable of being obtained by a characteristic extraction using a non-linear waveform input, is minute. <P>SOLUTION: In the area where the inclination of signal waveform, incapable of being obtained by the characteristic extraction using the non-linear waveform input, is minute, the inclination is obtained by using the result of the characteristic extraction by the linear waveform input, and the inclination is obtained by using the result of the characteristic extraction by the non-linear waveform input in the other area (S3), thereby suppressing the delay time from devizting beyond the delay table parameter even when there is any delay calculation error, and generating the highly precise timing library. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method of creating a timing library that stores timing information of each cell, which becomes basic data for performing delay calculation when verifying a semiconductor integrated circuit having a plurality of cells.

  The gate delay time of a circuit is obtained from a cell delay time table (hereinafter referred to as a delay table) described in a delay time calculation library (hereinafter referred to as a timing library) and wiring information connected to the cells. it can. Here, the cell refers to a block of circuits in which basic logic is expressed by an electronic circuit, such as an inverter, a buffer, a NAND circuit, and a NOR circuit. The delay table is generally expressed as a function of the slope of the input waveform of the electric signal applied to the input terminal and the load capacitance value connected to the output terminal. The delay accuracy, library size, and calculation time differ depending on the combination of the delay table parameters expressed by the slope of the input waveform and the load capacity. Therefore, it is required to reduce the table size as much as possible while maintaining the delay accuracy. .

Hereinafter, a conventional method for creating a timing library will be described with reference to FIG.
FIG. 2A is a conceptual diagram for explaining a method of extracting characteristics of a measurement target cell when a linear waveform is input, and FIG. 2B is a table illustrating a delay table of the measurement target cell when a linear waveform is input. FIG. 2D is a conceptual diagram for explaining a method of extracting characteristics of a measurement target cell when a nonlinear waveform is input, and FIG. 2E is a table illustrating a delay table of the measurement target cell when a nonlinear waveform is input. FIG.

As shown in FIG. 2A, a linear signal waveform having a slope t _s-L is given to the input terminal and a load is given to the output terminal for the measurement target cell 12 (inverter in this case) for creating the timing library. When _CL is given as a capacitor, a delay time t _pd from when a potential is input from the input terminal to when the potential at the output terminal is output is measured. Since high accuracy is required for the measurement, a transistor level simulator such as SPICE is usually used. Here, the slope t _s-L usually indicates the time until the voltage rises from the zero potential to the power supply voltage, and is called the waveform slope.

In the above example, a linear waveform is given as the input signal waveform. However, since the signal transmitted to the circuit is usually non-linear, a circuit such as that shown in FIG. There is. In this example, a temporary drive cell 11 and a temporary drive cell load capacitance C _cntl are provided to generate an input signal waveform. The inclination t _s-NL of the input signal applied to the measurement target cell 12 can be _obtained by changing the load capacitance C _cntl even if the drive capability of the temporary drive cell 11 is constant when an electrical signal is applied to the input portion of the temporary drive cell 11. Various nonlinear waveforms can be generated as ts _-NL .

The accuracy of the delay calculation depends on the size of the delay table and the number of parameters of the delay table. The greater the number of parameters, the higher the accuracy. In addition, the larger the delay table size, that is, the greater the waveform slope t _s-L (or t _s-NL ) value and load capacitance C _cntl value, the _wider the circuit application range of the cell. For example, when the circuit is used in an area exceeding the description range of the delay table, the delay accuracy is not guaranteed. If it is within the description range of the delay table, it is possible to predict the value by linearly interpolating between delay table parameters or using a certain function. However, it is difficult to predict in an area beyond the description range of the delay table, and for example, prediction is often performed by extending the interpolation in the delay table as it is (for example, see Non-Patent Document 1).

Here, the delay table of the circuit shown in FIG. 2 (a) is as in FIG. 2 (b), the slope t _s-L and load capacitor C _L by a delay time t _pd given to the output terminal is determined. The delay table of the circuit shown in FIG. 2 (d) is as FIG. 2 (e), the slope _{t s-NL,} is supplied to the output terminal load capacitance _{C L} and the load capacitance _{C cntl} by the delay time _{t pd} is It has been decided.
F. Dartu, N .; Menezes, J.M. Qian and L. T.A. Pilage, “A Gate-delay Model for High-speed CMOS Circuits,” Proc. of IEEE / ACM DAC 1994, 1994, pp. 576-580.

However, when a timing library is created as in the prior art, since the waveform is generated via a temporary drive cell that generates a nonlinear waveform, the waveform slope at the slope _ts-NL cannot be reduced beyond a certain level. . For example, _assuming that the driving capability of the temporary driving cell 11 is constant, it is possible to generate the most steep (steep) t _{s -NL} when the control load C _cntl = 0 is set. That is, when the magnitude of the required gradient _{t s-NL} value is less than _{t s-NL} value o'clock control load _{C cntl} = 0, can not be produced because it can not be any more reduced control load _{C cntl.}

  In addition, in order to guarantee the library accuracy, it is necessary to use all the circuits that use the cell within the delay table parameter range. However, in actuality, the gate level delay calculation using this timing library has a delay calculation error. However, there is a possibility that it deviates outside the delay table parameter because the error fluctuates with plus or minus with respect to zero accuracy error.

Here, the lower limit of the delay table parameter that can be generated is when the control load C _cntl = 0 and the temporary drive cell has the maximum drive capacity. On the other hand, the cell used for the temporary drive cell is registered in the library. As a result, the slope t _s-NL cannot be made smaller than a certain value, and in the actual circuit, the slope of the delay-calculated waveform also causes the control load C _cntl to be _reduced due to the delay calculation error. There is a problem that a value smaller than the slope of the waveform when 0 is set may appear.

  In order to solve the above problems, the timing library creation method according to the present invention has a delay calculation error in a region where the slope of the signal waveform, which cannot be obtained by characteristic extraction by nonlinear waveform input, is small. An object of the present invention is to generate a highly accurate timing library that can suppress the delay time from deviating outside the delay table parameter. It is another object of the present invention to easily create a temporary drive cell having a high drive capability.

  In order to achieve the above object, a timing library creating method according to claim 1 of the present invention is a timing library creating method for each cell used for timing verification of a semiconductor integrated circuit having a plurality of cells including basic logic elements. The step of calculating a first timing library by applying a linear input signal waveform to the input terminal of the target cell, and the step of calculating the second timing library by applying a nonlinear input signal waveform to the input terminal of the target cell. The timing library of the target cell is synthesized using the first timing library in the region where the slope of the input signal waveform to each cell is small, and the second timing library in the other regions. And a step of performing.

  The timing library creating method according to claim 2 is the timing library creating method according to claim 1, wherein a temporary drive cell and a variable load capacitance are added to an input terminal of the target cell in order to generate the nonlinear input signal waveform. It is characterized by doing.

A timing library creation method according to a third aspect is the timing library creation method according to the second aspect, wherein a plurality of the temporary drive cells are connected and provided in parallel.
A timing library creating method according to a fourth aspect is the timing library creating method according to the first or second aspect, wherein the temporary driving cell is an inverter or a buffer.

  According to the above method, the delay calculation error is obtained by obtaining the slope using the result of the characteristic extraction by the linear waveform input in the region where the slope of the signal waveform that cannot be obtained by the characteristic extraction by the nonlinear waveform input is small. Even if there is a delay time, it is possible to prevent the delay time from deviating from the delay table parameter, and as a result, a highly accurate timing library can be generated.

  Also, in the region where the slope of the signal waveform that could not be obtained by the characteristic extraction by nonlinear waveform input is very small, the slope is calculated using the result of the characteristic extraction by linear waveform input using a temporary drive cell with higher driving capability. In other areas, it is possible to suppress the delay time from deviating from the delay table parameter even if there is a delay calculation error by calculating the slope using the result of characteristic extraction by nonlinear waveform input. High timing library can be generated. Furthermore, it is not necessary to create a circuit with a particularly large transistor size in order to create a temporary drive cell having a high drive capability, and there is an advantage that a new effort is saved.

  As described above, in a region where the slope of the signal waveform that could not be obtained by characteristic extraction by nonlinear waveform input is very small, the slope is obtained using the result of characteristic extraction by linear waveform input, and in other regions By obtaining the slope using the result of characteristic extraction by nonlinear waveform input, it is possible to suppress the delay time from deviating outside the delay table parameter even if there is a delay calculation error, and as a result, a highly accurate timing library can be generated. .

  Also, in the region where the slope of the signal waveform that could not be obtained by characteristic extraction by nonlinear waveform input is very small, the slope is calculated using the result of characteristic extraction by linear waveform input using a temporary drive cell with higher driving capability. In other areas, it is possible to suppress the delay time from deviating from the delay table parameter even if there is a delay calculation error by calculating the slope using the result of characteristic extraction by nonlinear waveform input. High timing library can be generated. Furthermore, it is not necessary to create a circuit with a particularly large transistor size in order to create a temporary drive cell having a high drive capability, and there is an advantage that a new effort is saved.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Embodiment 1 of the Invention
Hereinafter, Embodiment 1 of the present invention will be described with reference to FIGS.

  FIG. 1 is a flowchart showing the library creation method of the present invention. FIG. 2C is a graph of the delay table of the measurement target cell when the linear waveform is input, and the table of FIG. 2B is graphed. Similarly, FIG. 2 (f) is a graph of the delay table of the measurement target cell when the nonlinear waveform is input, and is a graph of the table of FIG. 2 (d). FIG. 2 (g) is a graph of the delay table created by the timing library creation method of the present invention. The graph of FIG. 2 (c) is used in a region where the slope is small, and FIG. 2 is used in other regions. The graph of (f) is used. Further, FIG. 2 (h) is a diagram illustrating a table illustrating a delay table created by the timing library creating method of the present invention, and the graph of FIG. 2 (f) is summarized in the table.

Here, as the circuit for obtaining the delay table, a circuit in which the measurement target cell 12 is an inverter as shown in FIG. 2 is used. In FIG. 2D, the temporary drive cell 11 and the output pin of the temporary drive cell 11 are connected to its input terminals. A variable load capacitance C _cntl is provided between the input pins of the measurement object cell 12. The temporary drive cell 11 is a circuit that generates an input waveform of the measurement target cell 12, and a buffer is usually used. Also in the present embodiment, an inverter provided with temporary drive cell 11 and variable load capacitance C _cntl is used.

A process of creating a timing library will be described with reference to FIG.
In FIG. 1, first, characteristic extraction by linear waveform input is performed (S1). In this step, determine the slope t _s-L and load capacitor C _L by changing the delay time of the measurement target cell t _pd of the signal waveform. For example, when the set (ts _−L , C _L ) = (3 ps, 1 fF), t _pd = 15 ps. What should be noted here is to take a sufficiently small value as the slope value of the signal waveform. The value must be smaller than the signal waveform of the circuit in which the measurement target cell is used. Although it depends on the circuit, it is usually 1 to 3 ps. Further, the interval between the values that can be taken by the inclination of the signal waveform is small when the value is small, and it is preferable that the interval is widened as the value increases. This is because the delay characteristic of the transistor changes abruptly in a minute region of the waveform slope. FIG. 2B shows the combinations in a table. The obtained data is stored in the Libert _s-L database.

Next, characteristic extraction by nonlinear waveform input is performed (S2). In this step, the slope _{ts -NL} of the input waveform can be controlled by the variable load capacitance C _cntl . The variable load capacitance C _{cntl in} FIG. _2E is a temporary drive cell load capacitance value necessary to obtain an arbitrary gradient t _s-NL . The combination of the slope of the signal waveform and the load capacity is the same value as in FIG. However, in FIG. 2 (e), the slope ts _-NL has no value of 3 ps or 7 ps. This is because even when the temporary drive cell load capacitance value was set to zero, only a slope t _s−NL = 8 ps was obtained. As a result, the slope t _s-L and the slope t _s-NL are not the same. Conversely, it should be noted that the t _pd values are different even if the slope t _s-L and the slope t _s-NL are the same value. This is because the signal waveform differs between linear and non-linear. Usually, if the values are the same, the _tpd value becomes larger in the non-linear case. The obtained data is stored in the Libert _s-NL database.

Here, the error will be described.
FIG. 2B shows the result when the characteristic extraction is performed according to FIG. 2A, and FIG. 2C is a graph of the result. In FIG. 2C, the combinations of the slope t _s-L , the load capacitance C _L , and the delay time t _pd in the table of FIG. 2B are represented corresponding to PL1, PL2, PL3, and PL4 from the top. ing. That, PL1 _is the point when the _{(t s-L, C L} , t pd) = (3ps, 2fF, 15ps). Here, it is assumed that the vertical axis of the graph is the delay t _pd and the horizontal axis is the slope t _s-L . In this example, the load capacity C _L = 2fF is constant, but the load capacity is actually variable. If the load capacity is also variable, it is necessary to solve a four-point plane considering the combination of t _s-L and C _L. In this embodiment, the load capacity is constant for the sake of simplicity.
Next, when the value of the slope t _s-L is 5 ps, that is, when obtaining the delay time t _pd 1 when (t _s-L , C _L ) = (5 ps, 2 fF), as shown in FIG. The delay time t _pd 1 can be obtained by linearly interpolating PL1 and PL2, for example. On the other hand, it is assumed that the delay time t _pd 2 when (ts _−L , C _L ) = (5 ps, 2 fF) is actually obtained by using transistor level simulation. In the figure, it is a white circle. Of course, the former is an approximate value and the latter is a true value. The difference t _pd 1-t _pd 2 can be defined as an error. In the figure, error 1 is assumed.

Similarly, FIG. 2 (f) is represented with respect to FIG. 2 (e). _2F , the _combinations of the variable load capacity C _cntl , the slope time t _s-NL , the load capacity C _L , and the delay time t _{pd in} the table of FIG. It is expressed corresponding to. If t _s−L = t _s−NL = 5 ps, error 2 is obtained in the same manner as described above. Here, an interpolation method by linear extension from the table is used for the interpolation outside the table. Outside the table is located on the left side of the point PNL1. In FIG. 2 (e), this is the case when ts _−NL <6 ps. This is usually used well. As is apparent from the figure, error 1 <error 2. This is because in FIG. 2E, since t _s-NL is only up to 6 ps, and the slope t _s-L (= t _s-NL ) = 5 ps is outside the table area, the error due to interpolation has increased. is there.

Finally, timing library synthesis is performed (S3). This synthesizes data based on the Libs _s-L and Libs _s-NL obtained in S1 and S2, and in the region where the control load capacitance C _cntl = 0 is smaller than the linear waveform input, Libt _s-L is used, and in other areas, non-linear waveform input Libt _s-NL is adopted. In other words, the combination of the inclination of the same signal waveform and the load capacitance C _L is when there is employed a libt _s-NL nonlinear waveform input. This is because the delay accuracy is higher than the result of linear waveform input. When only the load capacitance _CL is the same, the result may be replaced with a linear waveform input result (this embodiment corresponds to this). FIG. 2G and FIG. 2H show the synthesis results, and the error is smaller than the error 2.

As described above, according to the timing library creation method in the first embodiment, the characteristic extraction result by linear waveform input is obtained in the region where the slope of the signal waveform that cannot be obtained by characteristic extraction by nonlinear waveform input is small. By using this to obtain the slope, it is possible to prevent the delay time from deviating from the delay table parameter even if there is a delay calculation error, and as a result, a highly accurate timing library can be generated.
(Embodiment 2)
Hereinafter, Embodiment 2 of the present invention will be described with reference to FIG.

FIG. 3 is a characteristic extraction circuit diagram of a measurement target cell when a nonlinear waveform is input in the second embodiment.
The temporary driving cell 13 is, for example, a plurality of temporary driving cells 11 connected in parallel. Accordingly, since the driving capability can be increased as compared with the case where there is only one temporary driving cell 11, it is possible to obtain a smaller value of the signal waveform slope (ts _-NL ). Here, the logic cells used for the temporary drive cell 13 must have the same transition (the same input / output polarity). Otherwise, a desired signal waveform cannot be generated at the output of the temporary drive cell 13.

  As described above, according to the timing library creation method in the embodiment, the temporary drive cell having higher drive capability is used in the region where the slope of the signal waveform that cannot be obtained by the characteristic extraction by nonlinear waveform input is small. By calculating the slope using the result of characteristic extraction by linear waveform input, the delay time can be prevented from deviating outside the delay table parameters even if there is a delay calculation error, resulting in the generation of a highly accurate timing library. it can. In addition, it is not necessary to create a circuit having a particularly large transistor size in order to create a temporary driving cell having a high driving capability, so that new labor can be saved.

Flow chart showing the library creation method of the present invention (A) Conceptual diagram for explaining a method of extracting characteristics of a measurement target cell at the time of linear waveform input (b) A diagram illustrating a table illustrating a delay table of the measurement target cell at the time of linear waveform input (c) At the time of linear waveform input (D) A conceptual diagram for explaining a method of extracting characteristics of a measurement target cell at the time of nonlinear waveform input. (E) An example of a delay table of the measurement target cell at the time of nonlinear waveform input. (F) Graphical representation of the delay table of the measurement target cell at the time of nonlinear waveform input (g) Graphical representation of the delay table created by the timing library creation method of the present invention (h) A diagram showing a table exemplifying a delay table created by the timing library creation method Circuit for extracting characteristics of measurement object cell when nonlinear waveform is input in embodiment 2

Explanation of symbols

11 Temporary drive cell 12 Cell to be measured 13 Temporary drive cell

Claims (4)

A timing library creation method for each cell used for timing verification for a semiconductor integrated circuit having a plurality of cells including basic logic elements,
Providing a linear input signal waveform to the input terminal of the target cell to calculate a first timing library;
Providing a non-linear input signal waveform to the input terminal of the target cell to calculate a second timing library;
Synthesizing the timing library of the target cell using the first timing library in a region where the slope of the input signal waveform to each cell is small, and using the second timing library in other regions; A timing library creation method characterized by comprising:   The timing library creation method according to claim 1, wherein a temporary drive cell and a variable load capacitance are added to an input terminal of the target cell in order to generate the nonlinear input signal waveform.   The timing library creation method according to claim 2, wherein a plurality of temporary drive cells are connected and provided in parallel.   3. The timing library creation method according to claim 1, wherein the temporary drive cell is an inverter or a buffer.

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