JP2005110439A - Electric double layer capacitor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electric double layer capacitor device capable of monitoring the terminal-to-terminal voltage of one or more electric double layer capacitors. <P>SOLUTION: The electric double layer capacitor device comprises an electric double layer capacitor that is charged by a charging means, and is discharged by a load, and a voltage detecting means detecting the terminal-to-terminal voltage of the electric double layer capacitor, and producing the resulting detection output. Furthermore, the electric double layer capacitor device is provided with a voltage detecting means (voltage division circuit 16) that is disposed in an electric double layer capacitor 4, detects the terminal-to-terminal voltage of the electric double layer capacitor, compares it with a reference voltage, and produces detection output indicating the magnitude relation between the terminal-to-terminal voltage and the reference voltage. Or, the electric double layer capacitor device comprises a plurality of electric double layer capacitors (41 to 48). The electric double layer capacitor device is provided with voltage detecting means (voltage division circuit 16, voltage monitoring portions 61 to 68) that are connected with the electric double layer capacitors, detect the terminal-to-terminal voltages of the electric double layer capacitors, compare the terminal-to-terminal voltages with a reference voltage, and produces detection output indicating the magnitude relation between the terminal-to-terminal voltages and the reference voltage. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to monitoring of voltage between terminals of an electric double layer capacitor, and relates to an electric double layer capacitor device including a single or plural electric double layer capacitors.

  The electric double layer capacitor is small and has a large capacity, but has a low withstand voltage. Therefore, by forming an electric double layer capacitor device in series, the withstand voltage can be increased. This is a high breakdown voltage as an electric double layer capacitor device, and does not increase the breakdown voltage of each electric double layer capacitor in series. Therefore, it is necessary to control the charging voltage of each electric double layer capacitor constituting the electric double layer capacitor device so as not to exceed the withstand voltage and to monitor the charging state.

The following patent documents exist in the prior art regarding such an electric double layer capacitor device.
Utility Model Registration No. 2575358 This patent document 1 discloses an electric double layer capacitor device in which a plurality of electric double layer capacitors are connected in series, and this electric double layer capacitor device is connected in parallel to each electric double layer capacitor. A transistor is connected as a current control means, the charging voltage of the electric double layer capacitor is compared with a reference voltage, and the current flowing through the transistor is controlled according to the difference voltage, whereby the charging voltage of each electric double layer capacitor is controlled. It is a configuration for balancing.

  By the way, it is indispensable to control the charging voltage of each electric double layer capacitor to be constant in order to protect the electric double layer capacitor from damage. However, the voltage between terminals of each electric double layer capacitor is detected and monitored. This is important in order to stabilize the charging voltage. There is no description or suggestion of such a problem in Patent Document 1, and there is no disclosure or suggestion of the solution.

Therefore, an object of the present invention is to provide an electric double layer capacitor device that enables monitoring of the voltage between terminals of one or more electric double layer capacitors.

  In order to achieve the above object, an electric double layer capacitor device of the present invention detects an electric double layer capacitor that is charged by a charging means and connected to a load and discharges, and a voltage between terminals of the electric double layer capacitor. And a voltage detection means for generating the detection output.

  With such a configuration, the electric double layer capacitor is connected to the charging means, charged to a predetermined voltage, and discharged by the connected load. The voltage between the terminals of such an electric double layer capacitor is detected by the voltage detection means, and the detection output is output. This output form is transmitted by an electric signal or the like. Further, the voltage detection means may be either voltage detection by a comparison means with a reference voltage or voltage detection representing transition of the voltage between terminals. In the latter case, for example, a controller IC having a voltage detection function can be used.

  In order to achieve the above object, the electric double layer capacitor device of the present invention is installed in the electric double layer capacitor 4 and detects the voltage between the terminals of the electric double layer capacitor and compares it with a reference voltage. In this configuration, voltage detection means (a voltage dividing circuit 16 and a voltage monitoring unit 6) that generates a detection output indicating a magnitude relationship with the reference voltage is provided.

  According to such a configuration, the voltage detection means installed in the electric double layer capacitor detects the voltage between the terminals, and the detection output is obtained from the electric double layer capacitor. In this case, it is possible to monitor the voltage between the terminals using the detection output of the voltage detection means without directly detecting the voltage between the terminals of the electric double layer capacitor.

  In order to achieve the above object, a display means (display device 28) may be provided which indicates the voltage between the terminals of the electric double layer capacitor by the detection output of the voltage detection means. With such a configuration, it is possible to know the state of the voltage between the terminals from the display of the display means.

  In order to achieve the above object, an electric double layer capacitor device according to the present invention is an electric double layer capacitor device including a plurality of electric double layer capacitors (41 to 48), and is connected to the electric double layer capacitor. Voltage detection means (divided voltage) that detects a voltage between terminals of the electric double layer capacitor, compares the voltage between the terminals and the reference voltage, and generates a detection output indicating a magnitude relationship between the voltage between the terminals and the reference voltage. Circuit 16 and voltage monitoring units 61 to 68).

  According to such a configuration, the voltage between the terminals of each electric double layer capacitor is detected from the voltage detection means installed in each of the plurality of electric double layer capacitors, and each detection output is output from the voltage detection means. In this case, each detection output is an output representing the magnitude relationship based on the comparison between the voltage between the terminals of each electric double layer capacitor and the reference voltage. Therefore, it is possible to monitor the state of the voltage between the terminals of the plurality of electric double layer capacitors by each detection output.

  In order to achieve the above-mentioned object, it is possible to provide a control means (control unit 80) that receives the detection output of the voltage detection means and generates a display output representing the voltage across the terminals of the electric double layer capacitor. Good. That is, the control means receives the output of each voltage detection means, and obtains a display output of the voltage between the terminals of each electric double layer capacitor. The voltage between terminals of each electric double layer capacitor can be displayed by the display output.

  In order to achieve the above object, a charging means (charging device 30) for charging the electric double layer capacitor, and the detection output of the voltage detecting means, the electric double layer capacitor is set according to the voltage between the terminals. It is good also as a structure provided with the control means (control part 80) selectively charged with the said charging means. That is, when each electric double layer capacitor is charged by the charging means, the voltage between the terminals of each electric double layer capacitor can be detected, and the charging means can be controlled based on the detected output.

  In order to achieve the above object, a plurality of photocouplers (71 to 78) which are installed for each electric double layer capacitor and receive the detection output from the voltage detection means and connected in series, and these photocouplers It is good also as a structure provided with the control means (control part 80) which receives the said detection output through the series circuit of this, and recognizes the magnitude relationship of the said voltage between the said terminals of the said electric double layer capacitor.

With such a configuration, the detection output of the voltage between the terminals of each electric double layer capacitor is obtained from the voltage detection means installed for each electric double layer capacitor, and each detection output is taken out via the photocoupler. Each detection output is applied to the control means, and the magnitude relationship with the reference voltage is recognized. In this case, since the control means and each voltage detection means are electrically insulated by the photocoupler, there is no influence of the control means side on the electric double layer capacitor, and the electric double layer capacitor to the control means side is not affected. There is no effect. Therefore, the voltage between the terminals of the electric double layer capacitor can be monitored with high accuracy, and the reliability of the control of the voltage between the terminals can be improved.

  As described above, according to the present invention, the following effects can be obtained.

  (1) Information indicating the voltage between terminals of the electric double layer capacitor can be easily obtained, and the information can be used for controlling the use of the electric double layer capacitor and charging thereof.

(2) Information indicating the voltage between the terminals of each electric double layer capacitor in an electric double layer capacitor device having a plurality of electric double layer capacitors can be easily obtained, and the information on the use state of each electric double layer capacitor and its charge control In addition, the electric double layer capacitor device can be used for preventing uneven charging of the electric double layer capacitor and the like, and a highly reliable electric double layer capacitor device can be provided.

(First embodiment)
A first embodiment of the electric double layer capacitor device of the present invention will be described with reference to FIG. FIG. 1 shows a first embodiment of the electric double layer capacitor device of the present invention.

  For example, a 5-cell electric double layer capacitor 41, 42, 43, 44, 45 is connected in series to the electric double layer capacitor device 2 as a plurality of electric double layer capacitors. A voltage monitoring unit 6 is installed as a voltage detection means assigned in units of 5 cells. This voltage monitoring unit 6 can detect the voltage or temperature between terminals of each electric double layer capacitor 41 to 45 per cell, and the voltage or temperature between terminals can be detected through a detection voltage representing the voltage or temperature between the terminals. In this configuration, the monitoring result is output. In this case, the detection of the voltage or temperature between terminals includes, for example, not only detecting that the voltage or temperature exceeds a predetermined value but also measuring a specific voltage level or temperature level. The voltage monitoring unit 6 uses, for example, a serial wired system.

  The voltage monitoring unit 6 includes a regulator 602, a voltage conversion circuit 604, a controller 606, and the like. The regulator 602 is a power supply unit for the voltage conversion circuit 604 and the controller 606 and supplies power to the voltage conversion circuit 604 and the controller 606 using the serialized electric double layer capacitors 41 to 45 as a power source. The voltage between the terminals of each of the electric double layer capacitors 41 to 45 is applied to the voltage conversion circuit 604. The voltage conversion circuit 604 detects and converts the voltage between the terminals, and applies the converted output to the controller 606. The controller 606 receives the conversion output, monitors the voltage between terminals or temperature, and outputs signal data representing the monitoring result. In this case, the controller 606 is composed of, for example, an IC, and this controller 606 is provided with a transmission-only port 608 and a reception-only port 610. The transmission-only port 608 includes two signal lines 608A and 608B, The reception-only port 610 has a four-signal line configuration of two signal lines 610A and 610B. The signal insulation means 612 is installed in each of the signal lines 610A and 610B on the reception dedicated port 610 side.

  With such a configuration, the voltage between the terminals or the temperature of each of the electric double layer capacitors 41 to 45 is detected through the voltage conversion circuit 604, converted, added to the controller 606, and monitored. The power supply to the voltage conversion circuit 604 and the controller 606 is supplied from the electric double layer capacitors 41 to 45 through the regulator 602. For example, if 0.4 V per cell, for example, 2.0 for 5 cells. Since it becomes [V], the operation is possible even when the voltage between the terminals of each of the electric double layer capacitors 41 to 45 is 0.4 [V] or less, and a monitoring operation is obtained. The monitoring result is added to control means such as a personal computer (not shown) through the transmission dedicated port 608, and can be used for control of charging and the like.

(Second Embodiment)
Next, a second embodiment of the electric double layer capacitor device of the present invention will be described with reference to FIG. FIG. 2 shows a configuration of a DLC unit using the electric double layer capacitor device 2 as the second embodiment.

  This DLC unit 620 is configured to monitor one unit 80 cells with 16 circuit boards 6001 (# 0), 6002 (# 1), 6003 (# 2)... 6016 (# 15). Each circuit board 6001 to 6016 is provided with the described electric double layer capacitor device 2 (FIG. 1). The circuit boards 6001 to 6016 are connected in series to transmit a communication signal of monitoring data. In this embodiment, a single communication connector 630 is installed, and # 0, # 1,. The addresses (numbers) of the circuit boards 6001 to 6016 are shown. Each of the circuit boards 6001 to 6016 is set with a unique ID code, and a non-volatile memory (not shown) is installed as a storage unit, and the IC code is recorded in the non-volatile memory. In this embodiment, 80 electric double layer capacitors 401 to 480 are set as the plurality of electric double layer capacitors.

  In this case, the hardware configuration of the circuit boards 6001 to 6016 is set to be the same, and the software such as the signal processing is different for the circuit boards 6001 to 6016 at # 0, # 1 to # 14, and # 15. Thus, the communication signal and the termination process of the communication signal can be automatically recognized.

  With such a configuration, the terminal 632 is configured as a + terminal and the terminal 634 is configured as a-terminal. The DLC unit 620 can be connected in series or in parallel, and connected to a charging means or a load (not shown). Discharge, terminal voltage and temperature can be monitored. In this embodiment, 16 sets of the described electric double layer capacitor device 2 and 80 cells of the electric double layer capacitors 401 to 480 are configured as a single DLC unit 620, and the electric double layer capacitors 401 to 480 of the DLC unit 620 are configured. Monitoring data of terminal voltage and temperature can be output from the communication connector 630.

(Third embodiment)
Next, a third embodiment of the electric double layer capacitor device of the present invention will be described with reference to FIG. FIG. 3 shows the configuration of a DLC bank using the DLC unit 620 as the third embodiment.

  This DLC bank 640 forms a bank by connecting a plurality of 80-cell DLC units 6201, 6202, 6203... In series, parallel, or series-parallel. In the DLC bank 640, a bank controller 642 is installed for each serialized bank, and each bank is controlled. The bank controller 642 is configured to monitor the parallel DLC unit 6201 and the like.

  With such a configuration, the voltage or temperature between terminals of the electric double layer capacitors 401 to 480 of each cell is electrically monitored for a number of DLC units 6201, 6202, 6203... Constituting the DLC bank 640. Charging and discharging can be controlled.

(Fourth embodiment)
Next, the configuration of the DLC bank 640 will be described with reference to FIG. FIG. 4 shows the configuration of the DLC bank 640, where (A) shows the configuration of series connection and (B) shows the configuration of parallel connection.

  These DLC banks 640 collect terminal voltage and temperature data for each DLC unit 6201, 6202,... Including 80 electric double layer capacitors 4, for example, and control unit 644 collects, for example, 7 units. It is done.

  For these DLC banks 640, for example, as shown in FIG. 4A, in the configuration of serial connection, the burden on the wiring and the control unit 644 is small, but if an abnormality occurs in any unit, the entire data is I can't take it. Data communication is performed in order from all units. Each unit requires two communication connectors.

  For example, as shown in FIG. 4B, in the parallel connection configuration, even if an abnormality occurs in any unit, data of other units can be acquired. In addition, since data can be collected from all units simultaneously, the communication time is short. One communication connector is required for each unit.

  Whether to use the DLC bank 640 in series or in parallel can be determined after confirming actual operation in consideration of communication reliability and installation space. Two communication connectors are mounted, and both systems can be used as hardware.

  The voltage monitoring unit 6 in each unit is supplied with power from the internal electric double layer capacitor 4, but power is supplied to the control unit 644 independently from the outside. As a result, the reliability of the control operation is maintained.

(Fifth embodiment)
A fifth embodiment of the electric double layer capacitor device of the present invention will be described with reference to FIG. FIG. 5 shows a fifth embodiment of the electric double layer capacitor device of the present invention.

The electric double layer capacitor device 2 constitutes a capacitor unit including, for example, an electric double layer capacitor 4 as a single electric double layer capacitor. An external terminal 8 is provided on the positive electrode 7 of the electric double layer capacitor 4, and an external terminal 12 is provided on the negative electrode 10. A voltage monitoring unit 6 is installed between the positive electrode 7 and the negative electrode 10 of the electric double layer capacitor 4. In this embodiment, the reference voltage source circuit 14 and the voltage dividing circuit 16 include a resistor 18, 20, a voltage processing unit 22 is connected between the positive electrode 7 and the negative electrode 10 to constitute a voltage monitoring unit 6. In this embodiment, the reference voltage source circuit 14 generates the reference voltage V _ref using the electric double layer capacitor 4 as a power source, and the voltage dividing circuit 16 divides and outputs the voltage V _T between the terminals of the electric double layer capacitor 4. The voltage processing unit 22 includes a voltage comparator 24 and a processor 26, and includes an IC. For example, the voltage comparator 24 compares the detection voltage V _S obtained from the inter-terminal voltage V _T with the reference voltage V _ref, and the processor 26 outputs voltage information V _DA representing the comparison result by the voltage comparator 24.

In the electric double layer capacitor device 2, the reference voltage source circuit 14, the voltage dividing circuit 16, and the voltage processing unit 22 may be installed in the casing of the existing electric double layer capacitor 4. Moreover, you may provide the indicator 28 which optically displays output information on the output side of the processor 26. FIG. And the charging device 30 is connected to the external terminals 8 and 12, and the electric double layer capacitor 4 is good also as a structure charged by 2.5V, for example. The charging device 30 may be configured to generate a DC voltage V _DC and a constant current by being fed with a commercial AC power supply 32.

In such a configuration, when charging of the electric double layer capacitor 4 proceeds and exceeds a predetermined voltage, the reference voltage source circuit 14 operates to generate the reference voltage V _ref . At this time, the voltage V _T between the terminals is divided by the voltage dividing circuit 16, and the detection voltage V _S corresponding to the resistance ratio of the resistors 18 and 20 is obtained. Here, if the resistance values of the resistors 18 and 20 are R ₁ , R _2, or both are R, the detection voltage V _S is
V _S = V _T · R ₂ / (R ₁ + R ₂ ) = V _T · R / 2R
= V _T / 2 (1)
It becomes. In this case, if the reference voltage source circuit 14 is provided with a unique battery, the reference voltage V _ref can be generated regardless of the voltage V _T between the terminals of the electric double layer capacitor 4.

The detection voltage V _S and the reference voltage V _ref are compared by the voltage comparator 24, and a comparison output representing the magnitude relationship is obtained. In this case, the voltage comparator 24 may have either a configuration for obtaining an output indicating that the detection voltage V _S exceeds the reference voltage V _ref or a configuration for obtaining an output indicating a level corresponding to the difference voltage. When such a comparison output is applied to the processor 26, voltage information V _DA corresponding to the comparison output is calculated and output from the processor 26. If configured to include a display 28 on the output side of this processor 26, terminal voltage V _T is a predetermined voltage, in this case, it can be optically display the detected voltage V _S exceeds the reference voltage V _ref, Moreover, it can display at the level according to the comparison value. The user can easily visually recognize the level of the terminal voltage V _T from the display. The indicator 28 can be composed of a light emitting element such as an LED, and can also be composed of a sounding element such as a buzzer. According to the indicator 28 composed of a sound generating element, the level of the voltage V _T between the terminals of the electric double layer capacitor 4 can be audibly recognized by a buzzer sound.

In this embodiment, the detection voltage V _S obtained from the voltage dividing circuit 16 and the reference voltage V _ref are compared. However, the inter-terminal voltage V _T and the comparison voltage VR may be compared. In addition, although the voltage comparator 24 is illustrated as being separated from the processor 26, the processor 26 may have a voltage comparison function.

Next, level comparison of the voltage comparator 24 will be described with reference to FIG. FIG. 6 is a graph showing the relationship between the transition of the detection voltage V _S corresponding to the inter-terminal voltage V _T of the electric double layer capacitor 4 and the reference voltage V _ref . In this case, the relationship between the detection voltage V _S and the inter-terminal voltage V _T is expressed by Equation (1) if the resistors 18 and 20 have the same resistance value R.

For example, when the electric double layer capacitor 4 is charged by the charging device 30 having a constant current output, the voltage V _T between the terminals rises linearly and the detection voltage V _S rises in the same manner. When the reference voltage source circuit 14 generates the reference voltage V _ref in response to the inter-terminal voltage V _T , the reference voltage V _ref is compared with the detected voltage V _S (= V _T / 2) generated in the voltage dividing circuit 16. As a result, a comparison output corresponding to the magnitude relationship between the two is obtained in the voltage comparator 24 and applied to the processor 26. In this case, the comparison output may be any voltage such as a voltage indicating that the detection voltage V _S has reached the reference voltage V _ref , or a voltage corresponding to a difference voltage between the two.

Further, after the detection voltage V _S reaches the reference voltage V _ref , a load (not shown) is connected to the external terminals 8 and 12, and when power is consumed by the load, the inter-terminal voltage V _T decreases. . This reduced state also appears in the detection voltage V _S , and an output representing the reduced voltage is obtained from the voltage comparator 24. Therefore, if the voltage information V _DA obtained by the processor 26 is used as a control input for starting or stopping charging of the charging device 30, charging is stopped when the detected voltage V _S exceeds the reference voltage V _ref , and the reference If charging is started when the voltage is lower than the voltage V _ref , the inter-terminal voltage V _T can be controlled to a constant charging voltage. In this case, in order to slow down charging / discharging, if a hysteresis characteristic is given by giving a voltage width to the reference voltage of the charging start voltage and the charging stop voltage, charging / discharging chattering can be prevented.

(Sixth embodiment)
A sixth embodiment of the electric double layer capacitor device of the present invention will be described with reference to FIG. FIG. 7 shows a sixth embodiment of the electric double layer capacitor device of the present invention.

  In the electric double layer capacitor device 40, eight electric double layer capacitors 41, 42, 43, 44, 45, 46, 47, and 48 are installed as a plurality of electric double layer capacitors. A series circuit of capacitors 41 to 44 and a series circuit of electric double layer capacitors 45 to 48 are connected in parallel to form a series-parallel circuit. The number of series of the plurality of electric double layer capacitors may be 9 or more, may be 8 or less, and the circuit configuration may be only a series circuit, not a series-parallel circuit. In short, it is determined by a request for a desired capacity and breakdown voltage. Then, common external terminals 50 and 52 are formed, and the above-described charging device 30 and the like are connected to the external terminals 50 and 52, for example.

  In addition, voltage monitoring units 61, 62, 63, 64, 65, 66, 67, 68 are installed corresponding to the electric double layer capacitors 41 to 48, and the voltage monitoring units 61 to 68 and the electric double layer capacitors 41 to 68 are installed. 48, the electric double layer capacitor 41 has a voltage monitoring unit 61, the electric double layer capacitor 42 has a voltage monitoring unit 62, and the like. In this embodiment, the voltage monitoring units 61 to 68 are configured by ICs, and each has a unique ID code. The power supply of each voltage monitoring part 61-68 is applied with the charging voltage of each electric double layer capacitor 41-48, and the voltage monitoring part 61-68 is provided with the measurement function of the voltage between terminals of each electric double layer capacitor 41-48. In addition, it has a data communication function and collects voltage monitoring data measured from the electric double layer capacitors 41 to 48.

  Photocouplers 71, 72,... 78 are connected to the output sides of the voltage monitoring units 61-68 as insulation means for the data communication path, and are connected to the control unit 80 via the photocouplers 71-78. The control unit 80 receives the voltage monitoring data collected through the photocouplers 71 to 78, and monitors and controls the voltage between the terminals of the electric double layer capacitors 41 to 48.

  Each voltage monitoring part 61-68 is the structure shown in FIG. 8, for example. The voltage monitoring units 61 to 68 include the reference voltage source circuit 14, the voltage dividing circuit 16, and the voltage processing unit 22 of the electric double layer capacitor device 2 (FIG. 5) described above. As described above.

  For example, as shown in FIG. 9, the photocouplers 71 to 78 include a light emitting diode 82 and a light receiving transistor 84 connected to the output side of the processor 26, and receive light from the light emitting diode 82 by the light receiving transistor 84. The output is obtained from the light receiving transistor 84 in response to the received light.

  The voltage monitoring processing operation or method for the electric double layer capacitor device 40 having such a configuration will be described.

The transition of the inter-terminal voltage V _T according to the charging of the electric double layer capacitors 41 to 48 is as described with reference to FIG. 6, and the voltage monitoring data is output from the voltage monitoring units 61 to 68. . For example, the voltage monitoring data includes 32 bits of a fixed code (8 bits), an ID code (16 bits), and voltage measurement data (8 bits) as a unit (packet), and FIG. 10 shows an example thereof.

  Therefore, in the control unit 80, ID codes related to the voltage monitoring units 61 to 68 to be acquired are set in the packet, and are sequentially transmitted to the voltage monitoring units 61 to 68. In this case, in the voltage monitoring data, the voltage measurement voltage Is set to $ 0, so that it can be distinguished from normal data.

  The ID code is a key for dialogue between the control unit 80 and each of the voltage monitoring units 61 to 68, and the voltage monitoring units 61 to 68 respond according to the specified ID code. That is, for example, the voltage monitoring unit 61 that has received the packet checks the ID code, and if it is not the corresponding ID code, there is no response, for example, the data is not changed and is transferred to the next voltage monitoring unit 62 It will be. Such an operation is sequentially performed from the voltage monitoring units 61 to 68, and when the packet is transmitted to the last voltage monitoring unit 68, the packet transmitted by the voltage monitoring unit 68 is returned to the control unit 80. In addition, the control unit 80 recognizes the coincidence and inconsistency of each ID code, checks that the measurement data that is the voltage monitoring data has been rewritten, and confirms the reliability of the data together with the voltage monitoring.

  In the data management process of the control unit 80, the data monitoring time of the voltage monitoring units 61 to 68 is, for example, the maximum communication time of the voltage monitoring units 61 to 68 is 200 u seconds, and is managed by the control unit 80. Assuming that the number of electric double layer capacitors 41 to 48 to be 1000 is, for example, 200 msec is required to obtain the voltage of any one electric double layer capacitor. Therefore, it takes about 200 seconds (3.4 minutes) to collect all 1000 data.

  Next, other embodiments and modifications of the electric double layer capacitor device of the present invention will be described below.

  (1) When the voltage monitoring units 61 to 68 are constituted by an IC, the operating voltage is 1.8V to 3.6V, and when the electric double layer capacitors 41 to 48 are used as a power source, the low voltage state. It is expected that the operation cannot be secured. In this case, operation compensation can be performed by installing a power source for each of the voltage monitoring units 61 to 68 or installing a common power source.

  (2) Although the data collection time increases depending on the number of electric double layer capacitors installed, the signal is transmitted from the control unit 80 without specifying the ID code, and the measurement result is returned only from the voltage monitoring unit detecting the abnormal voltage. By this method, the data collection time can be shortened.

(3) In the embodiment, the photocoupler is exemplified as the communication path insulating means. However, a transformer, a transistor circuit, or the like may be used instead of the photocoupler.

According to the present invention, information on the voltage between terminals of the electric double layer capacitor can be easily obtained, the information can be utilized for voltage management and temperature management of the voltage between terminals, and the electric double layer capacitor device utilized as a power supply device. The range of use can be expanded and is useful.

1 is a circuit diagram showing an electric double layer capacitor device according to a first embodiment of the present invention. It is a figure which shows the structure of the DLC unit which concerns on the 2nd Embodiment of this invention. It is a figure which shows the structure of the DLC bank which concerns on the 3rd Embodiment of this invention. It is a figure which shows the connection structure of the DLC bank which concerns on the 4th Embodiment of this invention. It is a circuit diagram which shows the electric double layer capacitor | condenser apparatus which concerns on the 5th Embodiment of this invention. It is a figure which shows transition of the detection voltage of the voltage between terminals of an electrical double layer capacitor, and the comparison with the detection voltage and a reference voltage. It is a block diagram which shows the electric double layer capacitor | condenser apparatus which concerns on the 6th Embodiment of this invention. It is a circuit diagram which shows the voltage monitoring part of the electric double layer capacitor | condenser apparatus which concerns on 6th Embodiment. It is a circuit diagram which shows the photocoupler of the electric double layer capacitor | condenser apparatus which concerns on 6th Embodiment. It is a figure which shows the structure of communication data.

Explanation of symbols

2, 40 Electric double layer capacitor device 4, 41-48 Electric double layer capacitor 6, 61-68 Voltage monitoring unit (voltage detection means)
16 Voltage divider (voltage detection means)
28 Display (display means)
30 Charging device (charging means)
71-78 Photocoupler 80 Control section (control means)
620 DLC unit 640 DLC bank

Claims (7)

An electric double layer capacitor that is charged by a charging means and connected to a load for discharging;
Voltage detecting means for detecting a voltage between terminals of the electric double layer capacitor and generating a detection output thereof;
An electric double layer capacitor device comprising:   Voltage detection means installed in an electric double layer capacitor, detecting a voltage between terminals of the electric double layer capacitor and comparing it with a reference voltage, and generating a detection output indicating a magnitude relationship between the voltage between the terminals and the reference voltage. An electric double layer capacitor device comprising:   3. The electric double layer capacitor device according to claim 1, further comprising display means for indicating the voltage between the terminals of the electric double layer capacitor based on the detection output of the voltage detection means. An electric double layer capacitor device comprising a plurality of electric double layer capacitors,
Detecting the voltage between the terminals of the electric double layer capacitor connected to the electric double layer capacitor, comparing the voltage between the terminals and the reference voltage, and indicating the magnitude relationship between the voltage between the terminals and the reference voltage Voltage detection means for generating an output;
An electric double layer capacitor device comprising:   5. The electric double layer capacitor device according to claim 4, further comprising control means for receiving the detection output of the voltage detection means and generating a display output representing the voltage across the terminals of the electric double layer capacitor. Charging means for charging the electric double layer capacitor;
5. The electric circuit according to claim 4, further comprising control means for receiving the detection output of the voltage detection means and selectively charging the electric double layer capacitor by the charging means in accordance with the voltage between the terminals. Multi-layer capacitor device. A plurality of photocouplers connected in series, receiving the detection output from the voltage detection means installed for each electric double layer capacitor,
Control means for receiving the detection output through a series circuit of these photocouplers and recognizing the magnitude relationship of the voltage between the terminals of the electric double layer capacitor;
The electric double layer capacitor device according to claim 4, further comprising: