JP2005101864A - Drive method of solid-state image pickup element and solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the drive method of a solid-state image pickup element with which dark current can be reduced, an image with sufficient image quality can be obtained, and charge quantity that a light receiving sensor deals with can sufficiently be secured; and to provide a solid-state imaging device having the solid-state image pickup element. <P>SOLUTION: In the solid-state image pickup element 10, a second conductive semiconductor region 14 is formed on the surface of the first conductive charge accumulation region 13 of the light receiving sensor. An element separation layer 20 formed of an insulating layer is embedded in a groove formed in a semiconductor substrate 11. An electrode 22 is embedded and formed in the element separation layer 20. At least in a light receiving period, voltage ΦV1 is applied to the electrode 22, and an accumulation layer where multiple carriers of the second conductive semiconductor region 14 are accumulated is formed at the periphery of the element separation layer 20. The solid-state imaging device is provided with the solid-state image pickup element 10 and a voltage applying means applying voltage ΦV1 to the electrode 22. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for driving a solid-state imaging device, and a solid-state imaging device including the solid-state imaging device.

  Due to the downsizing of the pixel cell of the solid-state imaging device, in particular, in the CMOS sensor (CMOS solid-state imaging device), a trench element isolation structure (so-called STI; Shallow Trench Isolation) should be adopted for the pixel portion as well as the peripheral circuit portion. There is.

  Further, in the light receiving sensor section, it has become common to adopt an embedded photodiode structure for reducing dark current.

When the trench element isolation structure is employed in the pixel portion as described above, the depletion layer extending from the light receiving sensor portion reaches the side surface of the trench element isolation layer, so that the SiO ₂ / There arises a problem that dark current is generated at the Si interface.
For this reason, it is required to suppress the dark current on the side surface of the trench element isolation layer.

Even when trench element isolation is not performed, it is desired to reduce the generation of dark current in the pixel portion as much as possible in order to achieve high sensitivity.
Thus, it is considered to reduce the dark current in the pixel portion in a structure in which element isolation is performed by the LOCOS method.
For example, a method of reducing dark current by forming a P ⁺ region below or in the vicinity of the LOCOS element isolation layer and forming the N layer of the photoelectric conversion part deeper than the LOCOS element isolation layer (see Patent Document 1). Proposed.
Further, for example, a LOCOS element isolation layer is used for the peripheral circuit portion, and a polycrystalline silicon oxide film is formed on the P ⁺ region of the isolation region instead of the LOCOS element isolation layer around the transistor and the light receiving portion of the pixel portion. A method of reducing the stress and reducing the dark current (see Patent Document 2) has been proposed.
JP-A-10-308507 JP-A-11-312731

Accordingly, when a trench element isolation structure is employed in the pixel portion, a P ⁺ region may be formed around the trench element isolation layer in order to suppress dark current on the side surface of the trench element isolation layer.

Here, FIG. 2 shows a schematic cross-sectional view of a CMOS type solid-state imaging device having a structure employing a trench element isolation structure and a buried photodiode structure.
In this solid-state imaging device 50, a P-type semiconductor well region 52 is formed on an upper portion of a substrate 51. In this P-type semiconductor well region 52, an N-type semiconductor region 53 serving as a charge accumulation region of a light-receiving sensor unit and an N ⁺ floating region. A diffusion 56 is formed.
A P-type (P ⁺ ) positive charge accumulation region 54 is formed near the surface of the substrate 51 on the N-type semiconductor region 53.
These P-type semiconductor well region 52, N-type semiconductor region 53, and P-type positive charge storage region 54 form a so-called buried photodiode structure.

In addition, a trench element isolation layer 60 made of an insulating layer (for example, silicon oxide, silicon nitride, or a multilayer thereof) is formed to electrically isolate the transistor and the photodiode of the light receiving sensor unit. In the vicinity of the surface of the substrate 51, regions such as a photodiode of the light receiving sensor part and a source / drain of a transistor are formed.
The positive charge accumulation region 54 is formed in contact with the trench element isolation layer 60 and has a larger area than the N-type semiconductor region 53.

A gate insulating film 57 is formed on the surface of the substrate 51, and a read gate electrode 58 and a reset gate electrode 59 are formed on the gate insulating film 57.
The read gate electrode 58, the gate insulating film 57, the N-type semiconductor region 53 of the light receiving sensor portion, and the floating diffusion 56 constitute a read transistor. A channel region of the read transistor, that is, between the floating diffusion 56 and the N-type semiconductor region 53 is a read region 55.
Furthermore, if necessary, components such as a color filter and an on-chip lens are provided above to form the solid-state imaging device 50.

In the solid-state imaging device 50, a P-type (P ⁺ ) semiconductor region 61 is formed around the trench element isolation layer 60 (side walls and below). This P-type semiconductor region 61 can reduce dark current generated around the trench element isolation layer 60.

  However, in order to sufficiently suppress the generation of dark current around the trench element isolation layer 60, it is necessary to form the P-type semiconductor region 61 thick or to increase the concentration of P-type impurities in the P-type semiconductor region 61. is there.

  When the P-type semiconductor region 61 is formed thick, the N-type semiconductor region 53 of the light-receiving sensor portion becomes smaller by that amount, and the amount of signal charge that can be accumulated (handled charge amount) is reduced. It becomes difficult to secure the range.

  Further, when the concentration of the P-type impurity in the P-type semiconductor region 61 is increased, the P-type impurity in the P-type semiconductor region 61 is likely to diffuse at the time of manufacture. As a result, the amount of signal charge (handled charge amount) that can be accumulated in the N-type semiconductor region 53 of the light receiving sensor portion is reduced.

  In order to solve the above-described problems, in the present invention, a solid-state imaging device capable of reducing dark current and obtaining an image with good image quality and ensuring a sufficient amount of charge handled by the light receiving sensor unit. And a solid-state imaging device including the solid-state imaging device.

  According to the solid-state imaging device driving method of the present invention, the second conductive type semiconductor region is formed on the surface of the first conductive type charge storage region of the light receiving sensor unit, and the insulating layer is formed in the groove formed in the semiconductor substrate. An element isolation layer is embedded and formed, and a voltage is applied to the electrode at least during a light receiving period with respect to a solid-state imaging device having a structure in which an electrode is embedded in the element isolation layer. An accumulation layer for accumulating majority carriers in the semiconductor region of the second conductivity type is formed around the separation layer.

  In the solid-state imaging device according to the present invention, the second conductivity type semiconductor region is formed on the surface of the first conductivity type charge storage region of the light receiving sensor unit, and the element isolation layer is formed of an insulating layer in the groove formed in the semiconductor substrate. Is embedded, and an electrode is embedded in the element isolation layer, and a solid-state imaging device and a voltage applying means for applying a voltage to the electrode are provided.

  In the solid-state imaging device driving method of the present invention and the solid-state imaging device of the present invention, the solid-state imaging element has a configuration in which a second conductivity type semiconductor region is formed around the element isolation layer. it can.

In the driving method of the solid-state imaging device of the present invention, the charge accumulation region is an N-type semiconductor region, and a negative voltage can be applied to the electrode during the light receiving period.
In the solid-state imaging device of the present invention, the charge storage region may be an N-type semiconductor region, and the voltage applying unit may be controlled to apply a negative voltage to the electrode at least during the light receiving period.

According to the driving method of the solid-state imaging device of the present invention described above, the solid-state imaging device has a configuration in which the second conductive type semiconductor region is formed on the surface of the first conductive type charge storage region of the light receiving sensor unit. Therefore, the dark current in the vicinity of the substrate surface of the light receiving sensor unit can be reduced.
A storage layer that accumulates majority carriers in the semiconductor region of the second conductivity type around the element isolation layer made of an insulating layer by applying a voltage to the electrode formed inside the element isolation layer at least during the light receiving period. This storage layer causes the side wall of the element isolation layer in the vicinity of the first conductivity type charge storage region (signal charge storage layer) of the light receiving sensor portion to be pinned by the storage layer, and from the interface of the side wall of the element isolation layer. Generation of dark current can be suppressed.

According to the above-described configuration of the solid-state imaging device of the present invention, the solid-state imaging device has a configuration in which the second conductive type semiconductor region is formed on the surface of the first conductive type charge storage region of the light receiving sensor unit. The dark current in the vicinity of the substrate surface of the light receiving sensor portion can be reduced.
And by providing a voltage applying means for applying a voltage to the electrode formed in the element isolation layer, a predetermined voltage is applied from the voltage applying means to the electrode formed in the element isolation layer. When applied, it is possible to form an accumulation layer for accumulating majority carriers in the semiconductor region of the second conductivity type described above, and to suppress the generation of dark current from the side wall interface of the element isolation layer.

  Further, in the solid-state imaging device driving method and the solid-state imaging device of the present invention, when the solid-state imaging device has a configuration in which a second conductivity type semiconductor region is formed around the element isolation layer, this element is used. Generation of dark current from the interface of the side wall of the element isolation layer can also be suppressed by the second conductivity type semiconductor region around the isolation layer. Thereby, the generation of dark current from the interface of the sidewall of the element isolation layer can be more effectively suppressed together with the above-described accumulation layer.

  According to the above-described present invention, it is possible to suppress the generation of dark current from the interface of the side wall of the element isolation layer, so that the dark current in the pixel portion can be reduced.

In particular, when the solid-state imaging device has a configuration in which the second conductivity type semiconductor region is formed around the element isolation layer, the second conductivity type is formed by applying a voltage to the second conductivity type semiconductor region and the electrode. Together with the accumulation layer for accumulating majority carriers in the conductive type semiconductor region, generation of dark current from the interface of the side wall of the element isolation layer can be more effectively suppressed.
Also, the second conductivity type semiconductor region is compared with the configuration in which the generation of dark current from the interface of the side wall of the element isolation layer is suppressed only by the second conductivity type semiconductor region formed around the element isolation layer. Even if the acceptor concentration is reduced or the thickness is reduced, the dark current can be sufficiently suppressed, so that the area of the charge accumulation region of the first conductivity type of the light receiving sensor portion is not compressed. The charge amount that can be accumulated in the light receiving sensor section, that is, the handling charge amount can be kept high.
This makes it possible to ensure a desired dynamic range.

  Therefore, according to the present invention, it is possible to realize a solid-state imaging device that has a low dark current and can obtain an image with good image quality.

As an embodiment of the solid-state imaging device of the present invention, a schematic cross-sectional view of a solid-state imaging device portion is shown in FIG. FIG. 1 shows a cross-sectional view of one pixel cell.
In this embodiment, the present invention is applied to a CMOS sensor (CMOS type solid-state imaging device).

A P-type semiconductor well region 12 is formed on the substrate 11, and an N-type semiconductor region 13 serving as a charge storage region of the light receiving sensor portion and an N ⁺ floating diffusion 16 are formed in the P-type semiconductor well region 12. .
In addition, a P-type (P ⁺ ) positive charge accumulation region 14 is formed near the surface of the substrate 11 on the N-type semiconductor region 13.
The P-type semiconductor well region 12, the N-type semiconductor region 13, and the P-type positive charge storage region 14 form a so-called buried photodiode structure.

  Further, a trench element isolation layer 20 made of an insulating layer (for example, silicon oxide, silicon nitride, or a multilayer thereof) for electrically isolating the transistor and the photodiode of the light receiving sensor unit is formed. This trench element isolation layer 20 In the vicinity of the surface of the substrate 11 in the middle, regions such as a photodiode of the light receiving sensor part and a source / drain of the transistor are formed.

A gate insulating film 17 is formed on the surface of the substrate 11, and a read gate electrode 18 and a reset gate electrode 19 are formed on the gate insulating film 17.
A read transistor is configured by the read gate electrode 18, the gate insulating film 17, the N-type semiconductor region 13 of the light receiving sensor portion, and the floating diffusion 16. A channel region of the read transistor, that is, between the floating diffusion 16 and the N-type semiconductor region 13 is a read region 15.
Furthermore, if necessary, components such as a color filter and an on-chip lens are provided above to constitute the solid-state imaging device 10.

In the present embodiment, in particular, the electrode 22 is embedded in the trench element isolation layer 20 made of an insulating layer.
Further, a P-type (P ⁺ ) semiconductor region 21 is formed around the trench element isolation layer 20 (side wall and below).

As a material of the electrode 22, for example, polycrystalline silicon, more preferably, polycrystalline silicon doped with impurities to reduce resistance can be used.
As a method for forming the electrode 22, for example, after forming the trench element isolation layer 20, a method of forming a groove therein and embedding the material of the electrode 22, and after forming a trench for the trench element isolation layer 20, A method may be considered in which the insulating layer is formed so as not to completely fill the inside of the trench to form the trench element isolation layer 20, and the material of the electrode 22 is buried in the remaining portion. In the former case, the P-type semiconductor region 21 may be formed after the electrode 22 is embedded.

Further, in the present embodiment, a solid-state imaging device is configured by including voltage application means (for example, a circuit such as a power supply circuit or wiring) that applies a voltage φV1 to the electrode 22.
At least in the light receiving period, a negative voltage (for example, −5 V) is applied to the electrode 22 as the voltage φV1 through the voltage applying unit.
That is, the solid-state imaging device in which the voltage application unit is controlled so as to apply a negative voltage to the electrode 22 at least during the light receiving period is configured.

  By thus applying a negative voltage to the electrode 22, a hole accumulation layer is formed in the vicinity of the sidewall of the trench element isolation layer 20, and the interface of the trench element isolation layer 20 is pinned by positive charges (holes). Thereby, together with the P-type semiconductor region 21 formed around the trench element isolation layer 20, it is possible to suppress the generation of dark current from the interface of the sidewall of the trench element isolation layer 20.

  Compared with the structure shown in FIG. 2, in the case of the present embodiment, even if the thickness of the P-type semiconductor region 21 and the concentration of P-type impurities (acceptor concentration) are small, the trench element isolation layer 20 It is possible to sufficiently suppress the generation of dark current from the side walls.

In order to suppress dark current when the hole storage layer is formed by applying a negative voltage to the electrode 22 without providing the P-type semiconductor region 21 around the trench isolation layer 20 ( It is necessary to apply a large negative voltage (for example, -15V).
Therefore, it is desirable to provide the P-type semiconductor region 21 around the trench element isolation layer 20.

  According to the above-described embodiment, the electrode 22 is embedded in the trench element isolation layer 20, the voltage φV1 is applied to the electrode 22, and a negative voltage is applied as the voltage φV1 at least in the light receiving period. As a result, a hole accumulation layer can be formed in the vicinity of the sidewall of the trench element isolation layer 20 and the interface can be pinned. Thereby, together with the P-type semiconductor region 21 formed around the trench element isolation layer 20, it is possible to suppress the generation of dark current from the sidewall of the trench element isolation layer 20.

Further, since a negative voltage is applied to the electrode 22 to form a hole accumulation layer, the P-type impurity concentration in the P-type semiconductor region 21 around the trench isolation layer 20 is compared with that in the configuration shown in FIG. Even if it is reduced or the thickness of the P-type semiconductor region 21 is reduced, the dark current can be sufficiently suppressed.
Accordingly, since the area of the N-type semiconductor region 13 that serves as a signal storage region of the light receiving sensor portion can be set large, the charge amount that can be stored (handled charge amount) can be maintained high, and a desired dynamic range can be secured. It becomes possible to do.

In the above-described embodiment, in the N-type semiconductor region 13 and the positive charge storage region 14, the end portion on the read region 15 side is at the same planar position, but the end portion of the N-type semiconductor region 13 is on the read region 15 side. It may be formed so as to protrude.
In this way, by forming so as to protrude to the read region 15 side, the read voltage applied to the read gate electrode 18 can be set low.

In the above-described embodiment, the charge accumulation region of the light receiving sensor portion is an N-type semiconductor region, and a P-type positive charge accumulation region is formed on the surface of the N-type semiconductor region, so that a so-called embedded photodiode structure is formed. Although the structure is formed, the present invention can be similarly applied to the case of the reverse conductivity type.
In the case of the reverse conductivity type, an N-type semiconductor region (negative charge storage region) is formed on the surface of the P-type charge storage region to constitute a buried photodiode structure. An N-type semiconductor region is formed around the trench isolation layer to reduce dark current. In this case, by applying the present invention, a positive voltage is applied to the electrode inside the trench element isolation layer at least during the light receiving period, and an accumulation layer of electrons is formed around the trench element isolation layer. The interface may be pinned by a layer.
That is, in the present invention, a buried conductive photodiode structure is formed by forming a second conductive type semiconductor region on the surface of the first conductive type charge storage region, and at least during the light receiving period, the electrode inside the trench element isolation layer is formed. A voltage is applied to form an accumulation layer for accumulating majority carriers in the semiconductor region of the second conductivity type around the trench element isolation layer, and the interface is pinned. Preferably, a second conductivity type semiconductor region is also formed around the trench element isolation layer.

In the above-described embodiment, the present invention is applied to a CMOS solid-state image sensor. However, the present invention can also be applied to solid-state image sensors having other configurations, such as a CCD solid-state image sensor. .
When the present invention is applied to a CCD solid-state imaging device, for example, a trench element isolation layer is formed in a portion that becomes a so-called channel stop region, and an electrode is embedded in the trench element isolation layer. A voltage for pinning the sidewall of the element isolation insulating layer is applied.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

1 is a schematic configuration diagram (a cross-sectional view of a pixel portion of a solid-state imaging device) of an embodiment of a solid-state imaging device of the present invention. It is a schematic sectional drawing of the CMOS type solid-state image sensor which employ | adopted the trench element isolation structure and the embedded photodiode structure.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Solid-state image sensor, 11 Substrate, 12 P-type semiconductor well region, 13 N-type semiconductor region, 14 Positive charge storage region, 15 Read-out region, 16 Floating diffusion, 17 Gate insulating film, 18 Read-out gate electrode, 19 Reset gate electrode , 20 Trench element isolation layer, 21 P-type semiconductor region, 22 electrodes

Claims (6)

A second conductivity type semiconductor region is formed on the surface of the first conductivity type charge storage region of the light receiving sensor unit,
In the groove formed in the semiconductor substrate, an element isolation layer made of an insulating layer is embedded and formed,
For a solid-state imaging device having a configuration in which an electrode is embedded in the element isolation layer,
A solid-state imaging device, wherein a voltage is applied to the electrode at least during a light receiving period, and a storage layer for storing majority carriers in the semiconductor region of the second conductivity type is formed around the device isolation layer. Driving method.   The solid-state imaging device driving method according to claim 1, wherein the solid-state imaging device has a second conductivity type semiconductor region formed around the element isolation layer.   2. The method for driving a solid-state imaging device according to claim 1, wherein the charge accumulation region is an N-type semiconductor region, and a negative voltage is applied to the electrode during the light receiving period. A second conductivity type semiconductor region is formed on the surface of the first conductivity type charge storage region of the light receiving sensor portion, and an element isolation layer made of an insulating layer is embedded in a groove formed in the semiconductor substrate. A solid-state imaging device having a configuration in which an electrode is embedded in the element isolation layer;
A solid-state imaging device comprising: a voltage applying unit that applies a voltage to the electrode.   The solid-state imaging device according to claim 4, wherein the solid-state imaging device has a second conductivity type semiconductor region formed around the element isolation layer.   5. The solid-state imaging device according to claim 4, wherein the charge accumulation region is an N-type semiconductor region, and the voltage application unit is controlled to apply a negative voltage to the electrode at least during a light receiving period. .

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