JP2005101630A - Manufacturing method of semiconductor member - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a substrate from being cracked while enabling reuse of a substrate and to obtain a semiconductor member by an easy method.
A process of attaching a film 2005 on a substrate 2000 including a porous semiconductor layer 2002 and a non-porous layer 2003, and applying a force in a direction to peel the film 2005 from the substrate 2000 to the film 2005. A step of separating the non-porous layer 2003 and the porous semiconductor layer 2002 from the substrate side to the film 2005 side with the porous semiconductor layer 2002 as a boundary, and a step of bonding the separated non-porous layer 2003 to the second substrate .
[Selection] Figure 4

Description

  The present invention relates to a method for manufacturing a semiconductor member for forming a semiconductor element such as a semiconductor integrated circuit, a solar cell, a semiconductor laser, or a light emitting diode, and more particularly to a method for manufacturing a semiconductor member having a step of separating a substrate.

  The semiconductor member is known by the name of a semiconductor wafer, a semiconductor substrate, a semiconductor device, etc., and a semiconductor element formed using the semiconductor region or a state before the semiconductor element is formed. Shall be included.

  Some of such semiconductor members have a semiconductor layer on an insulator.

The formation of single-crystal Si semiconductor layers on insulators is widely known as silicon-on-insulator (SOI) technology, and it uses many advantages that cannot be achieved with a bulk Si substrate used to fabricate ordinary Si integrated circuits. Much research has been done on what devices have. In other words, by using SOI technology,
1. Dielectric separation is easy and high integration is possible.
2. Excellent radiation resistance,
3. Floating capacitance is reduced and high speed is possible.
4). Well process can be omitted,
5). Can prevent latch-up,
6). Fully depleted field effect transistors are possible by thinning the film,
Etc. are obtained. These are detailed in, for example, the following documents. Special Issue: “Single-crystal silicon on non-single-crystal insulators”; edited by GWCullen, Journal of Crystal Growth, volume 63, no 3, pp 429-590 (1983).

  Furthermore, in recent years, many reports have been made on SOI as a substrate that realizes high speed and low power consumption of MOSFETs (IEEE SOI conference 1994). Further, when the SOI structure is used, since an insulating layer is provided below the element, the element isolation process can be simplified as compared with the case where the element is formed on the bulk Si wafer, and the device process step is shortened. That is, in combination with high performance, it is expected to reduce the wafer cost and process cost in total compared to MOSFET and IC on bulk Si.

  Among these, fully depleted MOSFETs are expected to increase speed and reduce power consumption by improving driving power. The threshold voltage (Vth) of the MOSFET is generally determined by the impurity concentration of the channel portion. In the case of a fully depleted (FD) MOSFET using SOI, the depletion layer thickness is equal to the SOI film thickness. It will also be affected. Therefore, in order to produce a large scale integrated circuit with a high yield, uniformity of the SOI film thickness has been strongly desired.

  In addition, devices on compound semiconductors have high performance that cannot be obtained with Si, such as high speed and light emission. At present, most of these devices are epitaxially grown on a compound semiconductor substrate such as GaAs and fabricated therein. However, the compound semiconductor substrate has problems such as high cost, low mechanical strength, and difficulty in producing a large area wafer.

  For this reason, attempts have been made to heteroepitaxially grow compound semiconductors on Si wafers that are inexpensive, have high mechanical strength, and can produce large-area wafers.

  Research on the formation of SOI substrates has been active since the 1970s. Initially, a method of heteroepitaxially growing single-crystal Si on an insulating sapphire substrate (SOS: Sapphire on Silicon) or a method of forming an SOI structure by dielectric separation by oxidation of porous Si (FIPOS: Fully Isolation by Porous Oxidized Silicon), oxygen ion implantation was well studied.

  In the FIPOS method, an N-type Si layer is formed into an island shape by proton ion implantation (Imai et al., J. Crystal Growth, vol 63, 547 (1983)) or epitaxial growth and patterning on the surface of a P-type Si single crystal substrate. In this method, only the P-type Si substrate is made porous by anodizing in an HF solution so as to surround the Si island, and then the N-type Si island is dielectrically separated by accelerated oxidation. In this method, the separated Si region is determined before the device process, and there is a problem that the degree of freedom in device design may be limited.

The oxygen ion implantation method is a method called SIMOX reported for the first time by K. Izumi. Oxygen ions are implanted into the Si wafer at about 10 ¹⁷ to 10 ¹⁸ / cm ² and then annealed at a high temperature of about 1320 ° C. in an argon / oxygen atmosphere. As a result, oxygen ions implanted with a depth corresponding to the projected range (Rp) of ion implantation are combined with Si to form an oxidized Si layer. At that time, the Si layer made amorphous by oxygen ion implantation above the oxidized Si layer is also recrystallized into a single crystal Si layer. The number of defects contained in the surface Si layer is conventionally as large as 10 ⁵ / cm ² , but by reducing the amount of oxygen implanted to around 4 × 10 ¹⁷ / cm ^{2, the} defect is reduced to −10 ² / cm ^2. Has succeeded. However, since the range of implantation energy and implantation amount that can maintain the film quality of the Si oxide layer, the crystallinity of the surface Si layer, etc. is narrow, the film thickness of the surface Si layer and buried oxide layer (BOX: Burried Oxide) is It was limited to a specific value. In order to obtain a surface Si layer having a desired film thickness, it is necessary to perform sacrificial oxidation or epitaxial growth. In that case, there is a problem that the uniformity of film thickness deteriorates as a result of the deterioration due to these processes being superimposed on the film thickness distribution.

  In addition, SIMOX has been reported to have a poorly formed Si oxide formation region called a pipe. As one of the causes, foreign substances such as dust at the time of injection are considered. In the portion where the pipe exists, the device characteristics deteriorate due to the leak between the active layer and the support substrate.

  As described above, the SIMOX ion implantation has a larger implantation amount than the ion implantation used in the normal semiconductor process, so that even if a dedicated apparatus is developed, the implantation time is long. Since ion implantation is performed by raster scanning an ion beam having a predetermined current amount or expanding the beam, an increase in implantation time is assumed as the area of the wafer increases. Further, it has been pointed out that problems such as occurrence of slip due to temperature distribution in the wafer become more severe in high-temperature heat treatment of a large area wafer. In SIMOX, a heat treatment at a high temperature not normally used in the Si semiconductor process at 1320 ° C. is essential, and there is a concern that the importance of this problem will be further increased including the development of the apparatus.

  In addition to the conventional SOI formation method as described above, in recent years, an Si structure is formed by bonding a Si single crystal substrate to another thermally oxidized Si single crystal substrate using heat treatment or an adhesive. The method is attracting attention. This method requires a uniform thinning of the active layer for the device. That is, it is necessary to reduce the thickness of a Si single crystal substrate having a thickness of several hundred μm to the order of μm or less. There are three types of thinning methods as follows.

(1). Thinning by polishing (2). Thinning by local plasma etching (3). Thinning by selective etching It is difficult to make a thin film uniformly by polishing (1). In particular, when the thickness of the sub-μm is reduced, the variation becomes several tens of percent, and this uniformity is a big problem. Further, as the wafer diameter increases, the difficulty increases only.

In the method (2), the film thickness is reduced to about 1 to 3 μm by the method (1) in advance and the film thickness distribution is measured at multiple points over the entire surface. Thereafter, based on this film thickness distribution, etching is performed while correcting the film thickness distribution by scanning a plasma using SF ₆ having a diameter of several millimeters, and the film is thinned to a desired film thickness. It has been reported that this method can achieve a film thickness distribution of about ± 10 nm. However, if there is a foreign substance (particle) on the substrate during plasma etching, this foreign substance becomes an etching mask, and thus a protrusion is formed on the substrate.

  In addition, since the surface is rough immediately after etching, touch polishing is necessary after the plasma etching is completed. However, since the amount of polishing is controlled by time management, the final film thickness is controlled by the polishing and the film thickness by polishing. Deterioration of the distribution has been pointed out. Further, in polishing, an abrasive such as colloidal silica directly rubs the surface that becomes the active layer, so there is a concern about formation of a crushed layer by polishing and introduction of processing strain. Further, when the wafer area is increased, the plasma etching time increases in proportion to the increase in the wafer area, and there is a concern that the throughput may be significantly reduced.

The method (3) is a method in which a film structure that can be selectively etched is formed in advance on a substrate to be thinned. For example, a P ⁺ -Si thin layer containing boron at a concentration of 10 ¹⁹ / cm ³ or more and a P-type Si thin layer are stacked on a P-type substrate by a method such as epitaxial growth to form a first substrate. After this is bonded to the second substrate through an insulating layer such as an oxide film, the back surface of the first substrate is thinned in advance by grinding and polishing. Thereafter, the P ⁺ layer is exposed by selective etching of the P type layer, and further, the P type layer is exposed by selective etching of the P ⁺ layer, thereby completing the SOI structure. This method is detailed in Maszara's report (WP Maszara, J. Electrochem. Soc., Vol. 138, 341 (1991)).

Selective etching is effective for uniform thinning,
・ Selectivity is not enough at 10 ² at most.

  -Since the surface property after etching is poor, touch polishing is required after etching. However, as a result, the film thickness decreases, and the film thickness uniformity tends to deteriorate. In particular, in polishing, the polishing amount is managed according to time. However, since the polishing rate varies greatly, it is difficult to control the polishing amount. Therefore, there is a particular problem in forming an ultrathin SOI layer of 100 nm.

The crystallinity of the SOI layer is poor because ion implantation, epitaxial growth on the heavily doped B-doped Si layer or heteroepitaxial growth is used. Moreover, the surface properties of the surfaces to be bonded are also inferior to those of ordinary Si wafers.
(C. Harendt, et.al., J. Elect. Mater. Vol. 20, 267 (1991), H. Baumgart, et.al., Extended Abstract of ECS 1st International Symposium of Wafer Bonding, pp. -733 (1991), CEHunt, Extended Abstract of ECS 1st International Symposium of Wafer Bonding, pp-696 (1991)). The selectivity of the selective etching largely depends on the concentration difference of impurities such as boron and the steepness of the profile in the depth direction. Therefore, if high-temperature bonding annealing for increasing the bonding strength or high-temperature epitaxial growth for improving crystallinity is performed, the depth distribution of the impurity concentration expands and the etching selectivity deteriorates. In other words, it has been difficult to improve both the bonding strength and the crystallinity of the etching selectivity.

  Under such circumstances, the present applicant previously proposed a novel method for manufacturing a semiconductor member in Patent Document 1. The method disclosed in the publication is as follows. That is, a member in which a non-porous single crystal semiconductor region is arranged on a porous single crystal semiconductor region is formed, and the surface of the member made of an insulating material is formed on the surface of the non-porous single crystal semiconductor region. After the bonding, the method for producing a semiconductor member is characterized in that the porous single crystal semiconductor region is removed by etching.

  In addition, Yonehara et al., The inventor of the present invention, reported a bonded SOI that has excellent film thickness uniformity and crystallinity and can be batch-processed (Non-Patent Document 1). Hereinafter, a method for manufacturing the bonded SOI will be described with reference to FIGS.

In this method, the porous layer 902 on the Si substrate 901 is used as a material for performing selective etching. A non-porous single-crystal Si layer 903 is epitaxially grown on the porous layer 902 and then bonded to the second substrate 904 through the oxidized Si layer 905 (FIG. 17A). The first substrate is thinned from the back surface by a method such as grinding to expose porous Si on the entire surface of the substrate (FIG. 17B). The exposed porous Si is removed by etching with a selective etching solution such as KOH or HF + H ₂ O ₂ (FIG. 17C). At this time, since the etching selectivity of porous Si to bulk Si (non-porous single crystal Si) can be sufficiently increased to 100,000 times, the thickness of the non-porous single crystal Si layer previously grown on the porous film is increased. Can be transferred onto the second substrate to form an SOI substrate with little reduction of the. Therefore, the film thickness uniformity of SOI is almost determined during epitaxial growth. Epitaxial growth can be performed using a CVD apparatus normally used in a semiconductor process. According to a report by Sato et al. (SSDM95), the uniformity is realized within 100 nm ± 2%, for example. Also, the crystallinity of the epitaxial Si layer was good, and 3.5 × 10 ² / cm ² was reported.

  In the conventional method, the etching selectivity is based on the difference in impurity concentration and the profile in the depth direction, so the temperature of heat treatment (bonding, epitaxial growth, oxidation, etc.) that expands the concentration distribution is largely limited to approximately 800 ° C. or less. It was. On the other hand, it has been reported that the etching in this method has a heat treatment temperature of about 1180 ° C. because the difference in structure between the porous and the bulk determines the etching speed, so that the heat treatment temperature is limited. For example, heat treatment after bonding is known to increase the bonding strength between wafers and reduce the number and size of voids generated at the bonding interface. Further, in the etching based on such a structural difference, even if there are particles adhering to the porous Si, the film thickness uniformity is not affected.

  However, a semiconductor substrate using bonding always requires two wafers, one of which is mostly discarded and discarded by polishing / etching, etc., and limited earth resources are wasted. It has become. Therefore, in the SOI by bonding, in addition to its controllability and uniformity, it is desired to reduce costs and improve economy.

  That is, there has been a demand for a method for manufacturing an SOI substrate with sufficient quality with good reproducibility, and simultaneously realizing resource saving and cost reduction by reusing a wafer.

  Under these circumstances, the present applicant bonded the two substrates first, then separated the bonded substrates in the porous layer, removed the residual porous material from one of the separated substrates, and removed the substrate. A method for manufacturing a semiconductor substrate to be reused was proposed in Patent Document 2.

  One example of the method disclosed in the publication will be described below with reference to FIGS.

  After the surface layer of the first Si substrate 1001 is made porous to form the porous layer 1002, a single crystal Si layer 1003 is formed thereon, and the single crystal Si layer and the first Si substrate are different from each other. The main surface of the second Si substrate 1004 is bonded via an insulating layer 1005 (FIG. 18A). Thereafter, the wafer bonded with the porous layer is divided (FIG. 18B), and the SOI substrate is formed by selectively removing the porous Si layer exposed on the surface on the second Si substrate side. (FIG. 18C). The first Si substrate 1001 can be reused by removing the remaining porous layer.

  The invention disclosed in Patent Document 2 separates a substrate by utilizing the point that the structure of the porous silicon layer is weaker than that of non-porous silicon, and once used in the manufacturing process of the semiconductor substrate. Since the substrate can be used again in the manufacturing process of the semiconductor substrate, it is very useful for reducing the cost of the semiconductor substrate.

  Separately, Patent Document 3 discloses that a semiconductor layer constituting a photoelectric conversion part of a solar cell is formed on a porous silicon layer, and then the semiconductor layer is separated from the porous layer. Again, it is shown that the substrate on which the porous silicon layer has been formed is reused.

  In the method disclosed in Patent Document 3, the semiconductor layer is bonded to a rigid jig through an adhesive, while the silicon substrate on which the porous silicon layer is formed is bonded to another jig (rigid body). After the alignment, the semiconductor layer is separated from the porous layer by pulling the jigs in opposite directions. In this method, a force that peels the entire surface of the wafer at a stretch is required to separate the rigid bodies. Therefore, if the wafer diameter increases, an external force proportional to the square must be applied.

  In addition, because it is difficult to control the force due to lack of flexibility, it is difficult to divide in the desired area.

  By the way, the solar cell is desired to be able to form an element on a low-cost substrate because of cost requirements. On the other hand, silicon is generally used as a semiconductor constituting the solar cell. Among these, single crystal silicon is most excellent from the viewpoint of efficiency of converting light energy into electromotive force, that is, photoelectric conversion efficiency. However, amorphous silicon is advantageous from the viewpoint of increasing the area and cost. In recent years, the use of polycrystalline silicon has been studied for the purpose of obtaining the cost as low as amorphous silicon and the high energy conversion efficiency as high as single crystal.

  However, the conventional methods proposed for such single crystals and polycrystalline silicon slice the massive crystals into a plate-like substrate, and it was difficult to reduce the thickness to 0.3 mm or less. . Therefore, since the substrate has a thickness more than necessary to sufficiently absorb the light amount, the effective use of the material has not been sufficient. That is, further reduction in thickness is necessary to reduce the price. Recently, a method of forming a silicon sheet by a spin method in which molten silicon droplets are poured into a mold has been proposed. However, the thickness is at least about 0.1 mm to 0.2 mm, which is necessary and sufficient for light absorption as crystalline silicon. Is still not sufficiently thin compared to a large film thickness (20 μm to 50 μm).

  Therefore, there has been proposed an attempt to achieve high energy conversion efficiency and low cost by separating (separating) the thin film epitaxial layer grown on the single crystal silicon substrate from the substrate and using it in a solar cell ( Non-patent document 2).

  However, in this method, it is necessary to insert a SiGe intermediate layer between the single crystal silicon used as a substrate and the growth epitaxial layer to perform heteroepitaxial growth, and then selectively melt this intermediate layer to peel off the growth layer. is there. In general, when heteroepitaxial growth is performed, defects are likely to be induced at the growth interface because of different lattice constants. Moreover, it cannot be said that it is advantageous in terms of process cost in terms of using different materials.

  Further, the method disclosed in Patent Document 4, that is, a solar cell characterized in that a sheet-like crystal is formed on a crystal substrate through a mask material by selective epitaxial growth and lateral growth, and then separated from the substrate. It was shown that a thin crystalline solar cell can be obtained by the battery manufacturing method.

  However, in this method, the opening provided in the mask material is in a line shape, and in order to separate the sheet-like crystal grown by selective epitaxial growth and lateral growth from this line seed, the cleavage of the crystal is used. Therefore, if the shape of the line seed is larger than a certain size, the contact area with the substrate increases, and the sheet-like crystal is damaged during the peeling. In particular, when the area of a solar cell is to be increased, the above method is practically difficult if the line length becomes several mm to several cm or more, no matter how narrow the line width (in practice, around 1 μm). It becomes.

  In view of such points, the present applicant formed a porous silicon layer by anodization on the surface of the silicon wafer and then peeled off. The peeled porous layer was fixed on the metal substrate, and the epitaxial layer was formed on the porous layer. Patent Document 5 discloses a method for manufacturing a solar cell in which a thin film crystal solar cell having good characteristics is obtained using this.

  However, even in this method, since the metal substrate is exposed to a high temperature process, there is a possibility that impurities are mixed in the epitaxial layer, which is not always perfect.

  On the other hand, although different from such a porous layer, a separation technique using a bubble layer is disclosed in Patent Document 6 as a material that performs a substantially similar function. In this publication, a bubble layer is formed in a silicon substrate by ion implantation, crystal rearrangement and bubble aggregation are caused by heat treatment in the bubble layer, and the region on the outermost surface side of the silicon substrate ( In this publication, it is called “thin semiconductor material film”) with the bubble layer as a boundary.

  The thin semiconductor material film here is a region where the implanted ions on the outermost surface of the bulk Si are not present or are present in an extremely small amount.

However, this method needs to be performed at a temperature at which crystal rearrangement and bubble agglomeration occur effectively, and it is not easy to establish ion implantation conditions and optimize heat treatment.
JP-A-5-21338 Japanese Patent Laid-Open No. 7-302889 JP-A-8-213645 U.S. Pat.No. 4,816,420 JP-A-6-45622 JP-A-5-211128 T. Yonehara et.al., Appl. Phys. Lett. Vol. 64, 2108 (1994) Milnes, AGand Feucht, DL, “Peeled Film Technology Solar Cells”, IEEE Photovoltaic Specialist Conference, p.338, 1975

  As described above, the conventional method for manufacturing a semiconductor member has problems such as cost and quality, or manufacturing problems.

  An object of the present invention is to provide a method of manufacturing a semiconductor member having a step of separating a substrate, wherein a part of the substrate can be reused as a raw material of the semiconductor member.

  The method for producing a semiconductor member of the present invention includes a step of attaching a film on a first substrate having a porous semiconductor layer and a non-porous semiconductor layer, and attaching the film to the first substrate. Separating the non-porous semiconductor layer from the first substrate in the porous semiconductor layer by applying a force in the direction of peeling from the film to the film, and the separated non-porous semiconductor layer to the second substrate And a step of bonding to the substrate.

  In the present invention, a substrate obtained by removing the porous layer remaining on the first substrate from which the non-porous semiconductor layer is separated can be used again as a raw material for the first substrate. The reuse of the substrate can be obtained by removing the remaining porous layer in the same manner in the case where the porous layer is separated from the substrate with respect to the substrate configured with the porous semiconductor layer. The substrate can be used again as a raw material for the substrate.

  In the method for producing a semiconductor member of the present invention, the substrate can be separated by utilizing the vulnerability of the porous semiconductor layer. Furthermore, in this invention, a board | substrate can be isolate | separated in a porous layer by sticking a film to a board | substrate and applying the force of the direction which peels a film from a board | substrate to a film. In this case, when the film is gradually peeled off from the edge of the substrate, the peeling force is applied mainly to the tip of the peeling portion of the film, so that the substrate can be easily separated.

  In the conventional method of simply mechanically separating the bonded wafers, the wafer may break, but in the method of the present invention, there is almost no wafer cracking.

  Further, according to the present invention, since the separation is performed simply using the vulnerability of the porous layer, there is no need to optimize in consideration of complicated physical phenomena such as agglomeration of bubbles due to heat treatment. It is possible to divide the substrate in an effective and effective manner.

  In addition, according to the present invention, since the substrate is separated and a part of the layer constituting the substrate can be transferred onto the film, applications applicable to various uses are possible.

  According to the method for manufacturing a semiconductor member of the present invention, the material can be effectively used by regenerating and repeatedly using the substrate. As a result, an inexpensive semiconductor member such as an SOI substrate or a solar cell can be provided. it can.

  Hereinafter, preferred embodiments of the present invention will be described, but the present invention is not limited to these embodiments, and any object can be used as long as the object of the present invention can be achieved.

[Porous semiconductor layer]
As the porous semiconductor layer, one using silicon (Si) is preferably used.

  Porous Si was discovered by Uhlir et al. In 1956 in the research process of electrolytic polishing of semiconductors (A. Uhlir, Bell Syst. Tech. J., vol. 35, 333 (1956)). Porous Si can be formed by anodizing a Si substrate in an HF solution. Unagami et al. Studied the dissolution reaction of Si in anodization, and reported that holes were necessary for the anodic reaction of Si in HF solution, and the reaction was as follows (T. Unagami, J. Electrochem. Soc., Vol. 127, 476 (1980)).

Si + 2HF + (2-n) e ⁺ → SiF ₂ + 2H ⁺ + ne ⁻
SiF ₂ + 2HF → SiF ₄ + H ₂
SiF ₄ + 2HF → H ₂ SiF ₆
Or
Si + 4HF + (4-λ) e ⁺ → SiF ₄ + 4H ⁺ + λe ⁻
SiF ₄ + 2HF → H ₂ SiF ₆
Here, e ⁺ and e ⁻ represent holes and electrons, respectively. Further, n and λ are the number of holes necessary for dissolving Si1 atoms, respectively, and porous Si is formed when the condition of n> 2 or λ> 4 is satisfied.

  From the above, P-type Si in which holes are present is made porous and N-type Si is not made porous. However, N-type Si can also be made porous by changing the conditions.

In the present invention, porous Si having single crystallinity can be formed by anodizing a single crystal Si substrate, for example, in an HF solution. The porous layer has a sponge-like structure in which pores having a diameter of about 10 ⁻¹ to 10 nm are arranged at intervals of about 10 ⁻¹ to 10 nm. The density is 2.1 to 0.6 g / cm ³ by changing the HF solution concentration to 50 to 20% or changing the current density compared to the density of single crystal Si of 2.33 g / cm ³ . Can be changed to range. That is, Porosity can be varied. In this way, the density of porous Si can be reduced to less than half that of single crystal Si, but single crystallinity is maintained, and a single crystal Si layer can be epitaxially grown on top of the porous layer. It is.

  In addition, since the porous layer has a large amount of voids formed therein, the density is reduced to less than half. As a result, since the surface area increases dramatically compared to the volume, the chemical etching rate is significantly increased as compared with the etching rate of a normal single crystal layer.

  The mechanical strength of porous Si varies with porosity, but is considered weaker than bulk Si. For example, if the porosity is 50%, the mechanical strength can be considered as half the bulk. That is, when compression, tension, or shear force is applied to the bonded wafer, the porous Si layer is first destroyed. Moreover, if the porosity is increased, the porous layer can be destroyed with a weaker force.

  In the present invention, the current density at the time of anodizing the porous layer can be changed to have a multilayer structure with different porosities. Also, a porous layer thicker than the thickness of the high concentration impurity layer can be formed by forming a high concentration impurity layer on one surface of the Si substrate and anodizing from this surface.

When helium or hydrogen is ion-implanted into bulk Si and heat treatment is applied, micro-cavity with a diameter of several nanometers to several tens of nanometers is formed at a density of 10 ^16-17 / cm ^{3 in the} implanted region. (Eg, A. Van Veen, CCGriffioen, and JHEvans, Mat. Res. Soc. Symp. Proc. 107 (1988, Material Res. Soc. Pittsburgh, Pennsylvania) p. 449.). Recently, the use of these microcavities as gettering sites for metal impurities has been studied.

  V.Raineri and S.U.Campisano formed a cavity group formed by injecting helium ions into bulk Si and heat-treating, and then forming a groove in the substrate to expose the side surface of the cavity group and perform an oxidation treatment. As a result, the cavities were selectively oxidized to form a buried oxide Si layer. That is, it has been reported that an SOI structure can be formed (V. Raineri, and S. U. Campisano, Appl. Phys. Lett. 66 (1995) p. 3654). However, in their method, the thickness of the surface Si layer and the buried Si oxide layer is limited to both the formation of the cavity group and the relaxation of the stress introduced by the volume expansion during the oxidation. Therefore, it is necessary to form a groove, and an SOI structure cannot be formed on the entire surface of the substrate. The porous semiconductor layer of the present invention includes a layer having such a micro-cavity or micro-bubble.

[the film]
As the film used in the present invention, a polyimide-based resinous adhesive film, a resinous conductive film, a metal conductive film, a film whose adhesive force changes by light, electron beam, heat, etc., or an aluminum foil containing Although glass cloth film etc. can be mentioned, it is not specifically limited to these.

  Specific examples include Tefzel film manufactured by Dupont, aluminum foil glass cloth tape (No. 363) manufactured by Scotch, heat-resistant aluminum foil tape (No. 433), and release tape manufactured by Nitto Denko Corporation ( No. 3200A, No. 31RH, BT-315) and the like.

  Further, when the film is attached to the substrate, for example, when the adhesive force is insufficient, the film can be attached using an adhesive. Adhesives such as epoxy-based adhesives, waxes, SOG (spin on glass), etc. can be used as the adhesive, or the resin component of the conductive paste can be heated and blown away to replace the adhesive. It can also be made.

  The thickness of the film of the present invention is appropriately selected according to the material and characteristics of the film to be used, but is preferably 5 μm to 3 cm, more preferably 10 μm to 1 cm.

[Non-porous semiconductor layer]
In the present invention, as the non-porous semiconductor layer, preferably, in addition to single crystal Si, polycrystalline Si, and amorphous Si, GaAs, InP, GaAsP, GaAlAs, InAs, AlGaSb, InGaAs, ZnS, CdSe, CdTe, A compound semiconductor such as SiGe can be used. The non-porous semiconductor layer may be one in which a semiconductor element such as an FET (Field Effect Transistor) is already formed.

[First substrate]
The first base is formed by forming the above-mentioned non-porous semiconductor layer on the porous silicon layer formed in the silicon substrate, or partially in the silicon substrate provided with the non-porous semiconductor layer. It can be configured by forming a porous silicon layer.

  Further, the first substrate is a substrate having a non-porous semiconductor layer formed on a silicon substrate in which an ion implantation layer for generating micro-bubbles is formed. A substrate in which an insulating film such as a nitride film or an oxide film is formed on a semiconductor layer, or a substrate in which an epitaxial semiconductor layer and an insulating layer are formed on a silicon substrate and then ion-implanted into the silicon substrate to form an ion-implanted layer; Furthermore, the thing etc. which formed the ion implantation layer in the non-porous semiconductor layer formed on the silicon substrate are included.

In the present invention, the epitaxial growth method used for forming the silicon layer on the porous layer includes a thermal CVD method, an LPCVD method, a sputtering method, a plasma CVD method, a photo CVD method, a liquid phase growth method and the like. For example, as a source gas used in a vapor phase growth method such as a thermal CVD method, an LPCVD method, a plasma CVD method, or a photo CVD method, SiH ₂ Cl ₂ , SiCl ₄ , SiHCl ₃ , SiH ₄ , Si ₂ H ₆ , and silanes such as SiH ₂ F ₂ and Si ₂ F ₆ and halogenated silanes are representative examples.

Also, hydrogen (H ₂ ) is added as a carrier gas or for the purpose of obtaining a reducing atmosphere that promotes crystal growth in addition to the source gas. The ratio of the amount of the source gas and hydrogen is appropriately determined according to the formation method, the type of the source gas, and the formation conditions, but is preferably 1:10 or more and 1: 1000 or less (introduction flow ratio). Preferably it is 1:20 or more and 1: 800 or less.

When liquid phase growth is used, epitaxial growth is performed by dissolving silicon in a solvent such as Ga, In, Sb, Bi, or Sn in a H ₂ or N ₂ atmosphere and gradually cooling the solvent or creating a temperature difference in the solvent. I do.

When a compound semiconductor layer is formed on the porous layer, MOCVD method, MBE method, liquid phase growth method or the like is used. The raw materials used in these crystal growth methods are appropriately determined depending on the type of compound semiconductor to be formed and each growth method. For example, when forming GaAs, the MOCVD method uses Ga (CH ₃ ) ₃ , AsH _3. Al (CH ₃ ) ₃ or the like is used, and in the liquid phase growth, the solvent is Ga, and As or As and Al are dissolved therein to perform the growth.

  The temperature and pressure in the epitaxial growth method used in the present invention vary depending on the forming method and the type of raw material (gas) used, but the temperature is about 800 when silicon is grown by a normal thermal CVD method, for example. It is desirable that the temperature is not lower than 1 ° C and not higher than 1250 ° C, and more preferably controlled at 850 ° C or higher and 1200 ° C or lower. In the case of the liquid phase growth method, depending on the type of the solvent, when silicon is grown using Sn or In as a solvent, it is desirable that the temperature is controlled at 600 ° C. or higher and 1050 ° C. or lower. When growing GaAs using Ga as a solvent, it is desirable to control the temperature to 650 ° C. or higher and 850 ° C. or lower. When GaAs is grown by the MOCVD method, it is desirable to control the temperature to 650 ° C. or higher and 900 ° C. or lower. In a low-temperature process such as a plasma CVD method, the temperature is generally 200 ° C. or higher and 600 ° C. or lower, and more preferably 200 ° C. or higher and 500 ° C. or lower.

Similarly, except for the MBE method, the pressure is generally about 10 ⁻² Torr to 760 Torr, and more preferably 10 ⁻¹ Torr to 760 Torr. When the MBE method is used, the exhaust pressure is suitably 10 ⁻⁵ Torr or less, more preferably 10 ⁻⁶ Torr or less.

[Second substrate]
Examples of the second substrate to which the non-porous semiconductor layer is transferred include a semiconductor substrate such as a single crystal silicon substrate, and an insulating film such as an oxide film (including a thermal oxide film) or a nitride film on the surface of the semiconductor substrate. , A light-transmitting substrate such as a quartz substrate or a glass substrate, a sheet-like resin or metal substrate, an insulating substrate such as alumina, and the like. Such a 2nd base | substrate is suitably selected according to the use of a semiconductor member.

[Lamination of non-porous semiconductor layer and second substrate]
In the present invention, the non-porous semiconductor layer on the above-mentioned film is bonded to the above-mentioned second substrate (so that the non-porous semiconductor layer is located inside) to obtain a multilayer structure. In the present invention, the multilayer structure in which the non-porous semiconductor layer is located on the inside is, of course, a structure in which the non-porous semiconductor layer on the film separated from the first substrate is directly bonded to the second substrate. This also includes a structure in which an insulating film such as an oxide film or a nitride film formed on the surface of the non-porous semiconductor layer, or a film other than this is bonded to the second substrate. That is, a structure in which the nonporous semiconductor layer is positioned inside the multilayer structure compared to the film or the support member is referred to as a multilayer structure in which the nonporous semiconductor layer is positioned inside.

  The specific bonding can be performed by keeping the bonding surface of the non-porous semiconductor layer and the second substrate flat, and bringing them into close contact, for example, at room temperature. In addition, in order to increase the bonding strength, anodic bonding, pressurization, heat treatment, and the like can be performed.

[Removal of porous layer]
After the multilayer structure obtained by bonding the first substrate and the second substrate is separated in the porous Si layer, the porous Si layer remaining on the separated substrate is the mechanical strength of the porous Si layer. Can be selectively removed by taking advantage of its low surface area and its very large surface area. As a selective removal method, a mechanical method using grinding or polishing, a chemical etching method using an etching solution, or an ion etching method (for example, reactive ion etching) can be employed.

  When the porous Si layer is selectively etched using an etching solution, the etching solution is not limited to a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide solution, but is a mixture of hydrofluoric acid and hydrofluoric acid with alcohol added thereto. Liquid, a mixture of alcohol and hydrogen peroxide in hydrofluoric acid, a mixture of buffered hydrofluoric acid, alcohol in buffered hydrofluoric acid, a mixture of hydrogen peroxide in buffered hydrofluoric acid, buffer A mixed solution obtained by adding alcohol and hydrogen peroxide to dehydrofluoric acid, or a mixed solution of hydrofluoric acid, nitric acid, and acetic acid can be employed. After selectively removing the porous layer, the flatness of the nonporous semiconductor layer can be increased by heat-treating the semiconductor member obtained by transferring the nonporous semiconductor layer in an atmosphere containing hydrogen.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.

[Embodiment 1]
The method for producing a semiconductor member of the present embodiment includes a step of forming a porous layer on at least a main surface side of a substrate, a step of attaching a film on the surface of the porous layer, and a substrate side and a film side in the porous layer. Separating. This will be described below with reference to FIG.

  First, a first Si single crystal substrate 101 is prepared, and a porous Si layer 102 is formed on the main surface layer (FIG. 1A). A flexible adhesive film 103 or a flexible film is attached to the porous Si surface via an adhesive (FIG. 1B). Of course, it is also possible to use a conductive paste. This also applies to the embodiments described later. Thereafter, the flexible film is peeled off from the first Si single crystal substrate 101 (FIG. 1C) and separated into the substrate side and the film side with the porous Si layer as a boundary. Thus, the porous Si thin film can be separated from the substrate 101 (FIG. 1D). The porous Si layer 102 on the film 103 thus obtained can be applied to a light emitting element, a gas adsorption sensor, and the like.

  The Si single crystal substrate 101 can be reused as a Si single crystal substrate by removing residual porous Si. If the surface flatness is unacceptably rough, it can be reused as a Si single crystal substrate after surface flattening.

[Embodiment 2]
Here, a step of forming a porous layer on at least the main surface side of the first substrate, a step of forming a non-porous layer on the porous layer, a step of attaching a film on the surface of the non-porous layer, the porous The porous layer has a step of separating the non-porous layer from the first substrate to the film side. This will be described below with reference to FIG.

  First, a first Si single crystal substrate 201 is prepared, and a porous Si layer 202 is formed on the main surface layer (FIG. 2A). A non-porous layer 203 is formed on the porous Si surface (FIG. 2B). A flexible adhesive film 204 or a flexible film is attached to the surface of the non-porous layer via an adhesive (FIG. 2 (c)). Thereafter, when a force is applied in the direction in which the flexible film is peeled off from the first Si single crystal substrate 201 (FIG. 2D), the non-porous layer and the porous layer are formed from the first substrate side with the porous Si layer as a boundary. The Si layer can be separated on the film side. Thus, the porous Si / non-porous layer is separated from the substrate 201 (FIG. 2 (e)). The separated porous Si / non-porous layer can be applied to a light emitting device, a sensor and the like.

  The first Si single crystal substrate 201 can be reused as the first Si single crystal substrate by removing residual porous Si. If the surface flatness is unacceptably rough, it can be reused as the first Si single crystal substrate after surface flattening.

[Embodiment 3]
Here, a step of forming a porous layer in the state in which the surface is kept non-porous on at least the main surface side of the first substrate, a step of attaching a film on the surface of the non-porous first substrate, Separating the first substrate side and the film side with the porous layer as a boundary. This will be described below with reference to FIG.

First, a first Si single crystal substrate 301 is prepared, and a porous ion implantation layer 302 is formed therein by ion implantation from the main surface layer side (FIG. 3A). As the first substrate, a substrate on which a non-porous layer is formed in advance may be used. That is, it is possible to deposit a non-porous material on the substrate in advance. The non-porous layer may be further formed after ion implantation. Prior to ion implantation, it is preferable to form a protective film such as SiO _{2 on the} main surface layer from the viewpoint of preventing surface roughness. A flexible adhesive film 304 or a flexible film is attached to the main surface of the first Si substrate via an adhesive (FIG. 3B). Thereafter, when the flexible film is peeled off from the first Si single crystal substrate 301 (FIG. 3C), it can be separated into the first substrate side and the film side with the porous ion implantation layer as a boundary. Thus, the surface non-porous layer 303 can be separated from the substrate 301 (FIG. 3D).

  The first Si single crystal substrate 301 can be reused as the first Si single crystal substrate by removing residual porous Si. If the surface flatness is unacceptably rough, it can be reused as the first Si single crystal substrate after surface flattening.

[Embodiment 4]
Here, the step of attaching a film on a first substrate comprising a porous semiconductor layer and a non-porous semiconductor layer, the force in the direction of peeling the film from the first substrate, A mode having a step of separating the non-porous semiconductor layer from the first substrate in the porous layer by adding to the film, and a step of bonding the separated non-porous semiconductor layer to the second substrate Will be described with reference to FIGS.

  First, a first substrate (FIG. 4C) including a porous semiconductor layer 2002 and a non-porous semiconductor layer 2003 is prepared. As the first substrate, for example, a single crystal silicon substrate 2000 (FIG. 4A) is made porous to form a porous layer 2002 (FIG. 4B), and then a non-porous structure is formed on the porous layer 2002. A semiconductor layer 2003 (for example, epitaxial Si) can be formed (FIG. 4C), or an ion implantation technique for generating microbubbles can be used as described in the section on the first substrate. It can also be configured.

Next, a film 2005 is attached to the side of the first substrate on which the non-porous semiconductor layer 2003 is formed (FIG. 4D). Here, the surface to which the film 2005 is attached may be a non-porous semiconductor layer 2003, or an insulating layer such as a SiO ₂ layer (for example, a thermal oxide film) or a SiN layer formed on the surface of the non-porous semiconductor layer 2003. It may be the surface. The layers formed on the non-porous semiconductor layer 2003 can be appropriately selected and formed according to the characteristics required for the semiconductor member to be obtained.

  Next, the first substrate is separated by applying a force in a direction in which the film 2005 is peeled off to the film 2005 (FIG. 4E). The substrate including the separated single crystal silicon substrate 2000 is removed as the single crystal silicon substrate 2000 by removing the porous semiconductor layer (Si) 2002 (FIG. 4 (Z1)), and the next It can be used as a raw material for manufacturing the semiconductor member (FIG. 4 (Z2) → (A)).

  As shown in FIG. 5, the method of processing the substrate on the side of the film 2005 including the other separated non-porous semiconductor layer 2003 is roughly divided into three types. In the embodiment shown in W1 to W4, the porous semiconductor layer 2002 remaining on the opposite side of the film 2005 is removed, the non-porous semiconductor layer 2003 is bonded to the second substrate 2200, and then the film 2005 is removed. It is. In the embodiments shown in X1 to X6 and Y1 to Y5, the surface of a member (for example, a nonporous semiconductor layer 2003, a nonporous semiconductor layer 2002, etc.) on the opposite surface of the film 2005 is used as a support member (film, sheet, or Substrate etc.) After bonding to 2100, the film 2005 is removed, and the non-porous semiconductor layer 2003 exposed by removing the film 2005 is bonded to the second substrate 2200, and then the support member 2100 is removed. It is. The difference between the mode shown in X1 to X6 and the mode shown in Y1 to Y5 is that the porous semiconductor layer 2002 is removed before bonding to the support member 2100 (FIG. 5 (X2)) or bonded. It will be removed later (FIG. 5 (Y5)). If the example shown here is used, semiconductor members, such as an SOI substrate, a sensor, a solar cell, and a liquid crystal image display device, can be manufactured.

[Embodiment 5]
Here, a step of forming a porous layer on at least the main surface side of the first substrate, a step of forming a non-porous layer on the porous layer, a step of attaching a film on the surface of the non-porous layer, the porous A step of separating the first substrate side and the film side from the porous layer, a step of transferring the multilayer structure on the film side onto another support member (or film, etc.), and the non-porous property of the transferred multilayer structure A mode having a step of bonding the surface side of the porous layer to the second substrate and a step of removing the porous layer of the multilayer structure will be described.

  Here, a step of transferring the multilayer structure on the film side onto another support member (or film or the like), and a step of bonding the surface side of the non-porous layer of the transferred multilayer structure to the second substrate Is attached to a support member having an adhesive strength (or adhesive strength) higher than the adhesive strength (or adhesive strength) of the film, peeled off the film, and then the surface side of the non-porous layer of the multilayer structure where the film is peeled off This can be done by attaching to the second substrate. Thereafter, another support member (or another film or the like) is peeled off (the other film may be removed by etching).

  In addition, when a single layer or multilayer structure is peeled from the first substrate using a film whose adhesive strength is weakened by irradiating with ultraviolet rays, the initial high adhesive strength is used, and this is applied to another stage or When transferred to the film, the film may be peeled off from the structure by irradiating with ultraviolet rays to weaken the adhesive force.

  In addition, even if it does not use another support member etc., a film is melt | dissolved in a liquid by an etching, or the film which becomes weakly adhesive by the said ultraviolet-ray is used, and adhesive force is dropped by ultraviolet irradiation and it peels in a liquid. Thereafter, the remaining multilayer structure with a mesh, net, etc. is scooped and placed on the second substrate, whereby the surface side of the non-porous layer of the multilayer structure can be bonded to the second substrate.

  The steps described above can be similarly applied to other embodiments.

  This will be described below with reference to FIG.

A first Si single crystal substrate 401 is prepared, and a porous Si layer 402 is formed on the main surface layer (FIG. 6A). At least one non-porous layer 403 is formed on the porous Si surface (FIG. 6B). The non-porous 403 is arbitrarily selected from single crystal Si, polycrystal Si, amorphous Si, or a metal film, a compound semiconductor thin film, a superconducting thin film, and the like. Alternatively, an element structure such as a MOSFET may be formed. Furthermore, it may also mean that the bonding interface can be separated from the active layer if SiO ₂ 404 is formed on the outermost surface layer. A flexible adhesive film 405 or a flexible film is attached to the surface of the non-porous layer via an adhesive (FIG. 6C). Thereafter, when the flexible film 405 is peeled off from the first Si single crystal substrate 401 (FIG. 6D), it can be separated into the first substrate side and the film side with the porous Si layer as a boundary. Thus, the porous Si layer 402 / non-porous layer 403 / SiO ₂ 404 can be separated from the substrate 401 (FIG. 6E).

After peeling the porous Si 402 / non-porous layer 403 / SiO ₂ 404 from the film 405, the second substrate 406 and the surface of the SiO ₂ 404 are brought into close contact with each other as shown in FIG. Thereafter, the bonding may be strengthened by anodic bonding, pressurization, or heat treatment as necessary, or a combination thereof.

  In the case where single crystal Si is deposited, it is preferable that the surface of the single crystal Si be bonded together after forming the oxidized Si by a method such as thermal oxidation. The second substrate can be selected from a Si substrate, a Si substrate formed with an Si oxide film, a light-transmitting substrate such as quartz, and a sapphire substrate, but is not limited thereto. As long as the surface used for bonding is sufficiently flat. FIG. 6 (f) shows a state of bonding through the insulating layer 404, but if the non-porous thin film 403 is not Si, or if the second substrate is not Si, the insulating layer 404 is not required. Good. In bonding, it is also possible to sandwich three insulating thin plates and stack them together.

  Further, the porous Si layer 402 is selectively removed. When the non-porous thin film is single crystal Si, hydrofluoric acid that is a normal Si etching solution or porous Si selective etching solution, or at least one of alcohol and hydrogen peroxide water is added to hydrofluoric acid. Using at least one of a mixed solution or a mixed solution obtained by adding at least one of alcohol and hydrogen peroxide to buffered hydrofluoric acid or buffered hydrofluoric acid, only the porous Si layer 402 is subjected to electroless wet chemistry. The film previously formed on the porous substrate of the first substrate is left on the second substrate by etching. As described above, it is possible to selectively etch only porous Si even with a normal Si etchant due to the enormous surface area of porous Si. Alternatively, the porous Si layer 402 is removed by selective polishing using the non-porous thin film layer 403 as a polishing stopper.

  In the case where the compound semiconductor layer is formed on the porous layer, only the porous Si layer 402 is chemically etched on the second substrate 406 using an etching solution having a high Si etching rate with respect to the compound semiconductor. The thinned single crystal compound semiconductor layer 403 is formed to remain. Alternatively, the porous Si layer 402 is removed by selective polishing using the single crystal compound semiconductor layer 403 as a polishing stopper.

  FIG. 6G shows a semiconductor substrate obtained by the present invention. A non-porous thin film, for example, a single crystal Si thin film 403, is flattened and uniformly thinned on the second substrate 406 to form a large area over the entire wafer. If an insulating substrate is used as the second substrate 406, the semiconductor substrate obtained in this manner can be preferably used from the viewpoint of manufacturing an electronic element that is insulated and separated.

  The first Si single crystal substrate 401 can be reused as a first Si single crystal substrate, a second substrate, or the like after removing residual porous Si. If the surface flatness is unacceptably rough, it can be reused as the first Si single crystal substrate or the second substrate after the surface flattening. In addition, each process demonstrated here is employable also in the other embodiment of this invention.

[Embodiment 6]
Here, a step of forming a porous layer inside with the surface holding at least a main surface side of the first substrate, a step of attaching a film on the surface of the non-porous layer, the porous Separating the first substrate side and the film side through the layers, transferring the multilayer structure on the film side onto another support member, and changing the surface side of the single crystal semiconductor of the transferred multilayer structure to the first side A mode including the step of bonding to the substrate 2 and the step of removing the porous layer of the multilayer structure will be described with reference to FIG.

First, a first Si single crystal substrate 501 is prepared, and at least one element of rare gas, hydrogen, and nitrogen is ion-implanted from the main surface layer side, and a porous ion-implanted layer 502 is formed inside. Is formed (FIG. 7A). The surface is in a state of holding the non-porous 503. Prior to that, it is preferable to form a protective film such as SiO ₂ 504 on the main surface layer from the viewpoint of preventing surface roughness. Furthermore, it may mean that the bonding interface can be separated from the active layer if SiO ₂ 504 is formed on the outermost surface layer.

A flexible adhesive film 505 or a flexible film is attached to the surface of the non-porous layer via an adhesive (FIG. 7B). Thereafter, when the flexible film 505 is peeled off from the first Si single crystal substrate 501 (FIG. 7C), it can be separated into the first substrate side and the film side through the porous ion implantation layer 502. Thus, the porous ion implantation layer 502 / non-porous layer 503 / SiO ₂ 504 can be separated from the substrate 501 (FIG. 7D).

After peeling the porous ion implantation layer 502 / non-porous layer 503 / SiO ₂ 504 from the film 505, the second substrate 506 and the surface of the SiO ₂ 504 are pasted as shown in FIG. Match.

  Further, the porous ion implantation layer 502 is selectively removed in the same manner as described above.

  FIG. 7F shows the semiconductor substrate obtained in this example.

  The first Si single crystal substrate 501 can be reused as a first Si single crystal substrate, a second substrate, or the like by removing the residual porous ion implantation layer.

[Embodiment 7]
Here, on the at least main surface side of the first substrate, a step of forming a porous layer therein while maintaining a non-porous surface, and a non-porous layer is formed on the surface of the non-porous substrate A step of attaching a film on the surface of the non-porous layer, a step of separating the first substrate side and the film side with the porous layer as a boundary, and transferring the multilayer structure on the film side onto another support member A mode having a step, a step of bonding the surface side of the insulating layer of the transferred multilayer structure to a second substrate, and a step of removing the porous layer of the multilayer structure will be described with reference to FIG.

First, a first Si single crystal substrate 601 is prepared, and at least one element of rare gas, hydrogen, and nitrogen is ion-implanted from the main surface layer side, and a porous ion-implanted layer 602 is provided therein. Is formed (FIG. 8A). The surface is in a state of holding the non-porous 603. Prior to that, a protective film such as SiO ₂ is preferably formed on the main surface layer from the viewpoint of preventing surface roughness.

Further, at least one non-porous layer 604 is formed on the non-porous layer on the surface of the first Si single crystal substrate 601 (FIG. 8B). A flexible adhesive film 606 or a flexible film is attached to the surface of the non-porous layer via an adhesive (FIG. 8C). Thereafter, when the flexible film 606 is peeled off from the first Si single crystal substrate 601 (FIG. 8D), it can be separated into the first substrate side and the film side with the porous ion implantation layer 602 as a boundary. In this way, the porous ion implantation layer 602 / non-porous layer 603 / non-porous thin film 604 / SiO ₂ 605 can be separated from the substrate 601 (FIG. 8E).

After peeling the porous ion implantation layer 602 / non-porous layer 603 / non-porous thin film 604 / SiO ₂ 605 from the film 606, as shown in FIG. 8 (f), the second substrate 607 and the SiO 2 ₂ Bond the surface of 605 together.

  Next, the porous ion implantation layer 602 is selectively removed.

  FIG. 8G shows the semiconductor substrate obtained in this example. A non-porous thin film, for example, a single crystal Si thin film 603/604, is flattened and uniformly thinned on the second substrate 607, and is formed in a large area over the entire wafer. If an insulating substrate is used as the second substrate 607, the semiconductor substrate obtained in this manner can be preferably used from the viewpoint of manufacturing an electronic element that is insulated and separated.

  The first Si single crystal substrate 601 can be reused as the first Si single crystal substrate, the second substrate, or the like by removing the residual porous ion implantation layer.

[Embodiment 8]
Here, a step of forming a non-porous layer on at least the main surface of the first substrate, a step of forming a porous layer inside the surface while maintaining the non-porous state, and a film on the surface of the non-porous layer A step of separating the first substrate side and the film side through the porous layer, a step of transferring the multilayer structure on the film side onto another support base, and A mode including the step of bonding the surface side of the insulating layer to the second substrate and the step of removing the porous layer of the multilayer structure will be described with reference to FIG.

First, a first Si single crystal substrate 701 is prepared, and at least one non-porous layer 702 is formed on the main surface (FIG. 9A). If SiO ₂ 703 is formed on the outermost surface layer, it may mean that the bonding interface can be separated from the active layer. At least one element of rare gas, hydrogen, and nitrogen is ion-implanted from the main surface of the first substrate to form a porous ion-implanted layer 704 inside (FIG. 9B). The surface is in a state of holding non-porous 702. Prior to that, a protective film such as SiO ₂ is preferably formed on the main surface layer from the viewpoint of preventing surface roughness.

  The porous ion implantation layer 704 is preferably near the interface between the first Si single crystal substrate 701 and the nonporous layer 702 or inside the nonporous layer 702.

A flexible adhesive film 705 or a flexible film is attached to the surface of the non-porous layer via an adhesive (FIG. 9C). Thereafter, when the flexible film 705 is peeled off from the first Si single crystal substrate 701 (FIG. 9D), it can be separated into the first substrate side and the film side with the porous ion implantation layer 704 as a boundary. In this way, the porous ion implantation layer 704 / non-porous layer 702 / SiO ₂ 703 can be separated from the substrate 701 (FIG. 9E).

After removing the porous ion implantation layer 704 / non-porous layer 702 / SiO ₂ 703 from the film 705, the second substrate 706 and the surface of the SiO ₂ 703 are removed as shown in FIG. to paste together.

  Next, the porous ion implantation layer 704 is selectively removed.

  FIG. 9G shows the semiconductor substrate obtained in this example. A non-porous thin film, for example, a single crystal Si thin film 702, is flattened and uniformly thinned over the second substrate 706 to form a large area over the entire wafer. If an insulating substrate is used as the second substrate 706, the semiconductor substrate obtained in this manner can be preferably used from the viewpoint of manufacturing an electronic element that is insulated and separated.

  The first Si single crystal substrate 701 can be reused as the first Si single crystal substrate, the second substrate, or the like by removing the residual porous ion implantation layer.

[Embodiment 9]
As shown in FIG. 10, two semiconductor substrates can be fabricated simultaneously by performing each step on both sides of the Si single crystal substrate in the steps shown in the above-described embodiments. FIG. 10 shows the double-sided specification of the fifth embodiment as an example of the double-sided specification, but it can be applied to any embodiment. In FIG. 10, 801 is a first Si single crystal substrate, 802 and 803 are porous Si layers, 804 and 805 are non-porous layers, 806 and 807 are SiO ₂ , 808 and 809 are flexible films, 810 and 811 Is a second substrate (support substrate).

  The first Si single crystal substrate 801 can be reused as a first Si single crystal substrate, a second substrate, or the like after removing residual porous Si. If the surface flatness is unacceptably rough, it can be reused as the first Si single crystal substrate or the second substrate after the surface flattening.

  The materials and thicknesses of the support substrates 810 and 811 may not be the same. The non-porous thin films 804 and 805 need not have the same material and film thickness on both sides.

[Embodiment 10]
The example which applies this invention to the manufacturing method of a solar cell is demonstrated.

The form example described here is
(B) a step of anodizing at least one principal surface side of the substrate to form a porous layer on the surface of the substrate; (b) a step of forming a semiconductor layer on the porous layer; A step of attaching a film to the surface; and (d) a step of separating the semiconductor layer into the film side with the porous layer as a boundary, and transferring the semiconductor layer to the film. The film used for manufacturing the solar cell is preferably a low heat resistant film, and preferably has a heat resistant temperature of 400 ° C. or lower.

As shown in FIG. 12A, first, B (boron) is introduced into the surface layer of the silicon single crystal substrate 1201 by thermal diffusion. The single crystal substrate 1201 having the surface layer of p ⁺ is anodized in an HF solution, for example, after a certain time at a low current level first elapses, and then suddenly raised to a high current level to form for a short time. It becomes porous (FIG. 12B). This thermal diffusion of B is not an essential process, and anodization is possible without using this method.

  In addition, in the anodization, the separation current is separated from the porous layer after epitaxial growth by changing the formation current level from low to high in the middle, for example, by changing the density of the porous layer in advance. Can be controlled to be easy to be.

Next, a silicon layer 1203 having a necessary and sufficient thickness as an active layer of the solar cell is formed on the porous surface layer 1202 by a thermal CVD method (FIG. 12C). At this time, the active layer can be controlled to be p ⁻ type (or n ⁻ type) by mixing a small amount of dopant when forming the silicon layer 1203.

A p ⁺ layer (or n ⁺ layer) 1204 is deposited on the active layer 1203 by plasma CVD, or is formed by increasing the amount of dopant at the end of the formation of the active layer 1203 (FIG. 12 (FIG. 12)). d)).

  A polymer film substrate 1205 on which copper paste is printed in advance as a back electrode 1209 is closely attached to the side on which the active layer 1203 is formed on the silicon single crystal substrate 1201, and is put in an oven (not shown) and heated. Then, the polymer film substrate 1205 and the silicon single crystal substrate 1201 are fixed (FIG. 12E).

  Next, force is applied between the polymer film substrate 1205 and the silicon single crystal substrate 1201 in a direction in which they are separated from each other. That is, using the flexibility of the polymer film, the two are gradually peeled off from the edge of the silicon single crystal substrate 1201 and separated at the porous layer 1202 (FIG. 12F).

  Next, the porous layer 1202a remaining on the active layer 1203 peeled from the silicon single crystal substrate is selectively removed.

An n ⁺ (p ⁺ ) layer 1206 is formed on the surface of the active layer 1203 from which the porous layer has been removed by a plasma CVD method or the like (FIG. 12 (g)), and a transparent conductive film that also serves as a surface antireflection layer on the n ⁺ (p ⁺ ) layer A film (ITO) 1207 and a grid-shaped collecting electrode 1208 are vacuum-deposited to form a solar cell (FIG. 12 (h)). FIG. 11 shows the solar cell thus obtained.

  The silicon single crystal substrate 1201 is removed by removing the porous layer 1202b remaining on the surface in the same manner as described above, and if the surface flatness is unacceptably rough, the surface flattening may be performed as necessary. After being performed (FIG. 12 (i)), it is subjected to the process of FIG. 12 (a) again.

[Embodiment 11]
Here, a mode for obtaining a polycrystalline solar cell will be described. A polycrystalline silicon solar cell can be manufactured by using a polycrystalline silicon substrate as the silicon substrate 1201 of the tenth embodiment and employing the same method as in the tenth embodiment so as to form the polycrystalline silicon layer 1203. .

[Embodiment 12]
An embodiment for producing a compound semiconductor solar battery will be described.

As shown in FIG. 13A, first, B (boron) is introduced into the surface layer of the silicon single crystal substrate 1301 by thermal diffusion. The single crystal substrate whose surface layer is ^{p.sup. +} Is made porous by anodizing in an HF solution, for example, by first elevating to a high current level after a certain time at a low current level and then gradually forming it. (FIG. 13B).

Next, for example, an n ⁺ layer (or p ⁺ layer) 1306, an active layer (n ⁻ type (or p ⁻ type)) 1303, a p ⁺ layer (or n ⁺ ) are formed on the porous surface layer 1302 by MOCVD. Layer) 1304 is formed continuously (FIG. 13C).

  A polymer film substrate 1305 on which a copper paste is printed in advance as a back electrode 1309 is closely attached to the side on which the compound semiconductor layer 1303 is formed on the silicon single crystal substrate 1301, and is put in an oven (not shown) and heated. Then, the polymer film substrate 1305 and the silicon single crystal substrate 1301 are fixed (FIG. 13D).

  Next, force is applied between the polymer film substrate 1305 and the silicon single crystal substrate 1301 in a direction in which they are separated from each other. That is, using the flexibility of the polymer film, the both are gradually peeled off from the edge of the silicon single crystal substrate 1301 and separated at the porous layer 1302 (FIG. 13E).

  The porous layer 1302a remaining on the compound semiconductor layer 1303 separated from the silicon single crystal substrate is selectively removed using an etchant having a high silicon etching rate with respect to the compound semiconductor (FIG. 13F).

  A grid-like current collecting electrode 1308 and a surface antireflection layer 1307 are vacuum-deposited on the surface of the compound semiconductor layer 1303 from which the porous layer has been removed to form a solar cell (FIG. 13G).

  The silicon single crystal substrate 1301 is removed by removing the porous layer 1302b remaining on the surface in the same manner as described above, and if the surface flatness is unacceptably rough, surface flattening is performed as necessary. After being performed (FIG. 13 (h)), it is subjected to the process of FIG. 13 (a) again.

  When the method of the present invention is applied to a method for manufacturing a solar cell, a conductive metal paste such as a copper paste or a silver paste is inserted between the substrate and the thin film crystalline semiconductor layer so as to adhere to each other. And a method of fixing by baking is preferably used. In this case, the fired metal such as copper or silver also functions as a back electrode and a back reflection layer. In the case of a substrate such as a polymer film, the softening point of the film substrate with the substrate and the thin film crystal semiconductor layer in close contact (in this case, a back electrode is formed in advance on the surface of the thin film crystal semiconductor layer). The both may be fixed by raising the temperature.

  In the solar cell of the present invention, the surface of the semiconductor layer can be textured for the purpose of reducing the reflection loss of incident light. In the case of silicon, hydrazine, NaOH, KOH or the like is used. The height of the texture pyramid to be formed is suitably in the range of several μm to several tens of μm.

  Examples of the present invention will be described below, but the present invention is not limited to these examples.

  The surface layer of the single crystal Si substrate was anodized in an HF solution.

  The anodizing conditions were as follows.

Current density: 7 (mA · cm ⁻² )
Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
Time: 11 (min)
Thickness of porous Si: 12 (μm)
After sticking an adhesive film (Nitto Denko Co., Ltd. release tape No. 3200A) on the surface of the porous layer, the back surface was fixed with a vacuum chuck. The adhesive film was then peeled from the wafer. Thereby, porous Si was separated, and a porous Si layer remained on the film side. Such a porous Si layer can be applied to a light emitting device.

  The porous Si remaining on the first substrate side is then selectively etched while being stirred with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. Thereafter, hydrogen annealing or surface treatment such as surface polishing was performed, and the substrate was again input again.

  The surface layer of the single crystal Si substrate was anodized in an HF solution.

  The anodizing conditions were as follows.

Current density: 7 (mA · cm ⁻² )
Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
Time: 11 (min)
Thickness of porous Si: 12 (μm)
This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. By this oxidation, the inner walls of the porous Si holes were covered with a thermal oxide film. Single-crystal Si was epitaxially grown to a thickness of 0.15 μm on the porous Si by a CVD (Chemical Vapor Deposition) method. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 80 Torr
Temperature: 950 ° C
Growth rate: 0.3 μm / min
After sticking an adhesive film (Nitto Denko Co., Ltd. release tape BT-315) on the single crystal Si surface, the back surface of the substrate was fixed to a vacuum chuck. The adhesive film was then peeled from the wafer. Thereby, porous Si was divided, and an epitaxial layer and a porous Si layer remained on the film side.

  Thereafter, the porous Si remaining on the film side may be selectively etched while being stirred with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. Then, the single crystal Si remained without being etched, and the porous Si was completely removed by selective etching using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, the selectivity with respect to the etching rate of the porous layer reaches 10 ⁵ or more, and the etching amount in the non-porous layer (about several tens of angstroms) is The film thickness can be ignored in practical use.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  The porous Si remaining on the first substrate side is then selectively etched while being stirred with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. Thereafter, hydrogen annealing or surface treatment such as surface polishing was performed, and the substrate was again input again.

  The surface layer of the single crystal Si substrate was anodized in an HF solution.

  The anodizing conditions were as follows.

Current density: 7 (mA · cm ⁻² )
Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
Time: 4 (min)
Porous Si thickness: 4.5 (μm)
further,
Current density: 30 (mA · cm ⁻² )
Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
Time: 1 (min)
Thickness of porous Si: ~ 4 (μm)
Under the above conditions, a porous Si layer having a two-layer structure with different porosities was formed. By this anodization, the porosity of the porous Si layer by 30 (mA · cm ⁻² ) was increased, and a structurally fragile layer was formed.

  This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. By this oxidation, the inner walls of the porous Si holes were covered with a thermal oxide film. Single-crystal Si was epitaxially grown on the porous Si by 0.15 μm by CVD (Chemical Vapor Deposition). The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 80 Torr
Temperature: 950 ° C
Growth rate: 0.3 μm / min
After sticking an adhesive film (Nitto Denko Co., Ltd. release tape No. 31RH) on the single crystal Si surface, the back surface was fixed to a vacuum chuck. The adhesive film was then peeled from the wafer. As a result, the fragile porous Si having a large porosity was divided as a boundary, and the epitaxial layer and the porous Si layer were separated from the wafer on the film side.

  Thereafter, the porous Si remaining on the film side was selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. As a result, the single crystal Si remained without being etched, and the porous Si was completely removed by selective etching using the single crystal Si as an etch stop material.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  The porous Si remaining on the first substrate side was then selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. Thereafter, hydrogen annealing was performed, and the substrate could be recharged again.

A P ⁺ high concentration layer, which is a high concentration impurity layer, was formed in a thickness of 5 μm on the surface layer of the single crystal Si substrate with no resistance specified by a diffusion method. At the same time, a P ⁺ high concentration layer was also formed on the back surface. Anodization was performed in the HF solution from the high concentration surface layer side.

  The anodizing conditions were as follows.

Current density: 7 (mA · cm ⁻² )
Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
Time: 11 (min)
Thickness of porous Si: 12 (μm)
The porous Si layer has a two-layer structure. The lower porous Si had a fine fragile structure as compared with the surface layer portion.

  This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. By this oxidation, the inner walls of the porous Si holes were covered with a thermal oxide film. Single-crystal Si was epitaxially grown to a thickness of 0.15 μm on the porous Si by a CVD (Chemical Vapor Deposition) method. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 80 Torr
Temperature: 950 ° C
Growth rate: 0.3 μm / min
After the same adhesive film as used in Example 3 was attached to the surface, the adhesive film was peeled off from the wafer in the same manner as in Example 3.

  Thus, the lower fragile porous Si was divided as a boundary, and the epitaxial layer and the porous Si layer were separated from the wafer on the film side.

  Thereafter, the porous Si remaining on the film side was selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. As a result, the single crystal Si remained without being etched, and the porous Si was completely removed by selective etching using the single crystal Si as an etch stop material.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

The porous Si remaining on the first substrate side was then selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. Thereafter, surface treatment such as hydrogen annealing or surface polishing was performed, and the first substrate was again put into the diffusion process of the high concentration P ⁺ layer.

H ⁺ ions were implanted at 5 × 10 ¹⁶ cm ⁻² at 40 keV from the surface of the single-crystal Si substrate. The single crystal was maintained about 0.2 μm on the surface. In this case, it is better to form a SiO ₂ layer on the surface in advance from the viewpoint of preventing surface roughness due to ion implantation.

  After the same film as used in Example 1 was attached to the Si substrate surface, the film was peeled off from the wafer in the same manner as in Example 1.

As a result, the wafer was divided with the ion implantation layer as a boundary, and the SiO ₂ layer, the single crystal Si layer, and the ion implantation layer remained on the film side.

  Thereafter, the ion-implanted layer on the film side was selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. As a result, the single crystal Si remained without being etched, and the ion implantation layer was selectively removed by using the single crystal Si as an etch stop material and completely removed.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  The ion implantation layer remaining on the first substrate side was then selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. Thereafter, hydrogen annealing or surface treatment such as surface polishing was performed, and the substrate was again input again.

H ⁺ was ion-implanted from the surface of the first single crystal Si substrate at 20 keV at 5 × 10 ¹⁶ cm ⁻² . The single crystal was maintained about 0.1 μm on the surface. In this case, it is better to form a SiO ₂ layer on the surface in advance from the viewpoint of preventing surface roughness due to ion implantation.

After peeling off the protective SiO ₂ layer on the surface, single-crystal Si was epitaxially grown by 0.3 μm on the single-crystal Si by the CVD (Chemical Vapor Deposition) method. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 80 Torr
Temperature: 950 ° C
Growth rate: 0.3 μm / min
After the same film as used in Example 1 was attached to the surface, the film was peeled off from the wafer in the same manner as in Example 1.

  As a result, the wafer was separated from the ion implantation layer as a boundary, and the single crystal Si layer and the ion implantation layer remained on the film side.

  Thereafter, the ion-implanted layer on the film side was selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. As a result, the single crystal Si remained without being etched, and the ion implantation layer was selectively removed by using the single crystal Si as an etch stop material and completely removed.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  The ion implantation layer remaining on the first substrate side is then selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. Thereafter, hydrogen annealing or surface treatment such as surface polishing was performed, and the substrate was again input again.

  Single-crystal Si was epitaxially grown to a thickness of 0.3 μm on the first single-crystal Si substrate by a CVD (Chemical Vapor Deposition) method. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 80 Torr
Temperature: 950 ° C
Growth rate: 0.3 μm / min
H ⁺ was ion-implanted from the surface of the epitaxial Si layer at 40 keV at 5 × 10 ¹⁶ cm ⁻² . The single crystal was maintained about 0.2 μm on the surface. In this case, it is better to form a SiO ₂ layer on the surface in advance from the viewpoint of preventing surface roughness due to ion implantation.

  After the film used in Example 2 was attached to the surface, this film was peeled off from the wafer in the same manner as in Example 2.

As a result, the wafer was divided with the ion implantation layer as a boundary, and the SiO ₂ layer, the single crystal Si layer, and the ion implantation layer remained on the film side.

  Thereafter, the ion-implanted layer on the film side was selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. As a result, the single crystal Si remained without being etched, and the ion implantation layer was selectively removed by using the single crystal Si as an etch stop material and completely removed.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  The ion implantation layer remaining on the first substrate side is then selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. Thereafter, hydrogen annealing or surface treatment such as surface polishing was performed, and the substrate was again input again.

  The surface layer of the first single crystal Si substrate was anodized in an HF solution.

  The anodizing conditions were as follows.

Current density: 7 (mA · cm ⁻² )
Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
Time: 11 (min)
Thickness of porous Si: 12 (μm)
This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. By this oxidation, the inner walls of the porous Si holes were covered with a thermal oxide film. Single-crystal Si was epitaxially grown to a thickness of 0.15 μm on the porous Si by a CVD (Chemical Vapor Deposition) method. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 80 Torr
Temperature: 950 ° C
Growth rate: 0.3 μm / min
Furthermore, a 100 nm SiO ₂ layer was formed on the surface of the epitaxial Si layer by thermal oxidation.

  After the film used in Example 2 was attached to the surface, the film was peeled off from the wafer in the same manner as in Example 2.

As a result, the substrate was separated with the porous Si as a boundary, and the SiO ₂ layer, the epitaxial layer, and the porous Si layer remained on the film side.

Next, the porous layer on the back surface of the film was bonded to an acrylic substrate using an epoxy adhesive, and then the film was removed by etching. Thereafter, it was bonded to the surface of the Si substrate (second substrate) prepared separately from the exposed SiO ₂ layer surface. Since the surface of SiO _{2 and the} surface of the Si substrate were very flat, they were firmly attached only by applying pressure at room temperature.

  Here, an acrylic substrate is used as the support member, but a single layer or a multilayer structure is peeled from the first substrate using a film (for example, manufactured by Nitto Denko Corporation) whose adhesive strength is weakened by irradiation with ultraviolet rays. In some cases, the initial high adhesive force may be used, and the ultraviolet light may be irradiated to transfer it to another support, and the adhesive force may be weakened and peeled off from the structure.

  In addition, even if it does not use another support stand, a thin film is melt | dissolved by etching in a liquid, or the film which becomes weakly adhesive by the said ultraviolet-ray is used, and adhesive force is dropped by ultraviolet irradiation and it peels in a liquid. Thereafter, the remaining multilayer structure with a mesh, net, etc. is scooped and placed on the second substrate, whereby the surface side of the non-porous layer of the multilayer structure can be bonded to the second substrate.

  Thereafter, the acrylic substrate remaining on the second substrate side was ground and removed, and the porous Si was selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. As a result, the single crystal Si remained without being etched, and the porous Si was completely removed by selective etching using the single crystal Si as an etch stop material.

  That is, a single crystal Si layer having a thickness of 0.1 μm could be formed on the Si oxide film. When the film thickness of the formed single crystal Si layer was measured at 100 points on the entire surface, the uniformity of the film thickness was 101 nm ± 3 nm.

  Further, heat treatment was performed at 1100 ° C. in hydrogen for 1 hour. When the surface roughness was evaluated with an atomic force microscope, the mean square roughness in a 5 μm square region was about 0.2 nm, which was equivalent to a commercially available Si wafer.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  Similar results were obtained when the oxide film was formed not on the epitaxial layer surface but on the second substrate surface, or on both surfaces.

  At the same time, the porous Si remaining on the first substrate side is then selectively etched while being stirred with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. After that, surface treatment such as hydrogen annealing or surface polishing was performed, and it was possible to input again as the first substrate or the second substrate.

    The surface layer of the first single crystal Si substrate was anodized in an HF solution.

  The anodizing conditions were as follows.

Current density: 7 (mA · cm ⁻² )
Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
Time: 4 (min)
Porous Si thickness: 4.5 (μm)
further,
Current density: 30 (mA · cm ⁻² )
Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
Time: 1 (min)
Thickness of porous Si: ~ 4 (μm)
By this anodization, the porosity of the porous Si layer by 30 (mA · cm ⁻² ) was increased, and a structurally fragile layer was formed.

  This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. By this oxidation, the inner walls of the porous Si holes were covered with a thermal oxide film. Single-crystal Si was epitaxially grown 0.3 μm thick on porous Si by CVD (Chemical Vapor Deposition). The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 80 Torr
Temperature: 950 ° C
Growth rate: 0.3 μm / min
Further, a 200 nm SiO ₂ layer was formed on the surface of the epitaxial Si layer by thermal oxidation.

After a film was applied to the SiO ₂ surface in the same manner as in Example 8, the film was peeled off from the wafer.

As a result, the wafer was separated from the lower brittle porous Si as a boundary, and the SiO ₂ layer, the epitaxial layer, and the porous Si layer remained on the film side.

  Subsequently, the subsequent steps were performed in the same manner as in Example 8.

  As a result, a single crystal Si layer having a thickness of 0.2 μm was formed on the Si oxide film. When the film thickness of the formed single crystal Si layer was measured at 100 points over the entire surface, the uniformity of the film thickness was 201 nm ± 6 nm.

  Further, heat treatment was performed at 1100 ° C. in hydrogen for 1 hour. When the surface roughness was evaluated with an atomic force microscope, the mean square roughness in a 5 μm square region was about 0.2 nm, which was equivalent to a commercially available Si wafer.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

A P ⁺ high-concentration layer was formed in a thickness of 5 μm by a diffusion method on the surface layer of the first single crystal Si substrate with no resistance specified. At the same time, a P ⁺ high concentration layer was also formed on the back surface. Anodization was performed in the HF solution from the high concentration surface layer side.

  The anodizing conditions were as follows.

Current density: 7 (mA · cm ⁻² )
Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
Time: 11 (min)
Thickness of porous Si: 12 (μm)
The porous Si layer has a two-layer structure. The lower porous layer Si layer had a fine fragile structure as compared with the surface layer portion.

  This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. By this oxidation, the inner walls of the porous Si holes were covered with a thermal oxide film. Single-crystal Si was epitaxially grown 0.3 μm thick on porous Si by CVD (Chemical Vapor Deposition). The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 80 Torr
Temperature: 950 ° C
Growth rate: 0.3 μm / min
Further, a 200 nm SiO ₂ layer was formed on the surface of the epitaxial Si layer by thermal oxidation.

After a film was applied to the SiO ₂ surface in the same manner as in Example 8, the film was peeled off from the wafer.

As a result, the wafer was separated from the lower brittle porous Si as a boundary, and the SiO ₂ layer, the epitaxial layer, and the porous Si layer remained on the film side.

  Subsequent steps were performed in the same manner as in Example 8 to fabricate an SOI substrate.

  As a result, a single crystal Si layer having a thickness of 0.2 μm was formed on the Si oxide film. When the film thickness of the formed single crystal Si layer was measured at 100 points over the entire surface, the uniformity of the film thickness was 201 nm ± 6 nm.

  Further, heat treatment was performed at 1100 ° C. in hydrogen for 1 hour. When the surface roughness was evaluated with an atomic force microscope, the mean square roughness in a 5 μm square region was about 0.2 nm, which was equivalent to a commercially available Si wafer.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  Similar results were obtained when the oxide film was formed not on the epitaxial layer surface but on the second substrate surface, or on both surfaces.

At the same time, the porous Si remaining on the first substrate side was then selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. The single crystal Si is left unetched, the single crystal Si is used as an etch stop material, the porous Si is selectively etched and completely removed, and again as a first substrate in the diffusion process of the high concentration P ⁺ layer, Alternatively, it could be recharged as the second substrate.

H ⁺ was ion-implanted from the surface of the first single crystal Si substrate at 40 keV at 5 × 10 ¹⁶ cm ⁻² . The single crystal was maintained about 0.2 μm on the surface. Next, a thermal oxide film (SiO ₂ ) was formed on this surface.

After a film was applied to the SiO ₂ surface in the same manner as in Example 8, the film was peeled off from the wafer in the same manner.

As a result, the wafer was separated with the ion implantation layer as a boundary, and the SiO ₂ layer, the single crystal Si layer, and the ion implantation layer remained on the film side. Subsequently, the subsequent steps were performed in the same manner as in Example 8.

  As a result, a single crystal Si layer having a thickness of 0.2 μm was formed on the Si oxide film. When the film thickness of the formed single crystal Si layer was measured at 100 points over the entire surface, the uniformity of the film thickness was 201 nm ± 6 nm.

  Further, heat treatment was performed at 1100 ° C. in hydrogen for 1 hour. When the surface roughness was evaluated with an atomic force microscope, the mean square roughness in a 5 μm square region was about 0.2 nm, which was equivalent to a commercially available Si wafer.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  Similar results were obtained when the oxide film was formed not on the surface of the first substrate but on the surface of the second substrate, or on both surfaces.

H ⁺ was ion-implanted from the surface of the first single crystal Si substrate at 20 keV at 5 × 10 ¹⁶ cm ⁻² . The single crystal was maintained about 0.1 μm on the surface. In this case, it is better to form a SiO ₂ layer on the surface in advance from the viewpoint of preventing surface roughness due to ion implantation.

After peeling off the protective SiO ₂ layer on the surface, single-crystal Si was epitaxially grown by 0.3 μm on the single-crystal Si by the CVD (Chemical Vapor Deposition) method. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 80 Torr
Temperature: 950 ° C
Growth rate: 0.3 μm / min
Further, a 200 nm SiO ₂ layer was formed on the surface of the epitaxial Si layer by thermal oxidation.

After a film was applied to the SiO ₂ surface in the same manner as in Example 8, the film was peeled off from the wafer in the same manner as in Example 8.

As a result, the wafer was separated with the ion implantation layer as a boundary, and the SiO ₂ layer, the single crystal Si layer, and the ion implantation layer remained on the film side. Subsequently, the subsequent steps were performed in the same manner as in Example 8.

  As a result, a single crystal Si layer having a thickness of 0.2 μm was formed on the Si oxide film. When the film thickness of the formed single crystal Si layer was measured at 100 points over the entire surface, the uniformity of the film thickness was 201 nm ± 6 nm.

  Further, heat treatment was performed at 1100 ° C. in hydrogen for 1 hour. When the surface roughness was evaluated with an atomic force microscope, the mean square roughness in a 5 μm square region was about 0.2 nm, which was equivalent to a commercially available Si wafer.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  Similar results were obtained when the oxide film was formed not on the surface of the first substrate but on the surface of the second substrate, or on both surfaces.

  At the same time, the ion-implanted layer remaining on the first substrate side was then selectively etched while being stirred with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. After that, surface treatment such as hydrogen annealing or surface polishing was performed, and it was possible to input again as the first substrate or the second substrate.

  Single-crystal Si was epitaxially grown to a thickness of 0.3 μm on the first single-crystal Si substrate by a CVD (Chemical Vapor Deposition) method. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 80 Torr
Temperature: 950 ° C
Growth rate: 0.3 μm / min
H ⁺ was ion-implanted from the surface of the epitaxial Si layer at 40 keV at 5 × 10 ¹⁶ cm ⁻² . The single crystal was maintained about 0.2 μm on the surface. In this case, it is better to form a SiO ₂ layer on the surface in advance from the viewpoint of preventing surface roughness due to ion implantation.

Further, a 200 nm SiO ₂ layer was formed on the surface of the epitaxial Si layer by thermal oxidation.

After a film was applied to the SiO ₂ surface in the same manner as in Example 8, the film was peeled off from the wafer in the same manner as in Example 8.

As a result, the wafer was separated with the ion implantation layer as a boundary, and the SiO ₂ layer, the single crystal Si layer, and the ion implantation layer remained on the film side. Subsequently, the subsequent steps were performed in the same manner as in Example 8.

  Thus, a single crystal Si layer having a thickness of 0.2 μm was formed on the Si oxide film. When the film thickness of the formed single crystal Si layer was measured at 100 points over the entire surface, the uniformity of the film thickness was 201 nm ± 6 nm.

  Further, heat treatment was performed at 1100 ° C. in hydrogen for 1 hour. When the surface roughness was evaluated with an atomic force microscope, the mean square roughness in a 5 μm square region was about 0.2 nm, which was equivalent to a commercially available Si wafer.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  Similar results were obtained when the oxide film was formed not on the surface of the first substrate but on the surface of the second substrate, or on both surfaces.

  At the same time, the ion implantation layer remaining on the first substrate side is then selectively etched while being stirred with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. After that, surface treatment such as hydrogen annealing or surface polishing was performed, and it was possible to input again as the first substrate or the second substrate.

  The surface layer of the first single crystal Si substrate was anodized in an HF solution.

  The anodizing conditions were as follows.

Current density: 7 (mA · cm ⁻² )
Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
Time: 11 (min)
Thickness of porous Si: 12 (μm)
This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. By this oxidation, the inner walls of the porous Si holes were covered with a thermal oxide film. Single-crystal GaAs was epitaxially grown on the porous Si by 0.5 μm by MOCVD (Metal Organic Chemical Vapor Deposition) method. The growth conditions are as follows.

Source gas: TMG / AsH ₃ / H ₂
Gas pressure: 80 Torr
Temperature: 700 ° C
After the same film as in Example 1 was attached to the surface, the film was peeled off from the wafer in the same manner as in Example 1.

As a result, the wafer was separated at the boundary of porous Si, and an epitaxial layer and a porous Si layer remained on the film side. Next, the porous layer on the back surface of the film was bonded to an acrylic substrate using an epoxy adhesive, and then the film was removed by etching. Thereafter, the surface of the epitaxial layer exposed and the surface of a separately prepared Si substrate (second substrate) were bonded together. After grinding and removing the acrylic substrate, the surface on the second substrate side is
Ethylenediamine + pyrocatechol + water (ratio of 17ml: 3g: 8ml)
110 ° C
Etched with.

  As a result, the single crystal GaAs remained without being etched, and the remaining portion of the ion implantation layer and the first Si substrate was selectively removed using the single crystal GaAs as an etch stop material and completely removed.

  As a result, a single crystal GaAs layer having a thickness of 0.5 μm was formed on the Si substrate. When the film thickness of the formed single crystal GaAs layer was measured at 100 points on the entire surface, the uniformity of the film thickness was 504 nm ± 16 nm.

  When the surface roughness was evaluated with an atomic force microscope, the mean square roughness in a 50 μm square region was approximately 0.3 nm, which was equivalent to a commercially available GaAs wafer.

  As a result of cross-sectional observation using a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the GaAs layer after the epitaxial growth, and good crystallinity was maintained.

  Similar results were obtained with other compound semiconductors.

It is also possible to bond to the second substrate via the SiO ₂ layer.

  At the same time, the porous Si remaining on the first substrate side was then selectively etched while being stirred with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. After that, surface treatment such as hydrogen annealing or surface polishing was performed, and it was possible to input again as the first substrate or the second substrate.

  The surface layer of the first single crystal Si substrate was anodized in an HF solution.

  The anodizing conditions were as follows.

Current density: 7 (mA · cm ⁻² )
Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
Time: 11 (min)
Thickness of porous Si: 12 (μm)
This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. By this oxidation, the inner walls of the porous Si holes were covered with a thermal oxide film. Single-crystal Si was epitaxially grown to a thickness of 0.15 μm on the porous Si by a CVD (Chemical Vapor Deposition) method. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 80 Torr
Temperature: 950 ° C
Growth rate: 0.3 μm / min
Furthermore, a 100 nm SiO ₂ layer was formed on the surface of the epitaxial Si layer by thermal oxidation.

After the same film as used in Example 3 was applied to the SiO ₂ surface, the film was similarly peeled off from the wafer.

As a result, the wafer was separated at the boundary of porous Si, and the SiO ₂ layer, epitaxial layer, and porous Si layer remained on the film side. Thereafter, the porous Si remaining on the film side was selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. Then, the single crystal Si remained without being etched, and the porous Si was completely removed by selective etching using the single crystal Si as an etch stop material.

That is, a 0.1 μm-thick single crystal Si layer / 0.1 μm-thick SiO ₂ layer could be formed on the film side.

After peeling off the film from the multilayer film, the surface of the Si ₂ layer prepared separately from the surface of the SiO ₂ layer was bonded.

  That is, a single crystal Si layer having a thickness of 0.1 μm could be formed on the Si oxide film. When the film thickness of the formed single crystal Si layer was measured at 100 points on the entire surface, the uniformity of the film thickness was 101 nm ± 3 nm.

  Further, heat treatment was performed at 1100 ° C. in hydrogen for 1 hour. When the surface roughness was evaluated with an atomic force microscope, the mean square roughness in a 5 μm square region was about 0.2 nm, which was equivalent to a commercially available Si wafer.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  Similar results were obtained when the oxide film was formed not on the epitaxial layer surface but on the second substrate surface, or on both surfaces.

  At the same time, the porous Si remaining on the first substrate side is then selectively etched while being stirred with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. After that, surface treatment such as hydrogen annealing or surface polishing was performed, and it was possible to input again as the first substrate or the second substrate.

  The surface layer of the first single crystal Si substrate was anodized in an HF solution.

  The anodizing conditions were as follows.

Current density: 7 (mA · cm ⁻² )
Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
Time: 11 (min)
Thickness of porous Si: 12 (μm)
This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. By this oxidation, the inner walls of the porous Si holes were covered with a thermal oxide film. Single-crystal Si was epitaxially grown to a thickness of 0.15 μm on the porous Si by a CVD (Chemical Vapor Deposition) method. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 80 Torr
Temperature: 950 ° C
Growth rate: 0.3 μm / min
Furthermore, a 100 nm SiO ₂ layer was formed on the surface of the epitaxial Si layer by thermal oxidation.

H ⁺ was ion-implanted from the surface of the SiO ₂ layer at 100 keV at 3 × 10 ¹⁶ cm ⁻² . The porosity of the anodized porous Si layer near this projected range increased.

After the same film as in Example 3 was applied to the SiO ₂ surface, the film was peeled off from the wafer in the same manner.

As a result, the wafer was separated from the porous layer of porous layer (near the projected range of ion implantation) as a boundary, and the SiO ₂ layer, epitaxial layer, and porous Si layer remained on the film side. Subsequently, the subsequent steps were performed in the same manner as in Example 8.

  As a result, a single crystal Si layer having a thickness of 0.1 μm was formed on the Si oxide film. When the film thickness of the formed single crystal Si layer was measured at 100 points on the entire surface, the uniformity of the film thickness was 101 nm ± 3 nm.

  Further, heat treatment was performed at 1100 ° C. in hydrogen for 1 hour. When the surface roughness was evaluated with an atomic force microscope, the mean square roughness in a 5 μm square region was equivalent to that of a commercially available Si wafer at 0.2 nm.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  Similar results were obtained when the oxide film was formed not on the epitaxial layer surface but on the second substrate surface, or on both surfaces.

  At the same time, the porous Si remaining on the first substrate side was then selectively etched while being stirred with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. After that, surface treatment such as hydrogen annealing or surface polishing was performed, and it was possible to input again as the first substrate or the second substrate.

  An example in which a solar cell is formed by transferring a single crystal silicon layer to a polyimide film by the process shown in FIG.

On the surface of a single crystal silicon wafer having a thickness of 500 μm, B ⁺ ₃ was thermally diffused at a temperature of 1200 ° C. using BCl ₃ as a thermal diffusion source to form a p ⁺ layer to obtain a diffusion layer of about 3 μm (FIG. 12A). ). Next, anodization was performed in the HF solution under the conditions shown in Table 1 to form a porous silicon layer on the wafer (FIG. 12B). That is, after the chemical 2.5 minutes with a low current of the first 5mA / cm ^2, go slowly raising the current level, finished the conversion was reached to 30mA / cm ² in 30 seconds.

Epitaxial growth was performed on the surface of the porous silicon layer using the usual thermal CVD apparatus under the conditions shown in Table 2, and the thickness of the silicon layer (single crystal) was set to 30 μm.

At this time, a small amount of B ₂ H ₆ (about several ppm to several ppm) is added during the growth to make the grown silicon layer p ^- type, and the amount of B ₂ H ₆ is increased at the end of the growth. (About several hundred ppm) p ⁺ layer was formed (FIGS. 12C and 12D).

A copper paste was applied to one surface of a polyimide film having a thickness of 50 μm by screen printing to a thickness of 10 to 30 μm, and this surface was adhered to the p ⁺ silicon layer surface of the wafer.

  In this state, the copper paste was baked under conditions of 360 ° C. for 20 minutes in an oven, and the polyimide film and the wafer were fixed (FIG. 12E).

  The surface of the bonded polyimide film and the wafer is fixed with a vacuum chuck (not shown) on the non-bonded side of the wafer, and a force is applied from one end of the polyimide film to flex the polyimide film. Peeling is performed by gradually peeling them from the edge of the wafer. In this way, the silicon layer was peeled off from the wafer and transferred onto the polyimide film (FIG. 12 (f)).

  The porous layer remaining on the silicon layer peeled off from the silicon wafer was selectively etched while stirring with a mixed solution of hydrofluoric acid, hydrogen peroxide solution and pure water. The silicon layer remained unetched and only the porous layer was completely removed.

In the non-porous silicon single crystal, the etching rate with respect to the above-mentioned etching solution is extremely low, and the selectivity with respect to the etching rate of the porous layer reaches 10 ⁵ or more. Is a film thickness reduction that can be ignored in practice.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the silicon layer and that good crystallinity was maintained.

  After cleaning the surface of the silicon layer on the obtained polyimide film with a hydrofluoric acid / nitric acid-based etching solution, the surface of the silicon layer is n on the silicon layer by a normal plasma CVD apparatus under the conditions shown in Table 3. A 200 μm thick μc-Si layer was deposited (FIG. 12G). The dark conductivity of the μc-Si layer at this time was ˜5 S / cm.

Finally, an ITO transparent conductive film (82 nm) / collecting electrode (Ti / Pd / Ag (400 nm / 200 nm / 1 μm)) was formed on the μc-Si layer by EB (Electron Beam) vapor deposition to obtain a solar cell ( FIG. 12 (h)).

This way, a polyimide thin film monocrystalline silicon solar cell obtained was measured for the I-V characteristic under the light irradiation of AM1.5 (100mW / cm ^2), open circuit voltage in the cell area 6 cm ² 0. 6V, a short-circuit photocurrent of 35 mA / cm ² , and a fill factor of 0.79, resulting in an energy conversion efficiency of 16.6%.

  Further, the porous layer remaining on the peeled silicon wafer was also removed by etching in the same manner as described above to give a smooth surface (FIG. 12 (i)). A plurality of thin-film single crystal solar cells having a high-quality semiconductor layer were obtained by repeating the above-described steps using the reclaimed wafer thus obtained.

  In this example, a solar cell is formed by transferring a polycrystalline silicon layer to a polyimide film by the process shown in FIG.

On the surface of a cast silicon (polycrystalline silicon) wafer having a thickness of 1 mm, thermal diffusion of B was performed at a temperature of 1200 ° C. using BCl ₃ as a thermal diffusion source to form a p ⁺ layer to obtain a diffusion layer of about 3 μm (see FIG. 12 (a)). Next, anodization was performed in the HF solution under the conditions shown in Table 4 to form a porous silicon layer on the wafer (FIG. 12B). Specifically, after 2.5 differentiation at a low current of 5 mA / cm ² , the current level was suddenly increased and the formation was completed at 100 mA / cm ² for 8 seconds.

Crystal growth was performed on the surface of the porous silicon layer using the usual thermal CVD apparatus under the conditions shown in Table 5, and the film thickness of the silicon layer (polycrystal) was set to 30 μm.

At this time, a small amount of PH ₃ (about several ppm to several ppm) is added during the growth to make the grown silicon layer n ^- type, and at the end of the growth, the amount of PH ₃ is increased (several hundreds). An n ⁺ layer was formed (about ppm) (FIGS. 12C and 12D).

A silver paste was applied to one surface of a polyimide film having a thickness of 50 μm by screen printing to a thickness of 10 to 30 μm, and this surface was adhered to the n ⁺ silicon layer surface of the wafer.

  In this state, the silver paste was baked under conditions of 360 ° C. and 20 minutes in an oven, and the polyimide film and the wafer were fixed (FIG. 12E).

  The surface of the bonded polyimide film and the wafer is fixed with a vacuum chuck (not shown) on the non-bonded side of the wafer, and a force is applied from one end of the polyimide film to flex the polyimide film. Peeling is performed by gradually peeling them from the edge of the wafer. In this way, the silicon layer was peeled off from the wafer and transferred onto the polyimide film (FIG. 12 (f)).

  The porous layer remaining on the silicon layer peeled off from the silicon wafer was selectively etched while stirring with a mixed solution of hydrofluoric acid, hydrogen peroxide solution and pure water. The silicon layer remained unetched and only the porous layer was completely removed.

Non-porous silicon polycrystal has an extremely low etching rate with respect to the above-mentioned etching solution, and the selectivity with respect to the etching rate of the porous layer reaches 10 ⁵ or more. The etching amount in the non-porous silicon layer (several tens of thousands) Is a film thickness reduction that can be ignored in practice.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the silicon layer and that good crystallinity was maintained.

  The surface of the silicon layer on the obtained polyimide film is cleaned by etching with a hydrofluoric acid / nitric acid based etching solution, and then p is formed on the silicon layer by a normal plasma CVD apparatus under the conditions shown in Table 6. A 200 μm thick μc-Si layer was deposited (FIG. 12G). The dark conductivity of the μc-Si layer at this time was ˜1 S (Siemens) / cm (Siemens is the reciprocal of ohm (Ω)).

Finally, an ITO transparent conductive film (82 nm) / current collecting electrode (Ti / Pd / Ag (400 nm / 200 nm / 1 μm)) was formed on the μc-Si layer by EB vapor deposition to obtain a solar cell (FIG. 12 (h )).

When the IV characteristics under the light irradiation of AM1.5 (100 mW / cm ² ) of the thin film polycrystalline silicon solar cell on polyimide obtained in this way were measured, the open area voltage was 0.58 V with a cell area of 6 cm ^2. The short-circuit photocurrent was 33 mA / cm ² , the fill factor was 0.78, and the energy conversion efficiency was 14.9%.

  Further, the porous layer remaining on the peeled silicon wafer was also removed by etching in the same manner as described above to give a smooth surface (FIG. 12 (i)). A plurality of thin-film polycrystalline solar cells having a high-quality semiconductor layer were obtained by repeating the above-described steps using the reclaimed wafer thus obtained.

  The example which transferred the compound semiconductor layer to the polyimide film and formed the solar cell is shown.

A p ⁺ layer was formed on the surface of a 500 μm thick single crystal silicon wafer by carrying out B thermal diffusion at a temperature of 1200 ° C. using BCl ₃ as a thermal diffusion source to obtain a diffusion layer of about 3 μm (FIG. 13A). ). Next, anodization was performed in the HF solution under the conditions shown in Table 7 to form a porous silicon layer on the wafer (FIG. 13B). That is, after differentiation for 2 minutes and 2.5 at low currents of 1 mA / cm ² and 5 mA / cm ² respectively, the current level was slowly increased and formation was achieved when 40 mA / cm ² was reached in 20 seconds. finished.

After annealing the surface of the porous silicon layer in a hydrogen atmosphere at 1050 ° C. for 7 minutes, a GaAs / AlGaAs layer (single crystal) having a tandem structure shown in FIG. 14 was deposited by a MOCVD (metal organic chemical vapor deposition) apparatus (FIG. 13 ( c); Note that 1306, 1303, and 1304 in FIG. 13 are replaced with 1403 to 1413 in FIG. 14, the crystal substrate 1401, 1402 is a porous layer, 1403 n ⁺ GaAs, 1404 is _{^{n + Al x Ga 1-x}} As, 1405 are n Al _0.37 Ga _0.63 As, 1406 are p Al0.37Ga0.63As , 1407 ^{p + Alx Ga1-x As,} 1408 are p Al _0.37 Ga _0.63 As, 1409 is _{^{n + Al x Ga 1-x}} As, 1410 are n Al _0.37 Ga _0.63 As, 1411 is n ⁺ Al _0.9 Ga _0.1 As 1412 are nGaAs and 1413 is pGaAs.

  After Pd / Au is formed by EB deposition on the grown p-GaAs layer, the copper paste is applied to one side of a 50 μm thick polyimide film by screen printing to a thickness of 10 to 30 μm. The wafer was bonded in close contact with the GaAs / AlGaAs layer side of the wafer.

  In this state, the copper paste was baked under conditions of 370 ° C. and 20 minutes in an oven, and the polyimide film and the wafer were fixed (FIG. 13D).

  The polyimide film and the wafer that are fixed are fixed to the surface of the wafer that is not bonded with a vacuum chuck (not shown), and a force is applied from one end of the polyimide film to Peeling is performed by gradually peeling the two from the edge of the wafer using flexibility. In this way, the porous layer was broken, and the GaAs / AlGaAs layer was peeled off from the wafer and transferred onto the polyimide film (FIG. 13 (e)).

  The porous layer remaining on the GaAs / AlGaAs layer peeled off from the silicon wafer was selectively etched at 110 ° C. with a mixed solution of ethylenediamine + pyrocatechol + pure water. The GaAs / AlGaAs layer remained without being etched, and only the porous layer was completely removed (FIG. 13 (f)).

  The etching rate of single crystal GaAs with respect to the above-described etching solution is extremely low, and the film thickness can be ignored in practical use.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the GaAs / AlGaAs layer and that good crystallinity was maintained.

The n ⁺ GaAs layer which is the outermost surface layer of the GaAs / AlGaAs layer on the obtained polyimide film is etched in a grid pattern to expose the n ⁺ Al _x Ga _1-x As layer, and the surface electrode (Au / Ge / Ni / Au) is formed only on the grid-like n ⁺ GaAs layer by EB evaporation and photolithography, and then TiO ₂ / MgO is deposited by plasma CVD as an antireflection film to form a solar cell (FIG. 13 ( g)).

Thus the polyimide film on the thin-film single-crystal GaAs / AlGaAs solar cell obtained AM1.5 (100mW / cm ²⁾ was measured for the I-V characteristic under irradiation with light, open-circuit voltage in the cell area of 4 cm ² 2 .3V, short-circuit photocurrent of 12.8 mA / cm ² and fill factor of 0.81, resulting in an energy conversion efficiency of 23.8%.

  Further, the porous layer remaining on the peeled silicon wafer was removed by etching in the same manner as in Example 17 and Example 18, and a smooth surface was obtained (FIG. 13 (h)). A plurality of thin film compound semiconductor solar cells having high-quality semiconductor layers were obtained by repeating the above-described steps using the thus obtained recycled wafer.

  The surface layer of the first single crystal Si substrate was anodized in an HF solution.

  The anodizing conditions were as follows.

Current density: 7 (mA · cm ⁻² )
Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
Time: 11 (min)
Thickness of porous Si: 12 (μm)
This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. By this oxidation, the inner walls of the porous Si holes were covered with a thermal oxide film. Single-crystal Si was epitaxially grown to a thickness of 0.15 μm on the porous Si by a CVD (Chemical Vapor Deposition) method. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 80 Torr
Temperature: 950 ° C
Growth rate: 0.3 μm / min
Further, a 20 nm SiO ₂ layer was formed on the surface of the epitaxial Si layer by thermal oxidation. In addition, this oxide film is provided as protection when sticking an adhesive film.

After a film was applied to the SiO ₂ surface in the same manner as in Example 1, the film was similarly peeled off from the wafer.

As a result, the film was peeled off through the porous Si, and the SiO ₂ layer, the epitaxial layer, and the porous Si layer were separated from the wafer on the film side.

  Thereafter, the porous Si remaining on the film side was selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. As a result, the single crystal Si remained without being etched, and the porous Si was completely removed by selective etching using the single crystal Si as an etch stop material.

  The single crystal Si layer surface exposed by etching was bonded to the surface of a Si substrate on which a 200 nm oxide film was formed.

  Thereafter, the film was removed by etching to form a single crystal Si layer having a thickness of 0.1 μm on the second substrate. When the film thickness of the formed single crystal Si layer was measured at 100 points on the entire surface, the uniformity of the film thickness was 101 nm ± 3 nm.

  Further, heat treatment was performed in hydrogen at 1100 ° C. for 1 hour. When the surface roughness was evaluated with an atomic force microscope, the mean square roughness in a 5 μm square region was about 0.2 nm, which was equivalent to a commercially available Si wafer.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  At the same time, the porous Si remaining on the first substrate side is then selectively etched while being stirred with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. After that, surface treatment such as hydrogen annealing or surface polishing was performed, and it was possible to input again as the first substrate or the second substrate.

H ⁺ was ion-implanted from the surface of the first single crystal Si substrate at 40 keV at 5 × 10 ¹⁶ cm ⁻² . The single crystal was maintained about 0.2 μm on the surface. In this case, it is better to form a SiO ₂ layer on the surface in advance from the viewpoint of preventing surface roughness due to ion implantation.

  After a film was applied to the surface in the same manner as in Example 3, the film was similarly peeled off from the wafer.

As a result, the wafer was separated with the ion implantation layer as a boundary, and the SiO ₂ layer, the single crystal Si layer, and the ion implantation layer remained on the film side.

  Thereafter, the ion-implanted layer remaining on the film side was selectively etched while being stirred with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. As a result, the single crystal Si remained without being etched, and the ion implantation layer was selectively removed by using the single crystal Si as an etch stop material and completely removed.

  It was bonded to the surface of the second substrate prepared separately from the surface of the single crystal Si layer exposed by etching. As the second substrate, two types of substrates, a Si substrate having a 200 nm oxide film formed on the surface and a quartz substrate, were prepared.

  Thereafter, the film was peeled off or removed by etching to form a single crystal Si layer having a thickness of 0.2 μm on the second substrate. When the film thickness of the formed single crystal Si layer was measured at 100 points over the entire surface, the uniformity of the film thickness was 201 nm ± 6 nm.

  Further, heat treatment was performed in hydrogen. In the case of the Si substrate, the temperature was 1100 ° C. for 1 hour, and in the case of the quartz substrate, the temperature was 900 ° C. for 4 hours. When the surface roughness was evaluated with an atomic force microscope, the mean square roughness in a 5 μm square region was about 0.2 nm, which was equivalent to a commercially available Si wafer.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  At the same time, the ion-implanted layer remaining on the first substrate side was then selectively etched while being stirred with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. After that, surface treatment such as hydrogen annealing or surface polishing was performed, and it was possible to input again as the first substrate or the second substrate.

H ⁺ was ion-implanted from the surface of the first single crystal Si substrate at 20 keV at 5 × 10 ¹⁶ cm ⁻² . The single crystal was maintained about 0.1 μm on the surface. In this case, it is better to form a SiO ₂ layer on the surface in advance from the viewpoint of preventing surface roughness due to ion implantation.

After peeling off the protective SiO ₂ layer on the surface, single-crystal Si was epitaxially grown by 0.3 μm on the single-crystal Si by the CVD (Chemical Vapor Deposition) method. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 80 Torr
Temperature: 950 ° C
Growth rate: 0.3 μm / min
Further, a 20 nm SiO ₂ layer was formed on the surface of the epitaxial Si layer by thermal oxidation. In addition, this oxide film is provided as protection when sticking an adhesive film.

  After the film was attached to the surface in the same manner as in Example 3, the film was peeled off from the wafer in the same manner as in Example 3.

As a result, the wafer was separated with the ion implantation layer as a boundary, and the SiO ₂ layer, the single crystal Si layer, and the ion implantation layer remained on the film side.

  Thereafter, the ion-implanted layer remaining on the film side was selectively etched while being stirred with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. As a result, the single crystal Si remained without being etched, and the ion implantation layer was selectively removed by using the single crystal Si as an etch stop material and completely removed.

  The surface of the single crystal Si layer exposed by etching was bonded to the surface of a quartz substrate prepared separately.

  Thereafter, the film was removed by etching to form a single crystal Si layer having a thickness of 0.2 μm on the quartz substrate. When the film thickness of the formed single crystal Si layer was measured at 100 points over the entire surface, the uniformity of the film thickness was 201 nm ± 6 nm.

  Further, heat treatment was performed in hydrogen at 900 ° C. for 4 hours. When the surface roughness was evaluated with an atomic force microscope, the mean square roughness in a 5 μm square region was about 0.2 nm, which was equivalent to a commercially available Si wafer.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  At the same time, the ion-implanted layer remaining on the first substrate side was then selectively etched while being stirred with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. After that, surface treatment such as hydrogen annealing or surface polishing was performed, and it was possible to input again as the first substrate or the second substrate.

  Single-crystal Si was epitaxially grown to a thickness of 0.3 μm on the first single-crystal Si substrate by a CVD (Chemical Vapor Deposition) method. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 80 Torr
Temperature: 950 ° C
Growth rate: 0.3 μm / min
H ⁺ was ion-implanted from the surface of the epitaxial Si layer at 40 keV at 5 × 10 ¹⁶ cm ⁻² . The single crystal was maintained about 0.2 μm on the surface. In this case, it is better to form a SiO ₂ layer on the surface in advance from the viewpoint of preventing surface roughness due to ion implantation.

Further, a 20 nm SiO ₂ layer was formed on the surface of the epitaxial Si layer by thermal oxidation. In addition, this oxide film is provided as protection when sticking an adhesive film.

After a film was applied to the SiO ₂ surface in the same manner as in Example 3, the film was peeled off from the wafer in the same manner as in Example 3.

As a result, the wafer was separated with the ion implantation layer as a boundary, and the SiO ₂ layer, the single crystal Si layer, and the ion implantation layer remained on the film side. Subsequently, the subsequent steps were performed in the same manner as in Example 22.

  When the surface roughness of the substrate thus obtained was evaluated with an atomic force microscope, the mean square roughness in a 5 μm square region was about 0.2 nm, which was equivalent to a commercially available Si wafer.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  At the same time, the ion-implanted layer remaining on the first substrate side was then selectively etched while being stirred with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. After that, surface treatment such as hydrogen annealing or surface polishing was performed, and it was possible to input again as the first substrate or the second substrate.

H ⁺ was ion-implanted from the surface of the first single crystal Si substrate at 40 keV at 5 × 10 ¹⁶ cm ⁻² . The single crystal was maintained about 0.2 μm on the surface. In this case, it is better to form a SiO ₂ layer on the surface in advance from the viewpoint of preventing surface roughness due to ion implantation.

  After a film was applied to the surface in the same manner as in Example 3, the film was similarly peeled off from the wafer.

As a result, the wafer was separated from the ion implantation layer as a boundary, and the SiO ₂ layer, single crystal Si layer, and ion implantation layer were separated from the wafer on the film side.

  Thereafter, the ion-implanted layer remaining on the film side was selectively etched while being stirred with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. As a result, the single crystal Si remained without being etched, and the ion implantation layer was selectively removed by using the single crystal Si as an etch stop material and completely removed.

After peeling the film from the multilayer film, the exposed SiO ₂ layer surface and the surface of a separately prepared Si substrate (second substrate) were bonded together.

  As a result, a single crystal Si layer having a thickness of 0.2 μm was formed on the Si oxide film. When the film thickness of the formed single crystal Si layer was measured at 100 points over the entire surface, the uniformity of the film thickness was 201 nm ± 6 nm.

  Further, heat treatment was performed at 1100 ° C. in hydrogen for 1 hour. When the surface roughness was evaluated with an atomic force microscope, the mean square roughness in a 5 μm square region was about 0.2 nm, which was equivalent to a commercially available Si wafer.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  Similar results were obtained when the oxide film was formed not on the surface of the first substrate but on the surface of the second substrate, or on both surfaces.

  The ion implantation layer remaining on the first substrate side was then selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide. After that, surface treatment such as hydrogen annealing or surface polishing was performed, and it was possible to input again as the first substrate or the second substrate.

H ⁺ was ion-implanted from the surface of the first single crystal Si substrate at 20 keV at 5 × 10 ¹⁶ cm ⁻² . The single crystal was maintained about 0.1 μm on the surface. In this case, it is better to form a SiO ₂ layer on the surface in advance from the viewpoint of preventing surface roughness due to ion implantation.

After peeling off the protective SiO ₂ layer on the surface, single-crystal Si was epitaxially grown by 0.3 μm on the single-crystal Si by the CVD (Chemical Vapor Deposition) method. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 80 Torr
Temperature: 950 ° C
Growth rate: 0.3 μm / min
Further, a 200 nm SiO ₂ layer was formed on the surface of the epitaxial Si layer by thermal oxidation.

  After the film used in Example 2 was attached to the surface, the film was similarly peeled off from the wafer.

As a result, the wafer was separated with the ion implantation layer as a boundary, and the SiO ₂ layer, the single crystal Si layer, and the ion implantation layer remained on the film side. Next, the subsequent steps were performed in the same manner as in Example 24.

  As a result, a single crystal Si layer having a thickness of 0.2 μm was formed on the Si oxide film. When the film thickness of the formed single crystal Si layer was measured at 100 points over the entire surface, the uniformity of the film thickness was 201 nm ± 6 nm.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  Single-crystal Si was epitaxially grown to a thickness of 0.3 μm on the first single-crystal Si substrate by a CVD (Chemical Vapor Deposition) method. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 80 Torr
Temperature: 950 ° C
Growth rate: 0.3 μm / min
H ⁺ was ion-implanted from the surface of the epitaxial Si layer at 40 keV at 5 × 10 ¹⁶ cm ⁻² . The single crystal was maintained about 0.2 μm on the surface. In this case, it is better to form a SiO ₂ layer on the surface in advance from the viewpoint of preventing surface roughness due to ion implantation.

Further, a 200 nm SiO ₂ layer was formed on the surface of the epitaxial Si layer by thermal oxidation.

  After a film was attached to the surface in the same manner as in Example 2, the film was similarly peeled off from the wafer.

As a result, the wafer was separated with the ion implantation layer as a boundary, and the SiO ₂ layer, the single crystal Si layer, and the ion implantation layer remained on the film side. Next, the subsequent steps were performed in the same manner as in Example 24.

  As a result, a single crystal Si layer having a thickness of 0.2 μm was formed on the Si oxide film. When the film thickness of the formed single crystal Si layer was measured at 100 points over the entire surface, the uniformity of the film thickness was 201 nm ± 6 nm.

  Further, heat treatment was performed at 1100 ° C. in hydrogen for 1 hour. When the surface roughness was evaluated with an atomic force microscope, the mean square roughness in a 5 μm square region was about 0.2 nm, which was equivalent to a commercially available Si wafer.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  In this example, a solar cell is formed by transferring a single crystal silicon layer to a Tefzel film (DuPont transparent film) by the process shown in FIG.

On the surface of a single crystal silicon wafer having a thickness of 500 μm, B diffusion was performed at a temperature of 1200 ° C. using BCl ₃ as a thermal diffusion source to form a p ⁺ layer to obtain a diffusion layer of about 3 μm (FIG. 15A). ). Next, anodization was performed in the HF solution under the conditions shown in Table 8 to form a porous silicon layer on the wafer (FIG. 15B). That is, after the chemical 2.5 minutes with a low current of the first 5mA / cm ^2, go slowly raising the current level, finished the conversion was reached to 30mA / cm ² in 30 seconds.

Epitaxial growth was performed on the surface of the porous silicon layer using the usual thermal CVD apparatus under the conditions shown in Table 9, and the film thickness of the silicon layer (single crystal) was set to 30 μm.

At this time, several hundred ppm of B ₂ H ₆ was added at the initial stage of growth to form a p ⁺ layer of 1 μm, and then the amount of B ₂ H ₆ was changed to 0. The growth silicon layer is made p ⁻ type at several ppm to several ppm, and at the end of growth, PH ₃ is added at several hundred ppm instead of B ₂ H ₆ to form an n ⁺ layer of 0.2 μm. A junction was formed (FIG. 15C).

After completion of the growth, an ITO transparent conductive film (82 nm) / collecting electrode (Ti / Pd / Ag (400 nm / 200 nm / 1 μm)) is formed on the n ⁺ layer by EB (Electron Beam) vapor deposition to previously form a solar cell structure. After fabrication (FIG. 15 (d)), a transparent adhesive is applied to one side of a 80 μm thick Tefzel film with a thickness of 10 to 30 μm, and this surface is in close contact with the transparent conductive film / collecting electrode surface of the wafer described above. And bonded together (FIG. 15 (e)).

  When the adhesive is fully cured, the non-bonded surface of the wafer is fixed to the fixed Tefzel film and wafer with a vacuum chuck (not shown). A force is applied to peel off the wafer from the edge of the wafer using the flexibility of the Tefzel film. In this way, the silicon layer was peeled off from the wafer and transferred onto the Tefzel film (FIG. 15 (f)).

  The porous layer remaining on the silicon layer peeled off from the silicon wafer was selectively etched while stirring with a mixed solution of hydrofluoric acid, hydrogen peroxide solution and pure water. The silicon layer remained unetched and only the porous layer was completely removed.

  The back surface of the silicon layer on the obtained Tefzel film was sputtered with 0.1 μm of Al to form a back electrode (FIG. 15G).

The IV characteristics when the AM 1.5 (100 mW / cm ² ) light irradiation was measured from the Tefzel film side for the thin film on the Tefzel thin-film single crystal silicon solar cell thus obtained was 6 cm ² in cell area. The open-circuit voltage was 0.59 V, the short-circuit photocurrent was 34 mA / cm ² , and the fill factor was 0.79, resulting in an energy conversion efficiency of 15.8%.

  Further, the porous layer remaining on the peeled silicon wafer was also removed by etching in the same manner as described above to give a smooth surface (FIG. 15 (h)). A plurality of thin-film single crystal solar cells having a high-quality semiconductor layer were obtained by repeating the above-described steps using the reclaimed wafer thus obtained.

  In this embodiment, an example is shown in which a single crystal silicon layer is once transferred to a resin film by the process shown in FIG. 16, and then the silicon layer is transferred again onto a second substrate to form a solar cell.

On the surface of a single crystal silicon wafer having a thickness of 500 μm, B ⁺ ₃ was thermally diffused at a temperature of 1200 ° C. using BCl ₃ as a thermal diffusion source to form a p ⁺ layer to obtain a diffusion layer of about 3 μm (FIG. 16A). ). Next, anodization was performed in the HF solution under the conditions shown in Table 10 to form a porous silicon layer on the wafer (FIG. 16B). That is, after the chemical 2.5 minutes with a low current of the first 5mA / cm ^2, go slowly raising the current level, finished the conversion was reached to 30mA / cm ² in 30 seconds.

Epitaxial growth was performed on the surface of the porous silicon layer with the usual thermal CVD apparatus under the conditions shown in Table 11, and the film thickness of the silicon layer (single crystal) was set to 40 μm.

At this time, several hundred ppm of B ₂ H ₆ was added at the initial stage of growth to form a p ⁺ layer of 1 μm, and then the amount of B ₂ H ₆ was changed to 0. The growth silicon layer is made p ⁻ type at several ppm to several ppm, and at the end of growth, PH ₃ is added at several hundred ppm instead of B ₂ H ₆ to form an n ⁺ layer of 0.2 μm. A bond was formed (FIG. 16C).

The pressure-sensitive adhesive surface of the 90 μm-thick UV curable pressure-sensitive adhesive film was adhered and adhered to the n ⁺ layer of the wafer (FIG. 16D).

  The surface of the wafer that is not bonded is fixed to the adhered adhesive film and the wafer with a vacuum chuck (not shown), and a force is applied from one end of the adhesive film to flex the adhesive film. Peeling is performed by gradually peeling them from the edge of the wafer. In this way, the silicon layer was peeled from the wafer and transferred onto the adhesive film (FIG. 16 (e)).

  The porous layer remaining on the silicon layer peeled off from the silicon wafer was selectively etched while stirring with a mixed solution of hydrofluoric acid, hydrogen peroxide solution and pure water. The silicon layer remained unetched and only the porous layer was completely removed.

  A back electrode was formed by applying 0.1 μm of Ag to the back surface of the silicon layer on the obtained adhesive film by sputtering (FIG. 16F). A backing plate made of SUS made of tin / lead solder was brought into contact with the back electrode surface of the silicon layer, and in this state, the solder was melted by applying heat to fix the backing plate and the silicon layer (FIG. 16 ( g)).

Finally, the adhesive film attached to the surface of the silicon layer is irradiated with ultraviolet rays to lower the adhesive property and peeled off from the silicon layer. Then, an ITO transparent conductive film (82 nm) is deposited on the n ⁺ layer by EB (Electron Beam) deposition. ) / Collecting electrode (Ti / Pd / Ag (400 nm / 200 nm / 1 μm)) was formed (FIG. 16H).

This way, the thin-film single crystal silicon solar cell obtained by double transfer, AM1.5 (100mW / cm ²⁾ was measured for the I-V characteristic under irradiation with light, open-circuit voltage in the cell area 6 cm ² 0. 6V, short-circuit photocurrent 34 mA / cm ² , fill factor 0.78, and energy conversion efficiency of 15.9% was obtained.

  Further, the porous layer remaining on the peeled silicon wafer was also removed by etching in the same manner as described above to give a smooth surface (FIG. 16 (i)). A plurality of thin-film single crystal solar cells having a high-quality semiconductor layer were obtained by repeating the above-described steps using the reclaimed wafer thus obtained.

  In this example, a solar cell is formed by transferring a silicon layer formed on a metal grade silicon substrate to a polyimide film by the process shown in FIG.

  Metal grade silicon refers to silicon having an impurity concentration in the range of about 1 ppm to 2%.

  An ingot was pulled up by a CZ (Czochralski) method using metal grade silicon with a purity of 98%, sliced into a 0.5 mm thick wafer, and the surface was mirror-polished to produce a metal grade silicon substrate. When elemental analysis in the vicinity of the surface of the produced metal grade silicon substrate was performed, the results shown in Table 12 were obtained.

The crystal grain size of the metal grade silicon substrate was several mm to several cm, and the specific resistance was 0.05 Ω · cm (p-type) (FIG. 12A).

Next, anodization was performed in the HF solution under the conditions shown in Table 13 to form a porous silicon layer on the metal grade silicon (FIG. 12B). That is, after ^two differentiation at low current of 2 mA / cm ² at first, the current level was slowly increased to reach 25 mA / cm ² in 1 minute, and then the formation was finished when this current level was held for 6 seconds. .

Crystal growth was performed on the surface of the porous silicon layer by a normal thermal CVD apparatus under the formation conditions shown in Table 14, and the film thickness of the silicon layer (polycrystal) was set to 30 μm.

At this time, a small amount of B ₂ H ₆ (about several ppm to several ppm) is added during the growth to make the grown silicon layer p ^- type, and the amount of B ₂ H ₆ is increased at the end of the growth. (About several hundred ppm) p ⁺ layer was formed (FIGS. 12C and 12D).

A copper paste was applied to one side of a polyimide film having a thickness of 50 μm by screen printing to a thickness of 10 to 30 μm, and this side was brought into close contact with the p ⁺ silicon layer surface of the metal grade silicon substrate described above.

  In this state, the copper paste was baked under conditions of 360 ° C. for 20 minutes in an oven, and the polyimide film and the wafer were fixed (FIG. 12E).

  The surface of the bonded polyimide film and the wafer is fixed with a vacuum chuck (not shown) on the non-bonded side of the wafer, and a force is applied from one end of the polyimide film to flex the polyimide film. Peeling is performed by gradually peeling them from the edge of the wafer. In this way, the silicon layer was peeled off from the metal grade silicon substrate and transferred onto the polyimide film (FIG. 12 (f)).

  The porous layer remaining on the silicon layer peeled off from the metal grade silicon substrate was selectively etched while stirring with a mixed solution of hydrofluoric acid, hydrogen peroxide solution and pure water. The silicon layer remained unetched and only the porous layer was completely removed.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the silicon layer and that good crystallinity was maintained.

  After cleaning the surface of the silicon layer on the obtained polyimide film with a hydrofluoric acid / nitric acid-based etchant, the conditions shown in Table 3 above were performed on the silicon layer by a normal plasma CVD apparatus. Then, 200 n-type μc-Si layer was deposited (FIG. 12G).

  Finally, an ITO transparent conductive film (82 nm) / collecting electrode (Ti / Pd / Ag (400 nm / 200 nm / 1 μm)) was formed on the μc-Si layer by EB vapor deposition to obtain a solar cell (FIG. 12 (h )).

When the IV characteristics under AM1.5 (100 mW / cm ² ) light irradiation of the thin film polycrystalline silicon solar cell on polyimide thus obtained were measured, the open area voltage was 0.57 V with a cell area of 6 cm ² . The short-circuit photocurrent was 32 mA / cm ² , the fill factor was 0.77, and an energy conversion efficiency of 14% was obtained.

  Further, the porous layer remaining on the peeled silicon wafer was also removed by etching in the same manner as described above to give a smooth surface (FIG. 12 (i)). A plurality of thin-film polycrystalline solar cells having a high-quality semiconductor layer were obtained by repeating the above-described steps using the reclaimed wafer thus obtained.

    The surface layer of the first single crystal Si substrate was anodized in an HF solution.

  The anodizing conditions were as follows.

Current density: 7 (mA · cm ⁻² )
Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
Time: 4 (min)
Porous Si thickness: 4.5 (μm)
further,
Current density: 30 (mA · cm ⁻² )
Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
Time: 1 (min)
Thickness of porous Si: ~ 4 (μm)
By this anodization, the porosity of the porous Si layer by 30 (mA · cm ⁻² ) was increased, and a structurally fragile layer was formed.

  This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. By this oxidation, the inner walls of the porous Si holes were covered with a thermal oxide film.

  This heat treatment is performed in advance at a low temperature to form a thin oxide film on the side walls of the pores (single crystallinity as a porous layer is maintained) to prevent the rearrangement of the pores. It is for stabilizing.

Next, the outermost surface of the substrate on which the porous layer was formed was immersed in a 1.25% HF solution to remove the thin oxide film formed on the outermost surface. The substrate thus obtained was subjected to heat treatment for 1 minute under the conditions of 1050 ° C. and 760 Torr while flowing H ₂ at 230 l / min, and further for 5 minutes under the condition of adding 50 sccm of SiH ₄ .

  This is to form a silicon film at a very slow rate by flowing a small amount of source gas containing silicon atoms into the film forming chamber and to block the outermost surface of the pores of the porous silicon layer. is there.

  Next, single-crystal Si was epitaxially grown on the porous Si by 0.3 μm by CVD (Chemical Vapor Deposition). The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 80 Torr
Temperature: 950 ° C
Growth rate: 0.3 μm / min
Further, a 200 nm SiO ₂ layer was formed on the surface of the epitaxial Si layer by thermal oxidation.

After a film was applied to the SiO ₂ surface in the same manner as in Example 8, the film was peeled off from the wafer.

As a result, the wafer was separated from the lower brittle porous Si as a boundary, and the SiO ₂ layer, the epitaxial layer, and the porous Si layer remained on the film side.

  Subsequently, the subsequent steps were performed in the same manner as in Example 8.

  As a result, a single crystal Si layer having a thickness of 0.2 μm was formed on the Si oxide film. When the film thickness of the formed single crystal Si layer was measured at 100 points over the entire surface, the uniformity of the film thickness was 201 nm ± 6 nm.

  Further, heat treatment was performed at 1100 ° C. in hydrogen for 1 hour. When the surface roughness was evaluated with an atomic force microscope, the mean square roughness in a 5 μm square region was about 0.2 nm, which was equivalent to a commercially available Si wafer.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  The present invention is applied to a semiconductor integrated circuit, a semiconductor element such as a solar cell, a semiconductor laser, and a light emitting diode, and a method for manufacturing a semiconductor member for forming an SOI substrate.

It is typical sectional drawing for demonstrating the method of this invention. It is typical sectional drawing for demonstrating the method of this invention. It is typical sectional drawing for demonstrating the method of this invention. It is typical sectional drawing for demonstrating the method of this invention. It is typical sectional drawing for demonstrating the method of this invention. It is typical sectional drawing for demonstrating the method of this invention. It is typical sectional drawing for demonstrating the method of this invention. It is typical sectional drawing for demonstrating the method of this invention. It is typical sectional drawing for demonstrating the method of this invention. It is typical sectional drawing for demonstrating the method of this invention. It is the schematic sectional drawing which showed the structure of the solar cell obtained by applying the method of this invention to the manufacturing method of a solar cell. It is explanatory drawing in the case of applying the method of this invention to the manufacturing method of a solar cell. It is explanatory drawing in the case of applying the method of this invention to the manufacturing method of a solar cell. It is the schematic sectional drawing which showed the structure of the GaAs / AlGaAs thin film solar cell formed on the porous layer by the method demonstrated in FIG. It is explanatory drawing at the time of applying this invention to the manufacturing method of a solar cell. It is explanatory drawing at the time of applying this invention to the manufacturing method of a solar cell. It is explanatory drawing for demonstrating the conventional method. It is explanatory drawing for demonstrating the conventional method.

Explanation of symbols

101, 201, 301, 401, 501, 601, 701, 801 Si substrate 102, 202, 402, 802, 803 Porous layer 103, 204, 304, 405, 505, 606, 705, 808, 809 Thin film 203, 303,403,503,603,604,702,804,805 Non-porous layer (non-porous thin film)
302, 502, 602, 704 Ion implantation layer 404, 504, 605, 703, 806, 807 Insulating layer 406, 506, 607, 706, 810, 811 Second substrate 1201, 1301, 1401, 1501, 1601 Crystal substrate 1202 , 1202a, 1202b, 1302, 1302a, 1302b, 1402, 1502, 1502a, 1502b, 1602, 1602a, 1602b porous layer 1103, 1203, 1303, 1503, 1603 active layer 1104, 1204, 1304, 1504, 1604 p ⁺ layer (Or n ⁺ layer)
1106, 1206, 1306, 1506, 1606 n ⁺ layer (or p ⁺ layer)
1107, 1207, 1307, 1508, 1611 Antireflection layer (transparent conductive layer)
1108, 1208, 1308, 1509, 1612 Current collecting electrode 1109, 1209, 1309, 1510, 1608 Back electrode 1403 n ⁺ GaAs
1404 n ⁺ Al _x Ga _1-x As
1405 n Al _0.37 Ga _0.63 As
1406 p Al _0.37 Ga _0.63 As
1407 p ⁺ Al _x Ga _1-x As
1408 p Al _0.37 Ga _0.63 As
1409 n ⁺ Al _x Ga _1-x As
1410 n Al _0.37 Ga _0.63 As
1411 n ⁺ Al _0.9 Ga _0.1 As
1412 nGaAs
1413 pGaAs
1506 Transparent film 1507 Adhesive layer 1606 UV curable film 1607 Adhesive layer

Claims (6)

A step of attaching a film on a first substrate configured to include a porous semiconductor layer and a non-porous semiconductor layer, and applying a force in a direction to peel the film from the first substrate to the film A step of separating the non-porous semiconductor layer from the first substrate in the porous semiconductor layer, and a step of bonding the separated non-porous semiconductor layer to the second substrate. A method for manufacturing a semiconductor member. The manufacturing method of the semiconductor member of Claim 1 which affixes the said film on a said 1st board | substrate through an adhesive agent. After the separation step, the nonporous semiconductor layer on the separated film is attached to another support member, the film on the nonporous semiconductor layer is removed, and the state is attached to the support member The method for manufacturing a semiconductor member according to claim 1, wherein a bonding step with the second substrate is performed. The non-porous semiconductor layer that is exposed by removing the porous layer remaining on the surface of the non-porous semiconductor layer on the separated film is bonded to the support member. A method for manufacturing a semiconductor member. The method for producing a semiconductor member according to claim 3, wherein the porous member remaining on the surface of the non-porous semiconductor layer on the separated film is bonded to the support member. The method for manufacturing a semiconductor member according to claim 3, wherein the support member is removed after the non-porous semiconductor layer is bonded to the second substrate.