JP2005101446A - Manufacturing method of semiconductor wafer - Google Patents

Abstract

The present invention provides a method for manufacturing a semiconductor wafer that has a small polishing allowance, can reduce processing time, and can achieve high planarization.
The method for manufacturing a semiconductor wafer includes a step of grinding a wafer after slicing, a step of forming an oxide film on the ground wafer, and removing only the oxide film formed on the surface to remove the surface of the wafer. An oxide film selective polishing step to be exposed; and a step of polishing the exposed wafer surface.
[Selection] Figure 2

Description

  The present invention relates to a method for manufacturing a semiconductor wafer, and more particularly to a method for manufacturing a semiconductor wafer having a polishing step with a reduced polishing allowance.

  In general, a silicon wafer manufacturing method includes a slicing step of slicing a silicon single crystal ingot pulled up by the Czochralski method to cut out a disk-shaped wafer, and grinding the both surfaces of the sliced wafer to flatten the wafer. It comprises a combination of a lapping process, an etching process for removing the work-affected layer generated in these processing processes by etching, and a polishing process for mirror polishing one side of the etched wafer.

On the other hand, in recent years, device manufacturers are rapidly increasing the integration density and speed, and there is a strong demand for improvement in wafer flatness. However, each conventional process has a number of problems. First, in the first slicing process, the ingot is cut and cut with an inner peripheral blade or a wire saw, but due to slight differences in fracture cross-sectional stress during slicing, surface roughness, waviness, warpage, and excessively damaged layers are generated. I will let you. In the subsequent lapping process, the roughness of the wafer is corrected, but the potential warpage generated in the slicing process cannot be completely corrected. In the wrapping process, the work-affected layer generated in the slicing process is removed. For the purpose of improving the processing efficiency, abrasive grains having a large particle size mainly composed of Al ₂ O ₃ , ZrO ₂ , and SiO ₂ are used. As a result, an altered layer peculiar to lapping occurs. This is the next etching step, and it reacts violently during etching to generate a certain type of bubbles, resulting in variations in the etching rate within the wafer surface, and in the case of acid etching, a specific undulation occurs.

  In the polishing process, it is generally possible to easily flatten a convex portion as viewed from the periphery. However, as shown in FIG. 7, in the case of a concave shape, on the contrary, it greatly exceeds the depth and is approximately twice the depth. Therefore, the level of planarization is inferior to that of the same convex shape. This is because the polishing cloth is an elastic body, and the polishing cloth is brought into contact with the concave shape to perform polishing. For example, when a grinding process is performed before polishing for high planarization, a structure in which streak-like grooves (streaks) are formed in a part of a flat surface having a small roughness in the running direction of the grindstone. Since the polishing cloth is an elastic body, when the polishing cloth hits the side wall and the bottom wall of the groove, polishing proceeds and the groove becomes deep and wide. When the groove becomes wider, the polishing cloth is more likely to hit the inside of the groove, so that the polishing speed inside the groove becomes faster. Thus, in order to completely remove the groove, a large amount of polishing allowance reaching approximately twice the depth of the groove is required, and when the polishing allowance is small, it remains in the state of a pit or the like.

  The increase in the polishing allowance for the purpose of complete removal of the groove causes deterioration of the flatness of the outer peripheral portion of the wafer in addition to the decrease in productivity, and therefore the limitation of the minimum allowance is a great obstacle to high planarization.

  In Patent Document 1, as a method for manufacturing a semiconductor wafer having a small nanotopology, a high flatness, and a small polishing amount in the mirror polishing process of the wafer surface, the semiconductor wafer after lapping is alkali-etched, and then a half barrel A method has been proposed in which a low-damage grinding wheel is used to grind the surface of a body wafer with a low-damage grinding wheel, then the irregularities formed on the back surface of the wafer are polished, and finally the surface is mirror-polished. . However, even if low damage grinding is performed using a low-damage grinding wheel after alkaline etching, not only a few grinding marks remain, but a polishing amount greater than that depth is required, so the polishing amount is reduced. There were limits.

Further, in Patent Document 2, a semiconductor wafer after lapping is etched with a primary etching solution, then the surface of the half barrel wafer is ground, and further, lighter than the primary etching with a secondary etching solution. A method of etching and polishing the surface of a semiconductor wafer has been proposed. However, since light etching with a secondary etching solution after surface grinding uses a NaOH solution with a weight concentration of 45 wt% as described in paragraph “0018”, the striations in grinding are deeply digged, and the grinding In order to remove the streak, the polishing amount during mirror polishing increases.
JP 2001-223187 A (paragraphs [0017] to [0020], FIG. 1) JP 2003-45836 A (paragraph [0018], FIG. 1)

  The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor wafer that has a small polishing allowance and can shorten the processing time during mirror polishing and can achieve high planarization.

  In order to achieve the above object, according to one aspect of the present invention, a step of grinding both surfaces of a wafer after slicing, a step of forming an oxide film on the ground wafer, and only the formed oxide film are provided. There is provided a method of manufacturing a semiconductor wafer, comprising: an oxide film selective polishing step for removing and exposing the wafer surface; and a step of polishing the exposed wafer surface. As a result, a semiconductor wafer manufacturing method is realized in which the polishing allowance is small, the processing time during mirror polishing can be shortened, and high planarization can be achieved.

  According to the method for manufacturing a semiconductor wafer according to the present invention, it is possible to provide a method for manufacturing a semiconductor wafer in which the polishing allowance is small, the processing time at the time of mirror polishing can be shortened, and high planarization can be achieved.

  Hereinafter, an embodiment of a wafer manufacturing method according to the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a process flow diagram of a wafer manufacturing method according to the present invention.

  As shown in FIG. 1, the wafer manufacturing method according to the present invention is performed by the following steps.

  A single crystal ingot pulled up by the Czochralski method is sliced into a disk-shaped wafer such as a silicon wafer (S1), and both sides of the sliced wafer are ground using a grinding apparatus using a grinding wheel (S2). .

  In the slicing step, a disk-shaped silicon wafer is cut out from an ingot of a single crystal such as a silicon single crystal using a cutting means such as a wire saw or an inner peripheral blade. However, in this step, a large undulation corresponding to the shape of the cutting edge of the cutting means is generated on the cut surface of the wafer, and a work-affected layer is formed from the wafer surface to a depth of about 25 μm to 50 μm.

  In the grinding step, both sides are ground using a single-side grinding apparatus. This single-side grinding apparatus has a grindstone that rotates at a high speed by a drive motor, and a rotary table that rotates at a high speed by a drive motor. Further, the rotary table is provided with a base plate made of a porous material such as ceramic, and pressure reducing means. The base plate is sucked and operated, and the wafer is sucked and fixed on the base plate at the time of grinding, and the surface of the silicon wafer is pressed against the grindstone to grind the surface undulation and the depth beyond the work-affected layer entered in the slicing process.

  Next, the ground wafer is etched (S3).

The etching step is performed by surface treatment (etching) of the silicon wafer by a chemical corrosion method, and it is preferable to use an alkaline solution containing KOH or NaOH for etching the silicon wafer. The present etching process is not an essential step in the method for manufacturing a semiconductor wafer according to the present invention, for _example, HF, may be used mixed acid of HNO _3, CH ₃ COOH. At this point, grooves (pits) exist on the surface of the wafer.

  Next, an oxide film is formed on the ground wafer (S4).

  For example, using an atmospheric pressure thermal oxidizer, supplying oxygen or water molecules to a wafer in a reaction tube heated near atmospheric pressure, a thermal oxidation reaction is performed at a high temperature to form an oxide film on the surface of the wafer (see FIG. 2 (a)). The thickness of the oxide film needs to be about 100 nm. At this time, the oxide film is buried in the portion where the groove exists, and the surface after the oxide film is formed has a concave shape.

  Next, only the oxide film formed on the surface is removed, and the oxide film that exposes the surface is selectively polished (S5).

  A wafer is affixed to the mounting plate and fixed, and the slurry containing abrasive grains is supplied to a hard polishing cloth that is affixed to the surface plate and has little penetration into the grooves of the polishing cloth, and is processed by high-speed polishing, and formed on the surface of the wafer. The remaining oxide film is polished leaving only the oxide film embedded in the groove (FIG. 2B). Polishing is completed with the oxide film remaining in the flat portion and the oxide film remaining only in the groove. As the polishing agent, a CeO system having a small chemical action is preferable, and in order to minimize the influence on the silicon surface, it is necessary to reduce the polishing amount of silicon as much as possible. Here, since the polishing rate ratio differs between the oxide film and silicon, the end point of the polishing of the oxide film can be easily detected by monitoring the load current on the surface plate or bed, etc., and the control of the oxide film polishing process is ensured Yes.

  Next, the exposed surface is polished (S6).

  This polishing step is normal polishing, and general colloidal silica is used as the polishing slurry for silicon. The polishing rate of the oxide film is about 1/5 to 1/10 of that of silicon, and the polishing rate of the oxide film is very slow. Therefore, when silicon around the oxide film remaining in the groove is polished, the oxide film portion is A protrusion is formed, and the polishing pressure locally increases in this portion. With this pressure increase, the polishing rate of the oxide film increases, the polishing rate becomes equal to that of silicon, and polishing proceeds in this state (FIGS. 2C and 2D).

  When the oxide film disappears, the portion has a convex shape from the periphery, but can be flattened with a polishing amount substantially the same as the height of the convex portion (FIG. 2E).

  According to the present embodiment, by polishing at a depth (polishing allowance) similar to the depth of the groove, the silicon wafer can be flattened, the polishing allowance is small, and the processing time during mirror polishing can be shortened. Therefore, high flatness can be achieved.

  Another embodiment of the wafer manufacturing method according to the present invention will be described.

  The manufacturing method in the case where the groove formed in the silicon wafer is large is performed by processes as shown in FIGS.

  For example, an oxide film is formed on a ground wafer (FIG. 3A). In this case, the oxidation time is increased in the oxidation step, and it is difficult to fill all the grooves with an oxide film. However, the polishing amount shown in FIGS. 3B to 3D is almost equal to the depth of the grooves. Compared with the conventional method that requires a polishing amount of about twice or more, the polishing amount is almost halved. The manufacturing process has two stages, an oxide film process and a normal polishing process, but the method of this embodiment can reduce the polishing time for normal polishing because the machining allowance is about half as described above. Since the oxide film polishing process is performed in this shortened time, the total manufacturing process time does not increase.

  The effect of the semiconductor wafer manufacturing method according to the present invention was confirmed using a 200 mm diameter silicon wafer.

  When both surfaces of the lapped silicon wafer were ground and the depth of the grinding streak was measured with a surface roughness meter, the depth was about 1.9 μm as shown in FIG. Hereinafter, when it is assumed that the depth of the groove is 2 μm, the allowance is required to be 4.0 μm or more in the case of only general polishing performed normally.

  Table 1 shows the polishing rates of the oxide film and the silicon layer under the polishing conditions of the oxide film selective polishing or normal polishing, respectively. Under oxide film selective polishing conditions, the oxide film has a higher polishing rate than the silicon layer, and under normal polishing conditions, the silicon layer has a higher polishing speed.

Example FIG. 5 shows the site flatness (25 μm □) of a sample obtained by the process flow shown in FIG. 2 using the silicon wafer. The polishing allowance for the silicon layer is 2.0 μm.

Conventional Example FIG. 6 shows the site flatness (25 μm □) of a sample obtained by normal polishing only using the above silicon wafer. The polishing allowance for the silicon layer is 4.0 μm.

  Comparing the lower three-stage outer peripheral sites in FIGS. 5 and 6 respectively, it can be confirmed that there are four sites with improved flatness of about 0.02 μm compared to the conventional example.

As described above, by using the present invention, the machining allowance can be reduced and the flatness of the outer peripheral portion is improved.

The process flow figure of one Embodiment of the manufacturing method of the semiconductor wafer concerning this invention. The conceptual diagram illustrating the process flow of one Embodiment of the manufacturing method of the semiconductor wafer concerning this invention. The conceptual diagram illustrating the process flow of other embodiment of the manufacturing method of the semiconductor wafer concerning this invention. (A) is the uneven | corrugated state figure of the silicon wafer surface after the etching of the Example of the manufacturing method of the semiconductor wafer concerning this invention, (b) is the sectional drawing. The measurement result figure of the site flatness of the wafer after grinding | polishing of the Example of the manufacturing method of the semiconductor wafer concerning this invention. The measurement result figure of the site flatness of the wafer after grinding | polishing of the Example of the manufacturing method of the conventional semiconductor wafer. The general conceptual diagram at the time of grinding | polishing in the manufacturing method of the conventional semiconductor wafer.

Claims (1)

A step of grinding the wafer after slicing, a step of forming an oxide film on the ground wafer, an oxide film selective polishing step of removing only the formed oxide film to expose the surface of the wafer, and the exposed wafer A method for producing a semiconductor wafer, comprising a step of polishing the surface of the semiconductor wafer.

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