JP2005086153A - Semiconductor device design method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce steps of timing adjustment in a semiconductor integrated circuit of a standard cell method. <P>SOLUTION: During automatic arrangement and wiring (20), a wiring delay cell, wiring delay dummy wiring, and a strap power supply/ground wiring are arranged. After timing is examined, between cells subjected to timing adjustment, a wiring delay cell (34) is connected according to a delay time reference table for the wiring delay cell, wiring-delay dummy wiring (32) is connected according to a delay time reference table for wiring, and rewiring is performed by arranging and connecting bypass wiring (29) on the strap power supply/ground wiring. Thus, it is possible to achieve more accurate timing adjustment and reduce the steps of automatic timing adjustment. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device design method capable of performing timing adjustment in a standard cell type semiconductor integrated circuit.

  In recent years, in the design of a fine process LSI whose manufacturing period is becoming longer, the masks for the transistor formation process and the wiring layer process tend to be ordered separately in order to shorten the manufacturing period and the design verification time. Therefore, the designer needs to perform final timing adjustment by adjusting the wiring length in a state where the transistor arrangement is fixed. This will be described with reference to FIG. FIG. 12A shows a partial flow in the semiconductor manufacturing process, and FIG. 12B shows a layout of the semiconductor device after automatic placement and routing. In FIG. 12, 16 is a transistor formation process, 17 is a wiring layer process, 12 is a timing adjustment target cell, 13 is a cell row in which the timing adjustment target cell 12 is arranged, 14 is an inter-cell wiring of the timing adjustment target cell 12, 18 Is a cell group that is not subject to timing adjustment.

  As shown in FIG. 12A, since the wiring layer process 17 is performed after the transistor formation process 16 in the semiconductor manufacturing process, the transistor is automatically formed and routed based on, for example, the layout shown in FIG. The mask used in the forming process 16 is ordered. Thereafter, timing adjustment is performed by adjusting the wiring length by correcting (changing) the wiring, and then a mask used in the wiring layer process 17 is ordered. Thus, the masks for the transistor formation process 16 and the wiring layer process 17 tend to be ordered separately, and the designer needs to carry out final timing adjustment by adjusting the wiring length while the transistor arrangement is fixed. is there.

  In addition, with the recent miniaturization of semiconductor processes, securing of design margins for process variations and verification of signal integrity (signal integrity) such as crosstalk have become more important, but the scale of semiconductor devices has increased. As a result, the number of timing adjustments after physical design is steadily increasing. Conventionally, these increasing timing adjustment points are adjusted manually by rewiring the timing error location as shown in the flow chart of FIG. 13, and the accuracy is not out of the cut and try area. The need for re-correction is also frequent, and the number of steps for repeating the timing verification process from manual wiring correction is increasing.

  FIG. 13 is a flowchart of timing adjustment in the conventional semiconductor device design method. In FIG. 13, 20 is an automatic placement and routing process, 21 is a delay information extraction process, 22 is a timing verification process, 23 is a timing error presence / absence determination process, 24 is a correction target timing error extraction process, and 25 is a manual wiring correction process.

  First, physical design of a semiconductor device is performed by automatic placement and routing (automatic placement and routing step 20), and delay information is extracted (delay information extraction step 21). Thereafter, timing verification is performed (timing verification step 22), the presence / absence of a timing error is determined (timing error presence / absence determination step 23), and the process ends if there is no error. If there is an error, the error is extracted (correction target timing error extraction step 24). The designer performs manual wiring correction on the extracted error location (manual wiring correction process 25), and then returns to the timing verification process 22 to perform timing verification again.

  FIG. 14 is a diagram showing an example of timing adjustment in the conventional method. In FIG. 14, 12 is a timing adjustment target cell, 14 is an inter-cell wiring (wiring that is automatically arranged and wired) of the timing adjustment target cell 12, and 19 is a wiring showing a manual wiring correction example.

Patent Document 1 discloses a method for improving clock skew of a semiconductor integrated circuit.
Japanese Patent Laid-Open No. 2001-34647 (page 1-6, FIG. 1)

However, like the conventional method above, the manual wiring correction method based on the experience of the designer is used in determining the delay time and the wiring length.
How long the wiring length is affected and how much the delay time is affected. It is difficult to predict how much the delay time is affected by the wiring layer even if the wiring length is the same until the timing error is eliminated. The manual wiring correction step 25 to the timing verification step 22 shown in FIG.

  An object of the present invention is to provide a semiconductor device design method capable of reducing the man-hours for timing adjustment in a standard cell type semiconductor integrated circuit.

  The present invention includes a step of placing a plurality of standard cell type functional cells by automatic placement and routing and physically designing a semiconductor device by wiring, a step of performing timing verification of the physically designed semiconductor device, and timing verification. As a result, if there is a timing error, the timing error can be resolved by extracting the timing error that can be resolved by changing the wiring length between functional cells, and rewiring to eliminate the timing error. Until it is done, the semiconductor device design method returns to the step of performing the timing verification of the semiconductor device after the step of performing rewiring, and has the following characteristics.

  The method of designing a semiconductor device according to claim 1 includes two pins each serving as an input pin and an output pin, and an internal wiring that connects the two pins, and the wiring lengths of the internal wirings are different from each other. In response to a plurality of standard cell type wiring delay cells having a specific delay time, a wiring delay cell delay time reference table describing each delay time is prepared in advance, and wiring delay is performed in the process of physically designing the semiconductor device. In the process of placing a cell in an area where no functional cell is placed and performing rewiring, a wiring delay cell for eliminating a timing error is selected based on the delay time reference table for the wiring delay cell. Rewiring is performed so that wiring delay cells are connected between functional cells having timing errors.

  According to the design method of the first aspect, wiring delay cells composed of a plurality of cell lineups having inherent delay times according to the wiring length are arranged, and timing is determined based on the delay time reference table for wiring delay cells. By realizing the adjustment by rewiring by connecting wiring delay cells, highly accurate timing adjustment can be performed while reducing man-hours, and short TAT can be realized.

  3. The semiconductor device design method according to claim 2, wherein a delay time for wiring is described for each of a plurality of wirings having a specific delay time according to a wiring width and a wiring length by each process or each wiring layer. In the process of preparing the reference table in advance and placing the dummy wiring in the process of physically designing the semiconductor device, the process of performing the rewiring is a dummy wiring for eliminating the timing error based on the wiring delay time reference table. Rewiring is performed so that is part of the wiring between functional cells having a timing error.

  According to the design method of the second aspect, dummy wiring is arranged at the time of physical design of the semiconductor device, and timing adjustment is realized by rewiring by connecting the dummy wiring based on the wiring delay time reference table. Precision timing adjustment can be performed while reducing man-hours, and short TAT can be realized.

  4. The semiconductor device design method according to claim 3, wherein the delay time for wiring describes each delay time for a plurality of wirings each having a specific delay time according to a wiring width and a wiring length by each process or each wiring layer. In the process of preparing the reference table in advance and physically designing the semiconductor device, the strap power supply / ground wiring is arranged and the rewiring process is performed in such a manner that the wiring connecting the functional cells having the timing error is the strap power supply. / When the wiring is arranged across the ground wiring, the bypass wiring for eliminating the timing error based on the wiring delay time reference table is arranged on the strap power supply / ground wiring, and the bypass wiring has a timing error. Rewiring is performed so as to be part of wiring between functional cells.

  According to the design method of the third aspect, the strap power supply / ground wiring is arranged at the time of physical design of the semiconductor device, and the timing adjustment is provided on the strap power supply / ground wiring based on the wiring delay time reference table. By realizing by rewiring, highly accurate timing adjustment can be performed while reducing man-hours, and short TAT can be realized.

  5. The semiconductor device design method according to claim 4, wherein the delay time for wiring describes each delay time for a plurality of wirings each having a unique delay time according to a wiring width and a wiring length for each process or wiring layer. A step of preparing a reference table in advance and physically designing a semiconductor device, and arranging a plurality of dummy wires having a predetermined unit delay and having a predetermined unit delay based on the wiring delay time reference table, and performing rewiring Is characterized in that the rewiring is performed so that the dummy wiring for eliminating the timing error becomes a part of the wiring between the functional cells in which the timing error exists based on the wiring delay time reference table.

  According to the design method of claim 4, a plurality of dummy wirings having a predetermined length are arranged at the time of physical design of the semiconductor device, and timing adjustment is realized by rewiring by connecting the dummy wirings based on the wiring delay time reference table. Thus, highly accurate timing adjustment can be performed while reducing the number of man-hours, and a short TAT can be realized.

  The semiconductor device design method according to claim 5 is the semiconductor device design method according to claim 4, comprising two pins each serving as an input pin and an output pin, and an internal wiring connecting between the two pins, respectively. For a plurality of standard cell type wiring delay cells that have different internal wiring lengths and have specific delay times according to the respective wiring lengths, a delay time reference table for wiring delay cells describing each delay time is prepared in advance. In the process of physically designing the semiconductor device, the wiring delay cell is placed in an area where the functional cell is not arranged, and the process of performing the rewiring has dummy wiring between and in the vicinity of the functional cell where the timing error exists. If not, select the wiring delay cell to eliminate the timing error based on the delay time reference table for the wiring delay cell. Wherein the-option the wiring delay cell is carried out rewiring to be connected between the functional cells in the presence of timing errors.

  According to the design method of the fifth aspect, in addition to the operational effect of the fourth aspect, the same operational effect as that of the first aspect can be obtained.

  The semiconductor device design method according to claim 6 is the semiconductor device design method according to claim 4 or 5, wherein the strap power supply / ground wiring is arranged and rewiring is performed in the physical design process of the semiconductor device. In this process, when the wiring connecting the functional cells where the timing error exists is arranged across the strap power supply / ground wiring, a bypass wiring for eliminating the timing error based on the wiring delay time reference table is provided. Rewiring is performed so that the bypass wiring is a part of the wiring between functional cells in which a timing error exists and is arranged on the strap power supply / ground wiring.

  According to the design method of the sixth aspect, in addition to the operational effect of the fourth or fifth aspect, the same operational effect as that of the third aspect can be obtained.

  The semiconductor device design method according to claim 7 is the semiconductor device design method according to claim 1, wherein each of the plurality of wirings has a specific delay time according to a wiring width and a wiring length by each process or each wiring layer. A wiring delay time reference table describing each delay time is prepared in advance, and in the process of physically designing the semiconductor device, strap power supply / ground wiring is arranged and rewiring is performed in the timing error process. When wiring that connects existing functional cells is arranged across the strap power supply / ground wiring, a bypass wiring is provided on the strap power supply / ground wiring to eliminate timing errors based on the wiring delay time reference table. Reroute so that the detour wiring is part of the wiring between functional cells where there is a timing error. And wherein the Hodokosuru.

  According to the designing method of the seventh aspect, in addition to the operational effect of the first aspect, the same operational effect as that of the third aspect can be obtained.

  The semiconductor device design method according to claim 8 is the semiconductor device design method according to claim 1, 5 or 7, wherein the wiring delay cell has a shield wiring for ensuring the reliability of a signal passing through the internal wiring. It is characterized by that.

  According to the design method of the seventh aspect, in addition to the operational effect of the first, fifth or seventh aspect, the wiring delay cell has the shield wiring, so that a signal integrity countermeasure can be taken.

  According to a ninth aspect of the present invention, there is provided a semiconductor device design apparatus comprising means for performing each step in the semiconductor device design method according to any one of the first to eighth aspects.

  According to the design apparatus of the ninth aspect, highly accurate timing adjustment can be performed while reducing man-hours, and a short TAT can be realized.

  As described above, according to the present invention, in timing adjustment in a standard cell type semiconductor integrated circuit, wiring delay cells, dummy wirings, strap power supply / ground wirings are arranged at the time of physical design of a semiconductor device, and timing adjustment is performed after timing verification. By performing rewiring between cells by connecting wiring delay cells based on the delay time reference table for wiring delay cells, connecting dummy wiring based on the delay time reference table for wiring, and placing and connecting bypass wiring Adjustments can be made with high accuracy, and man-hours due to automatic timing adjustment can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
The flow of the method for designing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIG.

  FIG. 1 is a diagram showing an example of a wiring delay cell that is indispensable for carrying out the embodiment of the present invention.

  In this wiring delay cell, VDD wiring (power wiring) 5 and VSS wiring (ground wiring) 6 are wired in accordance with the cell height of the standard cell series, and no transistor is formed in the cell. Pins 7 and 8 serving as outputs are provided, and the pins 7 and 8 are connected by wiring of a predetermined unit delay based on sheet resistance calculated by process, wiring layer, and shape. It has a shield wiring 9 that is wired along the connection on both sides of the connection between the pin 7 and the pin 8 and that is connected to the VSS wiring 6 and grounded, and has a configuration that takes signal integrity measures into consideration. is there.

  In this embodiment, such wiring delay cells are lined up and prepared for each delay time, and are automatically arranged in an empty area of a normal cell during physical design of a semiconductor device.

  Therefore, as shown in FIG. 2A, a reference table in which the delay times are associated with each other for a plurality of wiring delay cells with different delay times arranged in a lineup (step 1), and this table is converted into a database. deep. The database is a reference table database 2, and an example of the description content is shown in FIG. In the reference table database 2, the delay time can be referred to for each wiring delay cell.

  The flow of this embodiment will be described with reference to FIG. 13. First, physical design of a semiconductor device is performed by automatic placement and routing (automatic placement and routing step 20). At the same time, in the present embodiment, the wiring delay cells are also automatically arranged in a vacant area where the normal cells (logic cells having transistors formed in the cells) are not arranged.

  Then, after delay information is extracted (delay information extraction step 21), timing verification is performed (timing verification step 22), the presence / absence of a timing error is determined (timing error presence / absence determination step 23), and if there is no error, the process ends. To do. If there is an error, the error is extracted (correction target timing error extraction step 24).

  Next, the designer performs manual wiring correction on the error part extracted in step 24 (manual wiring correction step 25). In performing this manual wiring correction, in the present embodiment, the wiring delay cell reference table database 2 is used to eliminate the timing error while referring to the unit delay of each wiring delay cell arranged in the semiconductor device. Rewire to. An example of this timing adjustment is shown in FIG. In FIG. 8, 11 is a layout block, 12 is a timing adjustment target cell, 14 is a wiring between normal cells 12 and 12 when automatic placement and routing is performed, and 38 is an inter-cell wiring 14 cut by rewiring in manual wiring correction. 40 is a wiring delay cell, and 41 is a wiring re-wired by manual wiring correction.

  Hereafter, each process 20-25 in this Embodiment is demonstrated a little in detail.

  In the automatic placement and routing step 20, the semiconductor layout tool performs routing according to the standard cell placement and netlist connection information based on the placement and routing algorithm of the tool. At this time, the wiring delay cells arranged at the same time are randomly arranged by the shotgun arrangement of the layout tool based on the cell list created by the designer.

  In the delay information extraction step 21, the delay information extraction tool uses the sheet resistance, contact resistance, wiring board capacity, and inter-wiring capacity for each wiring layer modeled for each semiconductor process to determine the wiring length of the physical layout, contact The delay is calculated after extracting the wiring capacity from the number, the parallel wiring length of the wiring, the wiring shape, and the like.

  In the timing verification step 22, the static timing analysis tool calculates the delay of the combinational circuit between the flip-flops based on the delay information calculated in the step 21, and the large / small / etc. And the information is output.

  In the timing error presence / absence determination step 23, the designer checks the operating frequency, the combinational circuit delay time between the flip-flops, and the specification timing rules (multipath, false path, etc.) based on the information output in step 22. Whether or not there is a timing error is determined. Here, it is determined whether or not there is a timing error that can be corrected by correcting the wiring length. Therefore, in the case of a timing error that cannot be corrected by correcting the wiring length, the processing is terminated assuming that there is no error. The criteria for determining whether the error can be corrected by correcting the wiring length is, for example, that a delay exceeding 5% of the clock period of the flip-flop cannot be corrected, and a delay of 5% or less can be corrected. Can be set to

  In the correction target timing error extraction step 24, after the determination of the step 23 based on the output information of the step 22, information excluding the multipath and the false path (the cell in which the timing error has occurred, the instance name, and the interval between the cells) Path and delay time for each path).

  In the manual wiring correction process 25, the designer uses one or more wirings among the plurality of wiring delay cells arranged between the timing adjustment target cells 12 and 12 based on the timing error information output in the process 24. Select delay cell and rewire.

  As described above, according to the present embodiment, a plurality of wiring delay cells having different delay times are prepared in advance, and a reference table in which the respective delay times are associated with each other is generated. By connecting (rewiring) the wiring delay cell 40 having a delay time that eliminates the timing error, the wiring correction accuracy can be improved. From the manual wiring correction process 25 to the timing verification process 22. It is possible to reduce the number of repetitive processes, and to perform highly accurate timing adjustment while reducing man-hours, thereby realizing a short TAT.

  Note that the designer can arbitrarily select and rewire the wiring delay cell without creating a wiring delay cell reference table. In this case, however, it is necessary to select and reroute the wiring delay cell based on experience. As a result of repeated trial and error, the TAT becomes longer.

(Second Embodiment)
The flow of the method for designing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIG.

  In the present embodiment, wiring delay dummy wiring is applied during physical design of the semiconductor device. As shown in FIG. 3A, a reference table in which the wiring width / wiring length for each process or wiring layer is associated with the delay time is created (step 3), and this table is stored in a database. This database is a reference table database 4, and an example of the description content is shown in FIG. In such a reference table database 4, the delay time can be referred to by the shape (width / length) of the wiring in each process or each wiring layer. In FIG. 3B, a reference table in which the wiring width / wiring length for each wiring layer is associated with the delay time is created. However, a plurality of wiring layers are formed on the semiconductor substrate. Since each layer is formed by a predetermined process, a reference table in which wiring width / wiring length and delay time for each process are associated may be created. When different wiring layers are formed by the same process, it is possible to reduce the amount of data by creating a reference table in which wiring width / wiring length for each process is associated with delay time.

  Note that “by process” indicates a design rule, and “by wiring layer” indicates how many wiring layers are used from the transistor layer toward the vertical upward direction of the semiconductor substrate. The number of wiring layers that can be used varies depending on the process. In addition, the materials such as AL, Cu and their compounds, the film thickness, and the width that can be wired differ from layer to layer, and as a result, the sheet resistance of the wiring varies, affecting the delay time.

  Further, for example, in the reference table in the second embodiment as shown in FIG. 3B, the wiring width / wiring length for each process or wiring layer is associated with the delay time, and the wiring height (film thickness) is determined. Is not listed. This is because, for each process, the thickness of the wiring layer is uniquely determined, and the resistance value can be calculated by the sheet resistance. Therefore, the wiring height (film thickness) is not described in the reference table.

  The flow of this embodiment will be described with reference to FIG. 13. First, physical design of a semiconductor device is performed by automatic placement and routing (automatic placement and routing step 20). At the same time, in the present embodiment, a wiring delay dummy wiring is also arranged based on the reference table database 4. In this case, dummy wiring based on the delay table database 4 is applied to the gap between the main wirings conforming to the netlist description. At this time, the dummy wiring is wired based on the designation file describing the wiring length that realizes the delay time assumed to be necessary by the designer based on the delay table database 4. As a result, dummy wirings are wired in gaps that do not hinder actual wiring, and dummy wirings with random wiring layers, widths, lengths, and numbers are realized.

  Subsequently, as in the first embodiment, a delay information extraction step 21, a timing verification step 22, a timing error presence / absence determination step 23, and a correction target timing error extraction step 24 are performed.

  Next, the designer performs manual wiring correction on the error part extracted in step 24 (manual wiring correction step 25). In performing this manual wiring correction, in the present embodiment, the dummy wiring is selected and re-wired so as to eliminate the timing error while referring to the wiring delay dummy wiring reference table database 4.

  4A and 4B are schematic diagrams of the wiring delay dummy wiring inserted / rewired in the present embodiment. FIG. 4A is a layout wiring diagram in the automatic placement and routing process 20, and FIG. A wired layout diagram is shown. 12 is a timing adjustment target cell, 13 is a cell row in which the timing adjustment target cell 12 is arranged, 14 is an inter-cell wiring automatically arranged and wired, 15 is a wiring delay dummy wiring group arranged by automatic placement and wiring, and 38 is a cell A cut portion 39 of the interlevel wiring 14 indicates a wiring delay dummy wiring connection wiring. In the manual wiring correction process 25, the wiring delay dummy wiring (15) arranged in the automatic arrangement wiring process 20 is connected by the connection wiring 39, and the inter-cell wiring 14 is cut (cutting point 38) and re-wired.

  As described above, according to the present embodiment, a reference table in which the wiring width / wiring length for each process or wiring layer is associated with the delay time is created in advance, and between the cells 12 where the timing error occurs. In addition, by connecting (rewiring) the wiring delay dummy wiring so as to eliminate the timing error, it is possible to improve the accuracy of the wiring correction, and to reduce the repeated processing from the manual wiring correcting process 25 to the timing verification process 22. In addition, highly accurate timing adjustment can be performed while reducing man-hours, and short TAT can be realized.

(Third embodiment)
FIG. 5 is a flowchart showing the operation of the semiconductor integrated circuit design apparatus of this embodiment. 20 is an automatic placement and routing process, 21 is a delay information extraction process, 22 is a timing verification process, 23 is a timing error presence / absence determination process, 24 is a correction target timing error extraction process, 26 is a placement / wiring information extraction process of a corrected cell point, 27 Is a power strap presence / absence determination process, 28 is a wiring delay cell presence / absence determination process, 29 is a wiring extension process on the power strap, 30 is an error item remaining presence / absence determination process, 31 is a wiring delay dummy wiring presence / absence determination process, and 32 is a wiring delay dummy. A wiring extension process by wiring connection, 33 is a manual wiring correction process, and 34 is a wiring delay cell hunting / rewiring process.

  In the automatic placement and routing step 20, the semiconductor layout tool performs routing according to the standard cell placement and netlist connection information based on the placement and routing algorithm of the tool. At this time, a wiring delay cell and a wiring delay dummy wiring are also arranged. At this time, the wiring delay cells to be arranged are randomly arranged by the shotgun arrangement of the layout tool based on the cell list created by the designer. Further, dummy wiring based on a wiring delay table database (for example, database 4 in FIG. 3) is performed in the gap between the main wiring and the wiring delay cell arrangement conforming to the netlist description. At this time, the dummy wiring is wired based on a designation file that describes a line length that realizes a delay time assumed to be necessary by the designer. As a result, the wiring delay cell arrangement and the dummy wiring are applied to the gap that does not hinder the actual wiring, and the dummy wiring whose wiring layer, width, length, and number are random is realized.

  In the delay information extraction step 21, the delay information extraction tool uses the sheet resistance, contact resistance, wiring board capacity, and inter-wiring capacity for each wiring layer modeled for each semiconductor process to determine the wiring length of the physical layout, contact The delay is calculated after extracting the wiring capacity from the number, the parallel wiring length of the wiring, the wiring shape, and the like.

  In the timing verification step 22, the static timing analysis tool calculates the delay of the combinational circuit between the flip-flops based on the delay information calculated in the step 21, and the large / small / etc. And the information is output.

  In the timing error presence / absence determination step 23, the designer checks the operating frequency, the combinational circuit delay time between the flip-flops, and the specification timing rules (multipath, false path, etc.) based on the information output in step 22. Whether or not there is a timing error is determined. Here, it is determined whether or not there is a timing error that can be corrected by correcting the wiring length. Therefore, in the case of a timing error that cannot be corrected by correcting the wiring length, the processing is terminated assuming that there is no error. The criteria for determining whether the error can be corrected by correcting the wiring length is, for example, that a delay exceeding 5% of the clock period of the flip-flop cannot be corrected, and a delay of 5% or less can be corrected. Can be set to

  In the correction target timing error extraction step 24, after the determination of the step 23 based on the output information of the step 22, information excluding the multipath and the false path (the cell in which the timing error has occurred, the instance name, and the interval between the cells) Path and delay time for each path).

  In step 26, the placement and routing information (physical coordinates) of the timing correction target cell is calculated based on the timing error information output in step 24. This is automatically executed by a semiconductor layout tool.

  In step 27, it is determined whether or not a power supply strap method is used as the power supply method of the present LSI. In this step, the designer inputs parameters in a series of flows, and sets whether or not the power strap is used. At the same time, it is determined whether the power supply strap extends over the rectangular area formed at the cell placement origin between the timing correction target cells extracted in step 26. This is determined based on the cell position coordinates and the strap power supply / ground wiring coordinates. Further, the number (N) of correction targets is calculated in this step. At the same time, correction locations / numbers not subject to power supply strap correction are also calculated and held from the coordinates in step 26.

  In step 28, it is determined whether or not there is a wiring delay cell arranged in step 20 in the rectangular area formed at the origin of physical coordinates of the timing correction target cell extracted in step 26.

  In step 29, when the strap power supply is between the timing correction target cells in step 27, as shown in FIG. 6, the delay based on the reference table 4 on the strap power supply / ground and compensates for the timing error extracted in step 24. Wiring is executed with a wiring layer, a wiring width, and a wiring length to ensure time. Each time this correction is executed, 1 is subtracted from the correction target number (N) calculated in step 27. Correct until N = 0.

  In step 30, it is determined whether or not N = 0 in step 29.

  In step 31, whether or not a wiring delay dummy wiring exists in the rectangular area between the arrangement origins of the timing correction target cells is calculated from the physical coordinates of the power strap correction non-target information (correction location / number) in step 27.

  In step 32, if there is a wiring delay dummy wiring in step 31, the wiring delay dummy wiring is rerouted based on the delay reference table 4.

  In step 33, if there is no power supply strap between the timing correction target cell arrangements and no wiring delay cell, manual correction is performed based on the wiring layer, wiring width, and wiring length based on the delay reference table 4. .

  In step 34, when there is an arrangement delay cell in the vicinity of the arrangement of the timing correction target cell, the cell is hunted by the technique of Japanese Patent Laid-Open No. 2001-34647 (page 1-6, FIG. 1), Rewiring the hunted cells to correct timing.

  FIG. 6 is a diagram illustrating an example of processing in the power strap on-wire extension process 29. 11 is a layout block, 12 is a timing adjustment target cell, 14 is an inter-cell wiring that is automatically placed and routed, 36 is a strap power / ground wiring, 37 is an extension wiring performed in the wiring extension process 29, and 38 is an inter-cell wiring 14 Indicates the cutting point.

  In this wiring extension step 29, the extension wiring 37 is connected on the strap power supply / ground wiring 36, the inter-cell wiring 14 is cut (cutting point 38) and re-wired, thereby adjusting the timing by wiring extension and performing the timing margin. Is to secure. Here, in the standard cell arrangement region, one form of supplying power / ground to each cell is defined as a strap, and the strap power supply / ground wiring 36 has a wide wiring with respect to the minimum width wiring rule. In a form orthogonal to the internal power / ground line, the power / ground is wired in parallel in the standard cell placement area, and the power / ground is wired as a set in the standard cell placement area at almost equal positions.

  FIG. 7 is a diagram showing an example of the process of the wiring extension process 32 by connecting the wiring delay dummy wiring. 11 is a layout block, 12 is a timing adjustment target cell, 14 is an inter-cell wiring that is automatically placed and routed, 15 is a wiring delay dummy wiring group that is placed by automatic placement and routing, 36 is a strap power supply / ground wiring, and 38 is an inter-cell wiring A cut portion 39 of the wiring 14 indicates a wiring delay dummy wiring connection wiring.

  In this wiring extension process 32, the wiring delay dummy wiring (15) is connected by the connection wiring 39, the inter-cell wiring 14 is cut (cutting point 38) and re-wired, thereby adjusting the timing by wiring extension and performing the timing margin. Is to secure.

  FIG. 8 is a diagram showing an example of processing in the wiring delay cell hunting / rewiring process 34. 11 is a layout block, 12 is a timing adjustment target cell, 14 is an inter-cell wiring that is automatically placed and routed, 38 is a cut portion of the inter-cell wiring 14, 40 is a wiring delay cell, and 41 is a wiring delay cell connection wiring.

  In this wiring delay cell hunting / rewiring process 34, the wiring delay cell 40 is connected by the connection wiring 41, the inter-cell wiring 14 is cut (cutting point 38), and the wiring is rewired, thereby adjusting the timing and reducing the timing margin. It is to secure.

  As described above, according to the present embodiment, as shown in the flow of FIG. 5, steps 26 to 34 are provided instead of the manual wiring correction step 25 of FIG. 13, and the first and second steps are performed. Implementing wiring extension, connection, and rewiring with the delay time reference database 2 and 4 created in the embodiment as the basis of delay time-wiring correction amount calculation, reducing man-hours for highly accurate timing adjustment However, it is possible to implement a short TAT.

(Fourth embodiment)
FIG. 9 is a flowchart showing the operation of the semiconductor integrated circuit design apparatus of this embodiment.

  In the automatic placement and routing step 20, the semiconductor layout tool performs routing according to the standard cell placement and netlist connection information based on the placement and routing algorithm of the tool. At this time, a wiring delay dummy wiring is also arranged. In this case, dummy wiring based on a wiring delay table database (for example, database 4 in FIG. 3) is performed in the gap between the main wirings conforming to the netlist description. At this time, the dummy wiring is wired based on a designation file that describes a line length that realizes a delay time assumed to be necessary by the designer. As a result, dummy wirings are provided for gaps that do not hinder actual wiring, and dummy wirings with random wiring layers, widths, lengths, and numbers are realized. In the step 20 in the present embodiment, unlike the third embodiment, no wiring delay cell is disposed.

  Steps 21, 22, 23, 24, and 26 are the same as those in the third embodiment.

  In step 27, it is determined whether or not a power supply strap method is used as the power supply method of the present LSI. In this step, the designer inputs parameters in a series of flows, and sets whether or not the power strap is used. At the same time, it is determined whether the power supply strap extends over the rectangular area formed at the cell placement origin between the timing correction target cells extracted in step 26. This is determined based on the cell position coordinates and the strap power supply / ground wiring coordinates. Further, the number (N) of correction targets is calculated in this step. At the same time, correction locations / numbers not subject to power supply strap correction are also calculated and held from the coordinates in step 26 (used in step 32).

  In step 29, when the strap power supply is between the timing correction target cells in step 27, as shown in FIG. 6, the delay based on the reference table 4 on the strap power supply / ground and compensates for the timing error extracted in step 24. Wiring is executed with a wiring layer, a wiring width, and a wiring length to ensure time. Each time this correction is executed, 1 is subtracted from the correction target number (N) calculated in step 27. Correct until N = 0.

  In step 30, it is determined whether or not N = 0 in step 29. If N = 0, the process returns to step 22. If N ≠ 0, the process proceeds to step 31. In step 31, a wiring delay dummy is set in step 27 from the physical coordinates of the power strap correction non-target information (correction location / number) to the rectangular area between the timing correction target cell placement origins. It is calculated whether or not the wiring exists. In step 32, if there is a wiring delay dummy wiring in step 31, the wiring delay dummy wiring is rerouted based on the delay reference table 4, and the process returns to step 22 after completion. If there is no wiring delay dummy wiring in step 31, the process proceeds to step 33.

  In step 33, if there is no power supply strap between the timing correction target cell arrangements and no wiring delay cell, manual correction is performed based on the wiring layer, wiring width, and wiring length based on the delay reference table 4. .

  In the present embodiment, the wiring extension process 29 on the strap power supply / ground wiring in the third embodiment is provided, and highly accurate timing adjustment can be performed while reducing the man-hours, thereby realizing a short TAT development.

(Fifth embodiment)
FIG. 10 is a flowchart showing the operation of the semiconductor integrated circuit design apparatus of this embodiment.

  In the automatic placement and routing step 20, the semiconductor layout tool performs routing according to the standard cell placement and netlist connection information based on the placement and routing algorithm of the tool. At this time, wiring delay cells and wiring delay dummy wirings are also arranged in the same manner as in the third embodiment.

  Steps 21, 22, 23, 24, and 26 are also the same as in the third embodiment.

  In step 31, from the physical coordinate arrangement of the timing correction target cell calculated in step 26, it is calculated whether or not a wiring delay dummy wiring exists in a rectangular area between the timing correction target cell arrangement origins.

  In step 32, if there is a wiring delay dummy wiring in step 31, the wiring delay dummy wiring is rerouted based on the delay reference table 4.

  In step 34, when there is no wiring delay dummy wiring in step 31, and there is an arrangement delay cell in the vicinity of the arrangement of the timing correction target cell, Japanese Patent Laid-Open No. 2001-34647 (page 1-6, FIG. 1). The cell is hunted by this method, and the timing correction is performed by rewiring the timing correction target cell and the hunted cell.

  In the present embodiment, the wiring extension process 32 by connecting the wiring delay dummy wiring in the third embodiment is provided, and high-precision timing adjustment can be performed while reducing the number of man-hours, thereby realizing short TAT development.

(Sixth embodiment)
FIG. 11 is a flowchart showing the operation of the semiconductor integrated circuit design apparatus of this embodiment.

  In the automatic placement and routing step 20, the semiconductor layout tool performs routing according to the standard cell placement and netlist connection information based on the placement and routing algorithm of the tool. At this time, wiring delay cells are also arranged. At this time, the wiring delay cells to be arranged are randomly arranged by the shotgun arrangement of the layout tool based on the cell list created by the designer.

  Steps 21, 22, 23, 24, and 26 are the same as those in the third embodiment.

  In step 28, it is determined whether or not there is a wiring delay cell arranged in step 20 in the rectangular area formed at the origin of physical coordinates of the timing correction target cell extracted in step 26.

  In step 33, if there is no wiring delay cell between the timing correction target cells, manual correction is performed based on the wiring layer, wiring width, and wiring length based on the delay reference table 4.

  In step 34, when there is an arrangement delay cell in the vicinity of the arrangement of the timing correction target cell, the cell is hunted by the technique of Japanese Patent Laid-Open No. 2001-34647 (page 1-6, FIG. 1), and the timing correction target cell is Then, rewiring the hunted cells to correct the timing.

  In the present embodiment, the wiring delay cell hunting / rewiring process 34 in the third embodiment is provided, and highly accurate timing adjustment can be performed while reducing the number of steps, and short TAT development can be realized.

The figure which shows an example of the wiring delay cell used in the 1st Embodiment of this invention. (A) is a figure which shows preparation of the delay time reference table in the 1st Embodiment of this invention, (b) is a figure which shows an example of the delay time reference table. (A) is a figure which shows preparation of the delay time reference table in the 2nd Embodiment of this invention, (b) is a figure which shows an example of the delay time reference table. The schematic diagram of the wiring delay dummy wiring inserted in the 2nd Embodiment of this invention. 9 is a flowchart showing the operation of the semiconductor integrated circuit design apparatus according to the third embodiment of the present invention. The figure which shows the 1st example of the timing adjustment in the 3rd Embodiment of this invention. The figure which shows the 2nd example of the timing adjustment in the 3rd Embodiment of this invention. The figure which shows the 3rd example of the timing adjustment in the 3rd Embodiment of this invention. 10 is a flowchart showing the operation of the semiconductor integrated circuit design device of the fourth exemplary embodiment of the present invention. 10 is a flowchart showing the operation of the semiconductor integrated circuit design device of the fifth exemplary embodiment of the present invention. 14 is a flowchart showing the operation of the semiconductor integrated circuit design apparatus according to the sixth embodiment of the present invention. (A) is a partial flowchart in the semiconductor manufacturing process, (b) is a diagram showing the layout of the semiconductor device after automatic placement and routing. 10 is a flowchart of timing adjustment in a conventional semiconductor device design method. The figure which shows an example of the timing adjustment by a conventional method.

Explanation of symbols

1 Step of creating a delay time reference table of wiring delay cells 2 Database of delay time reference tables of wiring delay cells 3 Creating a reference table of wiring shapes (width / length) and delay times by process and wiring layer Step 4 Wiring shape (width / length) and delay time reference table database by process / wiring layer 5 Power wiring of wiring delay cell 6 Ground wiring of wiring delay cell 7 Pin 8 Pin 9 Shield wiring 11 Layout block 12 Timing adjustment target cell 13 Cell array 14 Inter-cell wiring 15 Wiring delay dummy wiring 16 Transistor formation process 17 Wiring layer process 18 Cell group 19 not subject to timing adjustment Wiring 20 showing manual wiring correction example Automatic placement and wiring process 21 Delay Information extraction process 22 Timing verification process 23 Timing error presence determination process 2 Correction target timing error extraction step 25 Manual wiring correction step 26 Corrected cell point placement / wiring information extraction step 27 Power supply strap presence / absence determination step 28 Wiring delay cell presence / absence determination step 29 Power supply strap on-wire extension step 30 Remaining error item presence / absence determination step 31 Wiring delay dummy wiring presence determination process 32 Wiring extension process by wiring delay dummy wiring connection 33 Manual wiring correction process 34 Wiring delay cell hunting / rewiring process 36 Strap power supply / ground wiring,
37 Extension wiring 38 implemented in wiring extension process 29 Cutting part 39 of inter-cell wiring 14 Wiring delay dummy connection wiring 40 Wiring delay cell 41 Wiring delay cell connection wiring

Claims (9)

A process of physically designing a semiconductor device by arranging and wiring a plurality of standard cell type functional cells by automatic placement and routing;
Performing timing verification of the physically designed semiconductor device;
As a result of the timing verification, if there is a timing error, extracting a timing error that can be resolved by changing the wiring length between the functional cells; and
Rewiring to eliminate the timing error, and
The semiconductor device design method returns to the step of performing the timing verification of the semiconductor device after the step of performing the rewiring until the timing error is eliminated,
Standard cells each having two pins serving as an input pin and an output pin and an internal wiring for connecting the two pins, each having a different wiring length and having a specific delay time according to each wiring length For a plurality of wiring delay cells of a type, a delay time reference table for wiring delay cells describing each delay time is prepared in advance,
In the step of physically designing the semiconductor device, the wiring delay cell is disposed in a region where the functional cell is not disposed, and the rewiring step includes the wiring delay cell for eliminating the timing error. The semiconductor is selected based on the delay time reference table for the wiring delay cell, and rewiring is performed so that the selected wiring delay cell is connected between the functional cells in which the timing error exists. Device design method. A process of physically designing a semiconductor device by arranging and wiring a plurality of standard cell type functional cells by automatic placement and routing;
Performing timing verification of the physically designed semiconductor device;
As a result of the timing verification, if there is a timing error, extracting a timing error that can be resolved by changing the wiring length between the functional cells; and
Rewiring to eliminate the timing error, and
The semiconductor device design method returns to the step of performing the timing verification of the semiconductor device after the step of performing the rewiring until the timing error is eliminated,
Prepare in advance a wiring delay time reference table that describes each delay time for a plurality of wirings each having a unique delay time according to the wiring width and wiring length by each process or wiring layer,
In the step of physically designing the semiconductor device, dummy wiring is arranged, and the step of performing the rewiring is performed by the dummy wiring for eliminating the timing error based on the wiring delay time reference table. A method of designing a semiconductor device, wherein rewiring is performed so as to be part of wiring between the functional cells having a timing error. A process of physically designing a semiconductor device by arranging and wiring a plurality of standard cell type functional cells by automatic placement and routing;
Performing timing verification of the physically designed semiconductor device;
As a result of the timing verification, if there is a timing error, extracting a timing error that can be resolved by changing the wiring length between the functional cells; and
Rewiring to eliminate the timing error, and
The semiconductor device design method returns to the step of performing the timing verification of the semiconductor device after the step of performing the rewiring until the timing error is eliminated,
Prepare in advance a wiring delay time reference table that describes each delay time for a plurality of wirings each having a unique delay time according to the wiring width and wiring length by each process or wiring layer,
In the step of physically designing the semiconductor device, a strap power supply / ground wiring is arranged, and the rewiring step is performed in such a manner that the wiring connecting the functional cells having the timing error is the strap power supply / ground wiring. Is arranged on the strap power supply / ground wiring for eliminating the timing error based on the wiring delay time reference table, and the bypass wiring is arranged for the timing error. A method for designing a semiconductor device, wherein rewiring is performed so as to be part of wiring between the existing functional cells. A process of physically designing a semiconductor device by arranging and wiring a plurality of standard cell type functional cells by automatic placement and routing;
Performing timing verification of the physically designed semiconductor device;
As a result of the timing verification, if there is a timing error, extracting a timing error that can be resolved by changing the wiring length between the functional cells; and
Rewiring to eliminate the timing error, and
The semiconductor device design method returns to the step of performing the timing verification of the semiconductor device after the step of performing the rewiring until the timing error is eliminated,
Prepare in advance a wiring delay time reference table that describes each delay time for a plurality of wirings each having a unique delay time according to the wiring width and wiring length by each process or wiring layer,
In the step of physically designing the semiconductor device, a step of arranging a plurality of fixed-length dummy wirings having a predetermined unit delay based on the wiring delay time reference table and performing the rewiring includes the wiring Rewiring is performed such that the dummy wiring for eliminating the timing error becomes a part of the wiring between the functional cells in which the timing error exists based on a delay time reference table for use Device design method. Standard cells each having two pins serving as an input pin and an output pin and an internal wiring for connecting the two pins, each having a different wiring length and having a specific delay time according to each wiring length For a plurality of wiring delay cells of a type, a delay time reference table for wiring delay cells describing each delay time is prepared in advance,
In the step of physically designing the semiconductor device, the wiring delay cells are arranged in a region where the functional cells are not arranged, and the rewiring step is performed between and near the functional cells where the timing error exists. When the dummy wiring does not exist, the wiring delay cell for eliminating the timing error is selected based on the wiring delay cell delay time reference table, and the selected wiring delay cell has the timing error. 5. The method of designing a semiconductor device according to claim 4, wherein rewiring is performed so as to be connected between the functional cells.   In the step of physically designing the semiconductor device, the strap power supply / ground wiring is arranged, and the rewiring step is performed by connecting the strap power supply / ground wiring to the functional cells having the timing error. Is arranged on the strap power supply / ground wiring for eliminating the timing error based on the wiring delay time reference table, and the bypass wiring is arranged for the timing error. 6. The method of designing a semiconductor device according to claim 4, wherein rewiring is performed so as to become part of wiring between the existing functional cells. Prepare in advance a wiring delay time reference table that describes each delay time for a plurality of wirings each having a unique delay time according to the wiring width and wiring length by each process or wiring layer,
In the step of physically designing the semiconductor device, a strap power supply / ground wiring is arranged, and the rewiring step is performed in such a manner that the wiring connecting the functional cells having the timing error is the strap power supply / ground wiring. Is arranged on the strap power supply / ground wiring for eliminating the timing error based on the wiring delay time reference table, and the bypass wiring is arranged for the timing error. The method of designing a semiconductor device according to claim 1, wherein rewiring is performed so as to be part of wiring between the existing functional cells.   8. The method of designing a semiconductor device according to claim 1, wherein the wiring delay cell has a shield wiring for ensuring reliability of a signal passing through the internal wiring.   9. A semiconductor device design apparatus comprising means for performing each step in the semiconductor device design method according to claim 1.

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