JP2005079873A - Method of transmitting digital data signal, method of decoding digital data signal, digital data signal output circuit, and digital data signal decoding circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of data lines used for transmission by multiplexing parallel digital data in the direction of a time axis. <P>SOLUTION: On the side of an output circuit of a digital data signal, parallel digital data signals S0 and S1 are encoded. A plurality of encoded pieces of digital data ENa to ENc are sampled by a plurality of delay clocks related with a clock CK. A plurality of sampled pieces of digital data SSa to SSc are multiplexed in the direction of the time axis of the clock CK to obtain a digital data signal DO being an output signal. Since the signal DO is one, only one data line is required for transmitting the digital data signal DO, and thereby the number of the data lines is reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a digital data signal transmission method, a digital data signal decoding method, a digital data signal output circuit, and a digital data signal decoding circuit suitable for application to a digital transmission system for transmitting n parallel digital data.

  Specifically, the number of data lines can be reduced when digital data is exchanged using a signal line (data line), and n (n ≧ 2) parallel digital data is transmitted. Even in such a case, parallel digital data can be transmitted simultaneously with a small number of data lines.

  When digital data is transmitted, it is necessary to transmit a clock for reproducing the digital data in addition to the data line for transmitting the digital data. Therefore, at least two data lines are required.

  As a technique for reducing the number of data lines including a clock as much as possible, a technique of transmitting digital data in a state of being multiplexed in the clock amplitude direction or the time axis direction is known (for example, Patent Document 1).

  In this technique, binary digital data is multiplexed in the amplitude direction of the clock to be transmitted, or binary digital data is multiplexed and transmitted in the time axis direction of the clock.

Japanese Patent Laid-Open No. 3-52437

  When the technique disclosed in Patent Document 1 described above is adopted, two data lines can be made one, and only one data line can be omitted. However, there is only one type of digital data that can be handled.

  Even when a certain signal (information) is converted into digital data having an appropriate number of bits, they are converted into serial digital data by parallel-serial conversion and multiplexed into a clock. Therefore, no specific technique for transmitting parallel digital data while reducing the number of data lines is disclosed. For example, a technique for superimposing and transmitting digital data converted into 3 bits on a clock as parallel data is not disclosed.

  Further, the digital data of a plurality of signals (information) having different contents are arranged in parallel, and the specific number n (n ≧ 2) digital data arranged in parallel can be transmitted simultaneously without increasing the data line. No technology is disclosed.

  This is because when n pieces of digital data are transmitted simultaneously, that is, in order to simultaneously transmit n pieces of parallel digital data, at least (n + 1) data lines are required.

  However, as the number of data lines increases, when connecting ICs such as LSIs, the same number of connection pins (terminal pins) as the data lines are required. The area of the IC substrate on which the LSI is mounted is increased, which becomes a bottleneck for downsizing the electronic device on which the IC substrate is mounted.

  For example, as shown in FIG. 16, when a plurality of, for example, two LSIs 1 and 2 mounted on an IC substrate (not shown) each have y input / output terminals, an IC for connecting these LSIs 1 and 2 is used. The data lines 3 formed on the substrate also require y data lines 3. As the number of data lines 3 increases, the area of the LSI itself and the IC substrate increases accordingly.

  In addition, when many data lines 3 are required, in order to adjust the delay amount between the data lines, it is necessary to design an equal length wiring between the data lines and an IC board in consideration of impedance matching. With the above constraints.

  Therefore, the present invention solves such a conventional problem, and in particular, even when n parallel digital data is transmitted, a digital data signal transmission method capable of greatly reducing the number of data lines. Etc. are proposed.

  In order to solve the above-described problem, in the digital data signal transmission method according to the first aspect of the present invention, n parallel digital data (n ≧ 2) are synchronized with the clock, and the n number of the parallel digital data is included in the clock. And a step of multiplexing the parallel digital data.

According to a fourteenth aspect of the present invention, there is provided a digital data signal decoding method according to the present invention, further comprising a data decoding unit that is synchronized with a transmission clock and is supplied with a digital data signal in which n-bit parallel digital data is multiplexed on the transmission clock. And
The data decoding unit decodes the digital data signal into the n-bit parallel digital data.

A digital data signal output circuit according to the present invention as set forth in claim 28, further comprising a multiplexing unit to which a clock and n (n ≧ 2) parallel digital data synchronized with the clock are respectively supplied.
The multiplexing section outputs a digital data signal in which the parallel digital data is multiplexed in the amplitude direction of the clock.

A digital data signal output circuit according to a thirty-second aspect of the present invention includes a multiplexing unit to which a clock and n (n ≧ 2) parallel digital data synchronized with the clock are respectively supplied.
The multiplexing section outputs a digital data signal in which the parallel digital data is multiplexed in the time axis direction of the clock.

A digital data signal decoding circuit according to the present invention as set forth in claim 41, further comprising a data decoding unit to which a digital data signal in which parallel digital data is multiplexed in a transmission clock is supplied,
The data decoding unit separates the transmission clock and uses the separated transmission clock to decode the parallel digital data multiplexed in the amplitude direction of the transmission clock. .

According to a 45th aspect of the present invention, there is provided a digital data signal decoding circuit according to the present invention, comprising: a data decoding unit to which a digital data signal in which parallel digital data is multiplexed is supplied to a transmission clock;
The data decoding unit separates the transmission clock and uses the separated transmission clock to decode the parallel digital data multiplexed in the time axis direction of the transmission clock. To do.

  In the present invention, n-bit parallel digital data or n serial digital data are arranged as n parallel digital data, and these n digital data are multiplexed and transmitted as a set to a clock to be transmitted in order. . Multiplexing to a clock can be considered in the amplitude direction of the clock and its time axis direction.

  When n parallel digital data are multiplexed in the clock amplitude direction, the n parallel digital data are regarded as n-bit digital data and converted into analog data. For example, when three parallel digital data are sequentially transmitted, the digital data is regarded as 3-bit digital data, and the 3-bit digital data is converted into analog data. Then, analog data corresponding to the bit contents (“1”, “0”) is obtained. For example, when analog data at “000” is used as a reference level (eg, zero level), parallel digital data of “111” is obtained as analog data having an analog level that is eight times the reference level.

  Then, the analog data converted according to the bit content of each parallel digital data is multiplexed on the clock. The multiplexed section is a section that is inverted to a high level (or low level) when the clock has a duty of 50%, and analog data is multiplexed only during this high level inversion period.

  When converting n pieces of parallel digital data into analog data, in addition to a method of simply converting n pieces of parallel digital data into analog data, the n pieces of parallel digital data are once encoded and encoded. There is a method for converting digital data into analog data.

  Thus, when a digital data signal obtained by multiplexing analog data on a clock is used as a transmission signal, the clock included in the digital data signal functions as a transmission clock. Therefore, even if three parallel digital data are simultaneously transmitted, only one data line is required because only one digital data signal is to be transmitted.

  This means that even if there are four parallel digital data, if this is regarded as 4-bit parallel digital data, analog conversion processing is performed and multiplexed on the clock, five data lines including the clock are required. Thus, data can be transmitted by only one data line.

  It is also possible to multiplex n parallel digital data in the time axis direction instead of the clock amplitude direction. In this case, a clock that is faster than the transmission clock can be used for data multiplexing. When a high-speed clock is used, a high-speed clock is generated from the transmission clock, and n parallel digital data are multiplexed on the original clock (transmission clock) based on the high-speed clock.

  The n parallel digital data existing on the same time axis are converted into n digital data, each of which is shifted in time axis, and the converted n digital data is, for example, in a high level section of a clock. Multiplexed in the time axis direction. For example, when there are three pieces of parallel digital data, the three digital data are sequentially multiplexed using four or more clocks of the transmission clock so that the three digital data can be multiplexed in the high level section of the clock. .

In this way, since three parallel digital data are multiplexed in the transmission clock, if this multiplexed signal is used as a transmission signal (digital data signal), only one data line is sufficient. . Depending on how to shift in the time axis direction, a high-speed clock of (2 ⁿ +1) times or more is used.

  As the number of data lines is reduced, when the present invention is applied to an LSI data transmission system, the number of input / output terminals of the LSI can be reduced, and on the side of an IC board on which a plurality of LSIs are mounted, etc. Since IC circuit design can be performed without considering long wiring and impedance matching, the circuit design is facilitated, and the LSI area and IC board area can be reduced.

  When the number of input / output terminals of an LSI is large, if processing is performed for every n bits, even if there are n × a times the number of input / output terminals, the total number of data lines is (n × a). Multiple parallel digital data can be transmitted simultaneously.

  As described above, according to the present invention, n parallel digital data are multiplexed and transmitted in the amplitude direction or time axis direction of the clock, so that the number of data lines at that time is significantly larger than the conventional number. The actual profit can be reduced.

  Next, preferred embodiments of a digital data signal transmission method and the like according to the present invention will be described in detail with reference to the drawings.

  In the present invention, n parallel digital data are multiplexed and transmitted on a clock, and the receiving side extracts this clock to separate and decode the n parallel digital data.

  As n parallel digital data, first, the same signal (information) is converted into n-bit digital data, and n (n bits) parallel digital data including upper bits to lower bits at that time Can be considered. In other words, it is handled as parallel digital data.

  The second is not related to whether or not they are related to each other, but each of n signals (information) is converted into digital data of a predetermined number of bits and converted into serial digital data. Parallel digital data can be considered when n data are arranged. The present invention can handle any of the parallel digital data.

  Multiplexing of parallel digital data to the clock is considered to be multiplexing in the amplitude direction of the clock and multiplexing in the time axis direction. The number n of parallel digital data to be transmitted at the same time may be two or more. In the following description, n = 2 and n = 3 will be exemplified. First, a case where n = 2 is illustrated. An example of the transmission system is a data transmission system between LSIs as shown in FIG.

(1) Example of multiplexing in the amplitude direction of the clock when n = 2 FIG. 1 shows an embodiment at this time. FIG. 1 shows a digital data signal transmission / reception system, which comprises a digital data signal output circuit 10 and a digital data signal decoding circuit 100. The digital data signal output circuit 10 constitutes a digital data signal transmitter, and is provided in the output stage on the LSI 1 side in FIG. The digital data signal decoding circuit 100 constitutes a digital data signal receiving unit, and is provided in an input stage on the LSI 2 side.

  Referring to the timing chart of FIG. 2, the output circuit 10 of the digital data signal DO has n parallel digital data S0 and S1 (FIG. 2B) synchronized with the clock CK (FIG. 2A). , C), and a multiplexing unit 20 for multiplexing.

  The multiplexing unit 20 multiplexes the D / A conversion unit 22 for parallel digital data, the sampling unit 24 for sampling the analog data that has been D / A converted, the analog data that has been sampled and converted into a pulse shape, and the clock CK. And a multiplexing unit 26.

  The D / A converter 22 is supplied with the clock CK from the terminal 18 and is supplied with two parallel digital data S0 and S1 synchronized with the clock CK from the terminals 12 and 14. The two parallel digital data S0 and S1 that are simultaneously input in parallel are regarded as 2-bit parallel digital data, and the parallel digital data S0 and S1 are converted into analog data SA.

  Accordingly, when 2-bit parallel digital data S0 and S1 are input as a combination of bits as shown in FIGS. 2B and 2C, analog data SA as shown in FIG. 2C is obtained by analog conversion. At this time, one parallel digital data S0 functions as a lower bit, and the other parallel digital data S1 functions as an upper bit. Incidentally, the analog data SA when the input bit is (0, 0) is “0” (zero = reference level), and the analog data SA when the input bit is (0, 1) is “1”. .

  The analog data SA is supplied to the sampling unit 24 together with the clock CK, and the analog data SA is sampled. Assuming that the analog data SA is output when the clock CK is at a high level and the ground level is output when the clock CK is at a low level, the sampling output having an analog level corresponding to the input bit as shown in FIG. 2E by the clock CK. SS is obtained. In the case of 2-bit input, it has four analog levels.

  The sampling output SS is supplied together with the clock CK to the adder 26 constituting the multiplexing unit. The adder 26 multiplexes (adds) the sampling output SS to the clock CK. Since the sampling output SS having the same pulse width as that of the clock CK is obtained at the same timing (high level interval) as that of the clock CK, the output signal shown in FIG. 2F in which the sampling output SS is multiplexed in the amplitude direction of the clock CK is obtained. . This output signal becomes the digital data signal DO.

  Since the digital data signal DO includes a clock (transmission clock) CK and also includes parallel digital data S0 and S1 to be transmitted, only one data line 28 connecting LSI1 and LSI2 is sufficient. Therefore, only one data line 28 is connected to the output terminal 27.

  The decoding circuit 100 for the digital data signal DO includes a data decoding unit 110 as shown in FIG.

  The data decoding unit 110 includes an A / D conversion unit 102 to which a digital data signal DO is supplied, a buffer unit 105 that functions as a transmission clock extraction unit for extracting a clock (transmission clock) CK from the digital data signal DO, The delay unit 106 delays the extracted clock CK.

  A predetermined threshold level is prepared in the buffer unit 105, and the digital data signal DO is compared by using the threshold level to compare the level of the digital data signal DO input through the input terminal 104. Thus, the clock CK is extracted. The extracted clock CK is further supplied to the delay unit 106, and in this example, is delayed by about ¼ clock from the input digital data signal DO. The delayed clock DLCK (FIG. 2G) is output to the output terminal 107 and supplied to the A / D converter 102.

  The A / D conversion unit 102 performs A / D conversion in synchronization with the extracted clock CK, and generates two parallel digital data from the input digital data signal DO. In this example, the level of the input digital data signal DO at the rising timing of the clock CK is sampled, and the sampling level is converted into 2-bit digital data.

  As a result, as shown in FIG. 2, in this example, the input digital data signal DOa having the lowest analog level with the clock CK multiplexed is converted into 2-bit digital data (0, 0). Therefore, the input digital data signal DOb having a level higher by one level than the lowest level is converted into 2-bit digital data (0, 1), and the input digital data signal DOd having the highest level is converted into 2-bit digital data (1 , 1), parallel digital data S0 and S1 as shown in FIGS. 2H and I are decoded and generated at the output terminals 108 and 109 at the same time.

  In this way, by multiplexing the data corresponding to the two parallel digital data S0 and S1 in the amplitude direction of the clock CK, the parallel digital data can be transmitted using a small number of data lines.

(2) Example of multiplexing n = 2 in the time axis direction of the clock CK A description will be given with reference to FIGS. In FIG. 3, the digital data signal output circuit 10 has a multiplexing unit 30 for clock CK multiplexing n parallel digital data S0 and S1 synchronized with a clock CK.

  The multiplexing unit 30 includes an encoding unit (encoder) 42 that encodes the parallel digital data S0 and S1 (FIGS. 4B and 4C) synchronized with the clock, and a plurality of encoded units, three in this example, The encoded output (digital data) ENa, ENb, ENc (see FIGS. 4D to F) is sampled by three sampling clocks DLCKa to DLCKc (FIG. 4K to M) related to the clock CK, and sampled It comprises a multiplexing unit 48 that multiplexes three digital data SSa to SSc (FIGS. 4G to I) in the time axis direction of the clock CK.

  Two parallel digital data S0 and S1 shown in FIGS. 4A and 4B are supplied to the encoding unit 42 from terminals 32 and 34, respectively. The encoding unit 42 encodes the input two parallel digital data S0 and S1 as 2-bit digital data, and converts the data into 3-bit digital data. Since there are a total of four bit combinations when the input is two parallel digital data S0 and S1, a total of three encoded outputs are required except for zero. Therefore, the encoding unit 42 performs encoding (pulse width modulation) so as to obtain three encoded outputs ENa to ENc as shown in FIGS.

  That is, as shown in FIG. 4, when the input parallel digital data S0 and S1 are (0, 0), an all-zero encoded output (ENa, ENb, ENc) = (0, 0, 0) is output. When (0,1) is (0,1), (1,0,0) is output. When the input is (1,0), (1,1,0) is output and the input is (1,1). In this case, the encoding process is performed so that all 1 encoded outputs (1, 1, 1) are output.

  The encoded encoded outputs ENa to ENc are supplied to the sampling unit 44. The sampling units 44 are provided as many as the number of encoded outputs, and delay clocks DLCKa to DLCKc obtained by sequentially delaying the clock CK supplied to the terminal 36 are supplied to the sampling units 44A to 44C. As shown in FIG. 4A, the clock CK is a pulse signal having a duty of 1/4 in this example in consideration of data multiplexing.

  Therefore, the clock CK is supplied to the first delay unit 46A of the cascaded delay units 46A to 46C and delayed by one clock. The delayed clock DLCKa is supplied to the first sampling unit 44A, where the lower bit encoded output ENa is sampled to obtain a sampling output SSa shown in FIG. 4G.

  Similarly, the clock DLCKb delayed by two clocks by the second-stage delay unit 46B and the intermediate bit encoded output ENb are supplied to the second sampling unit 44B, and the sampling output SSb shown in FIG. Then, the clock DLCKc delayed by 3 clocks output from the delay unit 46C at the final stage and the encoded output ENc of the upper bits are supplied to the third sampling unit 44C, and the sampling shown in FIG. 4I is performed. An output SSc is obtained.

  Here, since the delay clocks DLCKa to DLCKc are delayed by one clock, the relationship between the sampled outputs SSa, SSb, and SSc is obtained in a state shifted by one clock as shown in FIG.

The three sampling outputs SSa to SSc are supplied to an adder 48 that functions as a multiplexing unit, and are multiplexed (added) with the original clock CK that is not delayed.
As a result, when the input parallel digital data is (0, 0), only the clock CK is output, and when the input parallel digital data is (1, 0), the sampling output SSa is superimposed after the clock CK. The pulse width of the output signal DO increases by the pulse width of one clock.

  Similarly, when the input parallel digital data is (0, 1), since the sampling outputs SSa and SSb are superimposed, the pulse width of the output signal DO is widened by a pulse width of 2 clocks. When the parallel digital data is (1, 1), the sampling outputs SSa, SSb, and SSc are superimposed on the clock CK, respectively. As a result, the pulse width of the output signal DO is expanded by a pulse width of 3 clocks.

  Thus, by this sampling process and addition process, the two parallel digital data are regarded as 2-bit digital data, converted in the time axis direction of the clock CK, and multiplexed in the time axis direction of the clock CK. As a result, an output signal DO having a pulse width corresponding to the values (data values) of the parallel digital data S0 and S1 is obtained.

  The output signal DO becomes a digital data signal and is output from the output terminal 49 of the output circuit 10. Also in this case, the digital data signal DO includes the clock CK that also functions as a transmission clock, and the parallel digital data S0 and S1 are also superimposed in a state converted in the time axis direction. Only one data line 36 is required to transmit.

  The decoding circuit 100 for the digital data signal DO includes a data decoding unit 120 as shown in FIG.

  The data decoding unit 120 includes a transmission clock extraction unit 122 and a data generation unit 123 that generates parallel digital data S0 and S1 based on the extracted transmission clock CK.

  The transmission clock extraction unit 122 includes three delay units 122 (122A to 122C) connected in cascade to which the digital data signal DO is supplied. The data generation unit 123 constitutes a sampling unit 124 that can be expressed as a data conversion unit to which a digital data signal DO is supplied. In this example, three D-type flip-flops 124A to 124C and data decoding signals DFa to DFc are supplied. The data decoding unit 126 is configured to generate original parallel digital data S0 and S1 from the decoded outputs DCa and DCb. In this example, the data decoding unit 126 includes two D-type flip-flops 128A and 128B.

  A predetermined threshold level is set in the first-stage delay unit 122A that constitutes the transmission clock extraction unit, and the level of the digital data signal DO input through the input terminal 132 is set using this threshold level. By comparison, a clock (transmission clock) CK is extracted from the digital data signal DO, and in this example, a delayed clock DLCKa (FIG. 4K) obtained by delaying the extracted clock CK by one clock is output. The delayed clock CK is further supplied to the delay unit 122B to obtain a delay clock DLCKb (FIG. 4L) delayed by one clock, and further delayed by one clock by the final delay unit 122C. DLCKc (FIG. 4M) is output.

  The sampling unit 124 performs data conversion processing (sampling processing for pulse width conversion) such that a signal corresponding to the pulse width of the digital data signal DO is output by the delay clocks DLCKa to DLCKc. In this example, by sampling the level of the input digital data signal DO at the rising timing of the delay clock DLCKa, the D-type flip-flop 124A can obtain the sampling output (pulse width conversion output) DFa shown in FIG. 4N.

  Similarly, in the interstage D-type flip-flop 124B, the input signal is sampled (latched) by the delay clock DLCKb, whereby the sampling output DFb shown in FIG. 4O is obtained, and the delay clock DLCKc is supplied. A sampling output DFc shown in FIG. 4P is obtained from the D-type flip-flop 124C of the stage.

  The three sampling outputs DFa to DFc are supplied to the data decoding unit (decoder) 126, and the following decoding process is performed. Referring to FIGS. 4N to 4P and FIGS. 4Q and R, in this example, when the data conversion signals DFa to DFc are both zero, the data decoding signals DCa and DCb are both zero.

  When only the sampling output DFa is “1”, only the data decoded signal DCa is output to be “1”. When both the sampling outputs DFa and DFb are “1”, a decoding process is performed so that only the data decoded signal DCb becomes “1”, and when all the sampling outputs DFa to DFc are “1”. Then, a decoding process is performed in which the data decoded signals DCa and DCb are both “1”.

  Such data decoded signals DCa and DCb are further supplied to D-type flip-flops 128A and 128B, and the two data decoded signals DCa and DCb are sampled by the original clock CK. , S1 (FIG. 4S, T) are output. That is, the parallel digital data S0 and S1 before being multiplexed with the clock CK are restored.

  By multiplexing the two parallel digital data S0 and S1 converted in the time axis direction of the clock CK in this way, digital data can be transmitted using one data line 36.

  Next, an example of multiplexing three parallel digital data to the clock CK will be described with reference to FIG.

(3) Example of multiplexing in the amplitude direction of the clock CK when n = 3 (part 1)
This is the same configuration as described in (1). Since only the input side has been changed to three parallel digital data, description and operation thereof will be omitted.

(4) Example of multiplexing in the amplitude direction of the clock CK when n = 3 (part 2)
This will be described with reference to FIGS. FIG. 5 shows a digital data signal transmission / reception system, which comprises a digital data signal output circuit 10 and a digital data signal decoding circuit 100. The digital data signal output circuit 10 constitutes a digital data signal transmitter, and is provided in the output stage on the LSI 1 side. The digital data signal decoding circuit 100 constitutes a digital data signal receiving unit, and is provided in an input stage on the LSI 2 side.

  The output circuit 10 of the digital data signal DO is for multiplexing n pieces of parallel digital data S0, S1, S2 (FIGS. 6B, C, D) in this example in synchronization with the clock CK (FIG. 6A). The multiplexer 50 is configured.

  The multiplexing unit 50 is sampled by a parallel digital data encoding unit 52, a D / A conversion unit 54 that D / A converts the encoded output, and a sampling unit 56 that samples the D / A converted analog data. Thus, it is constituted by a multiplexing unit 58 that multiplexes the analog output data converted into a pulse shape and the clock CK.

  The encoding unit 52 is supplied with three parallel digital data S0, S1, and S2 synchronized with the clock CK from terminals 31a to 31c. The encoding unit 52 performs encoding by regarding each of the three parallel digital data S0 to S2 as 3-bit digital data. That is, the parallel digital data S0 is regarded as the lower bits and the parallel digital data S2 is regarded as the upper bits, and the encoding process is performed.

  In the encoding process according to this embodiment, parallel digital data S0 and S2 regarded as lower and upper bits are respectively inverted in phase and output, and the intermediate bit S1 is output as it is as encoded outputs ENa to ENc. And The encoded output after the encoding process is shown in FIGS.

  The encoded encoded outputs ENa to ENc are converted into analog data by the D / A converter 54 at the subsequent stage. A clock CK is supplied from a terminal 55 to the D / A converter 54, and analog conversion processing is performed in synchronization with the clock CK. In this embodiment, D / A conversion is performed so that the analog level when the values of the parallel digital data S0 to S2 are (1, 0, 1) becomes a reference value (for example, zero).

  In the case of three parallel digital data S0 to S2, eight encoded outputs ENa to ENc are obtained by combinations of input data values, and therefore there are eight levels by combining these encoded outputs ENa to ENc. Is converted to analog data DC0 (FIG. 6H). Incidentally, when the encoded outputs ENa to ENc are (1, 1, 1), they are converted into the maximum analog data DC0 as shown in FIG. 6H.

  The analog data DC0 is supplied to the sampling unit 56 together with the clock CK, and the analog data DC0 is sampled. If the analog data DC0 is output when the clock CK is high level and the ground level is output when the clock CK is low level, the clock CK corresponds to the values of the parallel digital data S0 to S2 as shown in FIG. 6I. A sampling output SS0 having an analog level is obtained.

  The sampling output SS0 is supplied together with the clock CK to the adder 58 constituting the multiplexing unit. The adder 58 multiplexes (adds) the sampling output SS0 to the clock CK. Since the sampling output SS0 having the same pulse width as that of the clock CK is obtained at the same timing (high level interval) as that of the clock CK, the output signal shown in FIG. 6J in which the sampling output SS0 is multiplexed in the amplitude direction of the clock CK is obtained. . This output signal becomes the digital data signal DO.

  Since the digital data signal DO includes a clock (transmission clock) CK and further includes parallel digital data S0, S1, and S2 to be transmitted, one data line is used to transmit the digital data signal DO. Is enough. Therefore, even when three parallel digital data S0 to S2 are transmitted, only one data line 57 is connected to the output terminal 59.

  The decoding circuit 100 for the digital data signal DO includes a data decoding unit 140 as shown in FIG.

  The data decoding unit 140 includes a transmission clock extraction unit 145 that extracts a transmission clock from the digital data signal DO, and a data generation unit 149 that generates parallel digital data 0 to S2 from the digital data signal DO.

  The data generation unit 149 includes a level shift unit 142 that shifts the level of the digital data signal DO, an A / D conversion unit 143 that is supplied with the level-shifted digital data signal DO, and data that decodes the A / D conversion output. And a decoding unit 144.

  The transmission clock extraction unit 145 for extracting the clock CK from the digital data signal DO is configured as a buffer unit, and the extracted clock CK is delayed by the delay unit 146.

  A digital data signal DO is supplied to the buffer unit 145 through the input terminal 141, and the level of the digital data signal DO is compared using a predetermined threshold level prepared in advance. A clock (transmission clock) CK is extracted. The extracted clock CK is further supplied to the delay unit 146, and in this example, it is delayed by about 1/4 clock from the input digital data signal DO. The delayed clock DLCK (FIG. 6K) is supplied to the output terminal 148 and also supplied to the A / D conversion unit 143.

  On the other hand, the level shift unit 142 subtracts (level shifts) the level of the input digital data signal DO by the level of the clock CK superimposed thereon to return to the level before the clock CK is superimposed (FIG. 6I). reference).

  The A / D converter 143 to which the level-shifted digital data signal DO is supplied performs A / D conversion processing in synchronization with the delayed clock DLCK. In this example, the level of the input digital data signal DO at the rising timing of the clock CK is sampled, and the sampling level is converted into 3-bit digital data.

  As a result, in this example, when the digital data signal DOa (FIG. 6I) has a reference level before clock multiplexing, the three A / D conversion outputs ADa, ADb, ADc are all zero (0, 0, 0). Converted. Therefore, the A / D conversion outputs ADa to ADc of the digital data signal DOb (corresponding to the encoded output (1, 0, 0)) one level higher than the reference level are (1, 0, 0), which is the highest level. The A / D conversion outputs ADa to ADc of the high digital data signal DOh (see FIG. 6I) are (1, 1, 1).

  The A / D conversion outputs ADa to ADc are supplied to the data decoding unit 144 at the subsequent stage, and the process opposite to the encoding process is performed. In other words, in the decoding process in the data decoding unit 144, the A / D conversion outputs ADa and ADc corresponding to the higher order and the lower order are output in a state where the phase is inverted, and the A / D conversion output ADb corresponding to the middle order is output. It is output as it is to be a decoded output (output signal). As a result, the parallel digital data S0, S1, S2 at the time of input is restored (FIGS. 6O to Q).

  Thus, even in the case of three parallel digital data, if parallel digital data is converted in the clock amplitude direction and multiplexed in the clock amplitude direction, data can be transmitted and received with a small number. Therefore, for example, even when data is exchanged between LSIs having n × m terminals, the number of LSI terminals is m in principle by handling n digital data as n parallel digital data. Thus, it is possible to reduce the size of the LSI and the IC substrate on which the LSI is mounted.

(5) Example of multiplexing the clock CK in the time axis direction when n = 3 (part 1)
This will be described with reference to FIGS. FIG. 7 shows a digital data signal transmission / reception system, which comprises a digital data signal output circuit 10 and a digital data signal decoding circuit 100. The digital data signal output circuit 10 constitutes a digital data signal transmission unit, and is provided in the output stage on the LSI 1 side as described above. The digital data signal decoding circuit 100 constitutes a digital data signal receiving unit, and is provided in an input stage on the LSI 2 side.

  The output circuit 10 of the digital data signal DO is synchronized with the clock CK (FIG. 8A), and in this example, is a multiplexing unit 60 for multiplexing three parallel digital data S0, S1, S2 (FIGS. 8D to F). Composed.

  The multiplexing unit 60 includes a parallel / serial conversion unit 61 that functions as a data conversion unit that converts the input parallel digital data S0 to S2 in the time axis direction of the clock CK, and a clock multiplication that multiplies the clock CK into an integer multiple of the clock NCK. A unit 62 and a multiplexing unit 63 for multiplexing digital data converted in the time axis direction by parallel-serial conversion of parallel digital data into a clock.

  In this example, the parallel-serial converter 61 includes D-type flip-flops 61A, 61B, and 61C that are cascade-connected and have a preset terminal PR. Three parallel digital data S0 to S2 synchronized with the clock CK are supplied to the input terminals 64a to 64c. The parallel-serial conversion unit 61 regards these parallel digital data S0 to S2 as 3-bit digital data and performs parallel-serial conversion processing.

  Therefore, the digital data S2 regarded as the upper bits is supplied to the preset terminal PR of the flip-flop 61A in the first stage, and the digital data S1 regarded as the middle bits is supplied to the preset terminal PR in the flip-flop 61B between the stages. The digital data S0 regarded as the lower bits is supplied to the preset terminal PR of the flip-flop 61C provided at the final stage. The data terminal D of the first flip-flop 61A is grounded and supplied with digital data “0”. A plurality of flip-flops 61A to 61C are connected in cascade so that the flip-flop output Q of the previous stage becomes the input of the data terminal D of the next stage.

  Further, the clock (reference clock) CK supplied to the terminal 65 is inverted in phase through the inverter 66, and in this example, the inverted clock DLCK (FIG. 8B) is slightly delayed in the flip-flops 61A to 61A. 61C is supplied to each load terminal LO. The input clock CK is further supplied to the PLL 62 in this example that constitutes the clock multiplier, and in this example, the high-speed clock NCK multiplied by 4 is generated (FIG. 8C). The multiplication number depends on the number of input parallel digital data. In the case of n = 3, in order to convert these parallel digital data as n digital data, in order to convert these parallel digital data in the time axis direction of the reference clock CK, at least the reference clock is required. This is because the added high-speed clock needs to be 4 times. The high-speed clock NCK is supplied to the clock terminals (CK) of the flip-flops 61A to 61C.

  In the above-described flip-flops 61A to 61C, when the load terminal LO is at a high level, the digital data input to the preset terminal PR is loaded to the output Q at the rising edge of the high-speed clock NCK supplied to the clock terminal (CK). When the load terminal LO is at a low level, the digital data input to the data terminal D is output at the rising edge of the high-speed clock NCK supplied to the clock terminal (CK).

  As a result, as shown in FIGS. 8D to 8F, when the parallel digital data S0 to S2 are (0, 0, 0), all the flip-flops 61A to 61C are loaded with “0”. “0” is output from the output Q of the flip-flop 61C of the stage. When the next parallel digital data is (1, 0, 0), only “1” is preset at the preset terminal PR for the flip-flop 61C at the final stage, and this becomes the output of the output terminal Q at the next high-speed clock timing. Thus, a high level output FF0 is obtained for one clock of the high-speed clock NCK. In the example of FIG. 8G, since the delay amount at the time of data processing of the parallel-serial conversion unit 61 is taken into consideration, the output FF0 is delayed by 1/2 NCK and output in this example. The following operations are also delayed and output by the same amount.

  At the timing of the next clock CK, the data of (0, 1, 0) is preset at the preset terminal PR, so that it is delayed by one clock of the high-speed clock NCK from the immediately preceding output timing (in practice, A parallel-serial conversion output FF0 that is high for one clock is obtained with a delay of 1.5 clocks). Next, since data of (1, 1, 0) is preset, a parallel-serial conversion output FF0 that is continuously at a high level for two clocks is obtained.

  Similarly, the parallel-serial conversion output FF0 corresponding to the combination of preset data to the preset terminal PR is obtained. As is clear from FIG. 8G, the parallel-serial conversion output FF0 is not changed, but three parallel digital data are converted in the time axis direction of the clock CK.

  The parallel / serial conversion output FF0 is supplied together with the clock CK to an adder 63 as a multiplexing unit provided in the next stage, and the parallel / serial conversion output FF0 is multiplexed within a time width between the clocks CK and CK. . In this example, output data FF0 converted in parallel and serially is multiplexed on the positive polarity side of the negative polarity clock CK having a duty of approximately 1/4. The multiplexed output signal becomes the digital data signal DO (FIG. 8H).

  Since the digital data signal DO includes digital data obtained by parallel-serial conversion of parallel digital data in the time axis direction in addition to the clock CK functioning as a transmission clock, only one data line 69 is connected from the output terminal 68. This digital data signal DO can be transmitted.

  The decoding circuit 100 for the digital data signal DO has a data decoding unit 150 as shown in FIG. The data decoding unit 150 includes a clock extraction unit 151 for extracting the clock CK from the input digital data signal DO, and a data generation unit 159 for generating three parallel digital data from the input digital data signal DO. The

  The data generation unit 159 extracts a multiple data extraction unit 152 that extracts the output data FF0 converted in parallel and serial from the input digital data signal DO, and a high-speed clock generation unit 153 that generates a high-speed clock NCK that is m times the extracted clock CK. And a data shift unit 154 that generates n (= 3) digital data obtained by sequentially shifting the output data FFO converted in parallel and serially using the high-speed clock NCK by a predetermined clock, and the time axis is shifted. The sampling unit 156 restores the original parallel digital data that has been serial-to-parallel converted by sampling each of the three digital data.

  The clock extraction unit 151 is configured as a buffer unit having a predetermined threshold level Vtha (FIG. 8I). The buffer unit 151 extracts and separates the negative clock CK (FIG. 8I) from the input digital data signal DO. The On the other hand, a buffer unit having a predetermined threshold level Vthb is also used for the multiple data extraction unit 152, and the digital data FF0 (FIG. 8J) converted in parallel and serial is extracted and separated by the buffer unit 152.

  In this example, the high-speed clock generation unit 153 is configured by a PLL, and uses the extracted clock CK (FIG. 8I) to generate m times as many high-speed clocks NCK (FIG. 8K). In this example, a high-speed clock NCK that is four times the clock CK is generated, similarly to the digital data signal output circuit 10 side.

  In this example, the data shift unit 154 is composed of three D-type flip-flops 154A to 154C connected in cascade, and output data FF0 which is a parallel-serial conversion output extracted and separated to the data terminal D of the first-stage flip-flop 154A. Is supplied. The output of each output terminal Q is input to the data terminal D at the next stage.

  The flip-flops 154A to 154C take in the input data at the rising timing of the supplied high-speed clock NCK and output it. As a result, the first stage flip-flop 154A outputs digital data SPc (FIG. 8L) obtained by delaying the extracted and separated digital data FF0 by one clock of the high-speed clock NCK. Actually, the output is delayed by the data processing time as shown in FIG. In this example, the output is delayed by 1/2 clock.

  The digital data SPb (FIG. 8M) delayed by one clock is output from the middle flip-flop 154B, and the digital data SPa (FIG. 8N) delayed by one clock is output from the final flip-flop 154C. .

  By applying such data conversion processing to the extracted and separated digital data FF0, three digital data SPa to SPc whose time axes are sequentially shifted are obtained.

  On the other hand, the extracted and separated clock CK is supplied to the inverter 155, the phase of which is inverted, and in this example, a delayed clock DLCKb (FIG. 8O) delayed by ½ clock is generated.

  Three digital data SPa to SPc whose time axes are sequentially shifted are supplied to the sampling unit 156. The sampling unit 156 has a function of latching, that is, sampling, input data for the interval of the delay clock DLCKb, and includes three D-type flip-flops 156A to 156C.

  The digital data SPc obtained from the first stage flip-flop 154A is supplied to the flip-flop 156A, and similarly, the digital data SPb is supplied to the flip-flop 156B, and the digital data SPa is supplied to the flip-flop 156C. The sampling outputs of the flip-flops 156A to 156C become parallel digital data S0 to S2, and are obtained at the respective output terminals 157a to 157c.

  The above-described delay clock DLCKb is supplied to each of the flip-flops 156A to 156C, and the digital data SPa to SPc are sampled at the rising timing, so that the sampling output at the delay clock DLCKb0 is all zero (0, 0, 0), the sampling output at the next delay clock DLCKb1 becomes (1, 0, 0), and the parallel digital data S0 to S2 are restored. Also in this case, the data is output after being delayed by the data processing time (1/2 clock) to the flip-flops 156A to 156C.

  As described above, even with three parallel digital data, one digital data signal DO is obtained by multiplexing the data corresponding to the parallel digital data after being converted in the time axis direction of the clock (transmission clock) CK. The data line 69 can be used for transmission.

(6) Example of multiplexing the clock CK in the time axis direction when n = 3 (part 2)
This will be described with reference to FIGS. 9 and 10. This embodiment follows the embodiment of (5) described above, and the embodiment of FIG. 7 supplies three parallel digital data directly to the parallel-serial converter 61 functioning as a data converter. However, in the embodiment of FIG. 9, the input three parallel digital data are once encoded, and the encoded data are supplied to the parallel-serial conversion unit 61. Therefore, only the data arrangement input to the parallel-serial converter is different, and the other operations are the same as those in FIG.

  The same parts as those in FIG. 7 are denoted by the same reference numerals, and the description of the configuration and the same operation as in FIG. 8 is omitted. In FIG. 9, in the multiplexing unit 60 constituting the output circuit 10 of the digital data signal, The three parallel digital data S0 to S2 input to the terminals 64a to 64c are encoded by the encoding unit 70. In this example, among the parallel digital data S0 to S2 synchronized with the clock CK, phase inversion processing is performed on each of the lower and upper bit parallel digital data S0 and S2, and the middle bit parallel digital data S1 is The encoding unit 70 performs encoding processing for performing output processing as it is.

  As a result, in the timing chart shown in FIG. 10, the input parallel digital data S0 to S2 (FIGS. 10D to F) are encoded as shown in FIGS. The encoded outputs are ENa to ENc.

  The encoded outputs ENa to ENc are supplied to the parallel / serial conversion unit 61, and output data (output digital data) FF0 (FIG. 10J) subjected to parallel / serial conversion is obtained. For example, when the parallel digital data S0 to S2 are (0, 0, 0), the encoded outputs ENa to ENc are (1, 0, 1). At this time, the rising edge of the delay clock DLCK (FIG. 10B) With reference to the timing, output data FF0 that is at a high level is obtained in a section in which the first and third high-speed clocks NCK (FIG. 10C) are obtained, and the parallel digital data S0 to S2 are (1, 0, 0). In some cases, the encoded outputs ENa to ENc are (0, 0, 1). At this time, output data FF0 is obtained in which only the section in which the third high-speed clock NCK (FIG. 10C) is obtained is at a high level. .

  Since this positive polarity conversion output FF0 which is high level is superimposed on the negative polarity clock CK, as shown in FIG. A multiplexed output signal (digital data signal) DO is obtained.

  The digital data signal DO decoding circuit 100 shown in FIG. In this data decoding unit 150, the only structural difference from the data decoding unit 150 in FIG. 7 is that a decoding unit (decoder) 180 is provided at the output stage of the sampling unit 156. The decoding unit 180 is provided because the parallel digital data S0 to S2 are encoded on the output circuit 10 side, and the encoded digital data ENa to ENc (FIGS. 10S to U) are converted to the original parallel data. Necessary for returning to digital data.

  In the data decoding unit 150, the clock (transmission clock) CK and the output data FF0 are separated from the received digital data signal DO, and the output data FF0 is sequentially shifted in the time axis direction using a four-times high-speed clock NCK. It is converted into three pieces of digital data SPa to SPc (FIGS. 10O to Q). As a result of sampling these three pieces of converted digital data SPa-SPc by the sampling unit 156, encoded outputs ENa-ENc shown in FIGS. 10S-U are generated. This encoded output is the same as the encoded output (FIGS. 10G to I) generated in the encoding process of the output circuit 10 described above.

  The encoded outputs ENa to ENc are decoded by the decoding unit 180 into the original parallel digital data S0 to S2 (FIGS. 10V to X).

  Even when the parallel digital data is once encoded and multiplexed as described above, the parallel digital data (corresponding output data) is multiplexed and transmitted to the clock CK by devising the encoding process. As a result, data lines can be greatly reduced as in the above-described embodiment.

(7) Example of multiplexing in the time axis direction of the clock when n = 3 (part 3)
This will be described with reference to FIGS. 11 and 12. In this embodiment, the parallel digital data is converted in the time axis direction and multiplexed on the clock CK using the (n + 1) -bit clock synchronous binary counter.

  In the digital data transmission system shown in FIG. 11, the digital data signal output circuit 10 side has a digital data multiplexing unit 80. In this embodiment, a 4-bit binary counter 81 is used as the multiplexing unit 80. Furthermore, inverters 83A to 83C that invert the three parallel digital data S0 to S2 supplied to the input terminals 82a to 82c, an inverter 85 that inverts the phase of the clock CK supplied to the input terminal 84, and the clock CK A clock multiplier 86 that generates a clock having a predetermined multiple, an inverter 87 that inverts the carry output Cy of the binary counter 81, and a multiplexer 88 that multiplexes the phase-inverted carry output Cy bar and the clock CK in the time axis direction. Thus, the multiplexing unit 80 is configured.

  Since the three parallel digital data S0 to S2 (FIGS. 12C to E) synchronized with the clock CK shown in FIG. 12A are handled, the binary counter 81 is a 4-bit synchronous counter. As this binary counter 81, for example, a commercial product having a model number of “SN74163” can be used.

  As is well known, this binary counter 81 is provided with four input terminals A to D and four output terminals QA to QD. The carry output Cy is fed back to the enable terminal ENP after being inverted in phase by the inverter 87. The remaining enable terminal ENT, clear terminal CL, and input terminal D are used while being fixed at a constant level (high level).

Parallel digital data S0 to S2 whose phases are inverted by inverters 83A to 83C are supplied to input terminals A, B, and C of the binary counter 81. Further, the clock CK whose phase is inverted by the inverter 85 is supplied to the load terminal LD bar. The clock multiplying unit 86 has a PLL configuration, and when three parallel digital data are regarded as three-bit digital data, eight outputs of three bits can be converted in the time axis direction of the clock CK. , (2 ⁿ +1) times faster clock NCK is generated (FIG. 12B). The high-speed clock NCK is supplied to the clock terminal (CK) of the binary counter 81.

  As is well known, in the binary counter 81, when the load terminal LD bar is at a low level, input data is loaded to the input terminals A to D at the rising edge of the high-speed clock NCK. When the enable terminal ENP is at a high level, the binary counter 81 performs a count-up operation, and when the enable terminal ENP is at a low level, the count-up operation is not performed.

  When the other enable terminal ENT is also at the high level, the count-up operation is performed, but when the other enable terminal ENT is at the low level, the count-up operation is stopped. At this low level, even if the output is all 1, the carry output is inverted to the low level.

  When the data at output terminals QA to QD are all “1”, carry output Cy is “1”. When the clear terminal CL is at a low level, the data of the output terminals QA to QD are all “0”. However, since the enable terminal ENT and the clear terminal CL are both fixed at a high level in the configuration of FIG. 11, the count process is executed without being affected by these.

  Here, for convenience of explanation, A to D and QA to QD are all handled as input data or output data.

  The operation of the binary counter 81 regards the input three parallel digital data S0 to S2 as 3-bit digital data, converts this into 4-bit digital data QA to QD, and carries out the carry output at that time. By using Cy, the 3-bit digital data S0 to S2 are converted in the time axis direction of the clock CK. Here, processing is performed in which the parallel digital data S0 is regarded as the lower bits and the parallel digital data S2 is regarded as the upper bits.

  As a result, when the 3-bit input is (0, 0, 0), the output data CD (inverted output Cy bar) of the inverter 87 is zero, and when the 3-bit input is (1, 0, 0), the inverter 87 is output. The output data CD is converted into output data corresponding to the combination of input bits so that output data that becomes low level only during the second pulse interval of the high-speed clock NCK is obtained.

  A specific example will be described with reference to FIGS. When the 3-bit inputs S0 to S2 are (0, 0, 0) as shown in FIG. 13A, the inverting input is (1, 1, 1), and as shown in FIG. 12B, the high-speed clock NCKa1 Since the data (1, 1, 1) loaded to the input terminals A to C at the low level becomes the 4-bit outputs QA to QD at the rising timing of the high-speed clock NCKa2, the 4-bit outputs QA to QD at this time The QD is all “1” as shown in FIG. 13A, and as a result, the carry output Cy is “1” and its inverted output Cy bar is “0”. When the inverted output Cy bar becomes “0”, that is, low level, the binary counter 81 stops counting, so when the 3-bit input is (0, 0, 0), the counting operation is not performed at all, and the output data is not The high level is maintained by the action of the enable terminal ENT.

  Since this output data CD is superimposed on the clock CK by the OR circuit 88 in this example constituting the multiplexing unit, only the positive clock CKa is output from the digital data signal DO as the output signal.

  Next, when the 3-bit inputs S0 to S2 are (1, 0, 0), the inverted input is (0, 1, 1) as shown in FIG. 13B, as shown in FIG. Since the data (0, 1, 1) loaded to the inputs A to C at the low level of the high-speed clock NCKb1 becomes the 4-bit outputs QA to QD at the rising timing of the high-speed clock NCKb2, the four bits at this time The outputs QA to QD are (0, 1, 1, 1) as shown in FIG. As a result, the carry output Cy is inverted to “0”, and the inverted output Cy bar becomes “1”. When the inverted output Cy bar becomes “1”, that is, high level, the binary counter 81 starts the count operation, and therefore performs the count-up operation at the rising edge of the high-speed clock NCKb.

  As a result, as shown in FIG. 13, the 4-bit outputs QA to QD are (1, 1, 1, 1), and the carry output Cy is inverted to “1” again. Accordingly, since the inverted output Cy bar becomes “0”, the binary counter 81 performs the count-up operation only once and then stops again.

  As a result, the inverted output Cy bar is inverted to a high level by one pulse of the high-speed clock NCK (see FIG. 12F and CDb). That is, it is converted into output data CDb for one pulse and output.

  Here, a delay at the time of the counting process occurs with the counting process of the binary counter 81 or the like. Considering this delay amount DL (1/2 clock in the figure), the output data CD is delayed by 1/2 clock and output as shown in FIG. 12F. Since the output data CDb is superimposed on the clock CKa by the adder 88, the digital data signal DO, which is an output signal, is superimposed on the positive clock CK and the output data CDb by one clock as shown in FIG. 12G. Will be output.

  Further, at the next clock timing, as shown in FIG. 13C, since the 3-bit inputs S0 to S2 are (0, 1, 0), the inverted input is (1, 0, 1). As shown in FIG. 12, the data (0, 1, 0) loaded to the input terminals A to C at the low level of the high-speed clock NCKc1 becomes the 4-bit outputs QA to QD at the rising timing of the high-speed clock NCKc2. At this time, the 4-bit outputs QA to QD are (1, 0, 1, 1). As a result, the carry output Cy is inverted to “0”, and the inverted output Cy bar is set to “1”. When the inverted output Cy bar becomes “1”, that is, high level, the binary counter 81 starts the count operation, and therefore performs the count-up operation at the rising edge of the high-speed clock NCKc.

  As a result of the count-up operation, the 4-bit outputs QA to QD are counted up to (0, 1, 1, 1) at the first high-speed clock NCKc2, as shown in FIG. It remains “0”. Accordingly, the inverted output Cy bar also remains “1”, whereby the second count-up process is performed. Since the 4-bit outputs QA to QD are all “1” by the second count-up process, the carry output Cy is inverted to “1” again at the same time as the count-up process is completed. Accordingly, since the inverted output Cy bar becomes “0”, the binary counter 81 performs the count-up operation only twice and then stops again.

  As a result, the inverted output Cy bar is inverted to the high level by two pulses of the high-speed clock NCKb as shown in FIG. That is, it is converted into output data CDc for two pulses and output. Since this output data CDc which is an inverted output is superimposed on the clock CK by the OR circuit 88, as shown in FIG. 12, the digital data signal DO which is the output signal is converted to the positive clock CK and the output data CDc (2 clocks). Minute) is superimposed and output.

  Thus, by the count-up process of the binary counter 81, the three parallel digital data S0 to S2 are converted into output data CD corresponding to the data contents, and this output data CD is superimposed on the time axis direction of the clock CK. The digital data signal DO is used. This digital data signal DO is transmitted to the LSI 2 side through the output terminal 89 using one data line 90.

  Next, the digital data signal decoding circuit 100 will be described with reference to FIGS.

  The decoding circuit 100 includes a data decoding unit 160. The data decoding unit 160 includes a clock extraction unit 162 that extracts a clock (transmission clock) CK from the received digital data signal DO, and a data generation unit 182 that generates parallel digital data S0 to S2 from the digital data signal DO. .

  The data generation unit 182 includes a 4-bit binary counter 161 as illustrated. Further, the data generation unit 182 includes a data extraction unit 168 that extracts the output data CD from the received digital data signal DO, a clock multiplication unit 166 that generates the high-speed clock NCK, and three data output from the binary counter 161. The serial / parallel converter 170 functions as a data converter that converts the counter output into three parallel digital data, and the inverter 172 that supplies the inverted clock CK bar to the load terminal LD bar of the binary counter 161.

  The binary counter 161 is the same as the binary counter used in the digital data signal output circuit 10. The clock extraction unit 162 includes an AND circuit 163 to which the digital data signal DO input to the terminal 175 is supplied, a D-type flip-flop 164 that outputs the digital data signal DO in synchronization with a high-speed clock NCK described later, and an output thereof. A digital data signal DO bar which is composed of an inverter 165 whose phase is inverted and which is delayed from the inverter 165 by one clock NCK and whose phase is inverted is obtained. This digital data signal DO bar is supplied to the AND circuit 163. Therefore, the original clock CK can be extracted and separated by the AND circuit 163 (FIG. 12I).

  In this example, the clock multiplying unit 166 is configured by a PLL, and is a clock that is nine times the transmission clock CK included in the input digital data signal DO, and extracts a high-speed clock NCK (FIG. 12H) synchronized with the transmission clock CK. To be separated.

  The extracted high-speed clock NCK is supplied to the D-type flip-flop 164, and in this example, a digital data signal DO delayed by one clock is output, and this and the input digital data signal DO itself constitute the data extraction unit 168. This is supplied to the AND circuit 167. As a result, the output data CD itself is output from the AND circuit 167 (FIG. 12J). The extracted output data CD is supplied to the enable terminal ENP of the binary counter 161 as an enable signal for count-up operation.

  The input terminals A to D of the binary counter 161 are all fixed at a low level, and the other enable terminal ENT and clear terminal CL are both fixed at a high level.

  The binary counter 161 is loaded with data (all zeros) of the input terminals A to D at the falling edge of the extracted inverted clock CK bar, and counts up in synchronization with the rising edge of the high-speed clock NCK supplied to the clock terminal (CK). Is done.

  As a result, the count-up operation is performed in synchronization with the high-speed clock NCK only during the period when the output data CD is high level with reference to the loaded data, and the data output when the output data CD is counted up during the low level period. QA to QD are held as they are.

  Therefore, as shown in section 1 of FIG. 12, when the output data CD is zero, the count-up operation is not performed. As a result, the output data QA to QD of the binary counter 161 is all zero (0, 0, 0, 0). In this example, since the lower 3 bits are used as the output data QA to QC, the output data QA to QC is (0, 0, 0).

When the output data CD is at the high level for one clock of the high-speed clock NCK,
As shown in section 2 of FIG. 12, the count-up operation is performed only during this high level period, that is, by one clock, and the count-up operation is stopped until the next clock CK falls. Therefore, only the counted up output data QA becomes high level, and the other output data QB to QD all remain at low level. Therefore, the output data QA to QD are (1, 0, 0, 0). Since the lower 3 bits are used as output data, the output data QA to QC are (1, 0, 0).

  In section 3 in FIG. 12 in which the output data D is at the high level for two clocks of the high-speed clock NCK, the count-up operation is performed only during the high-level period of the high-speed clock NCK (for two clocks). The QC is (0, 1, 0).

  The output data QA to QC are supplied to a D-type flip-flop 170 that functions as a data conversion unit. That is, the output data QA is supplied to the data input terminal D of the flip-flop 170A, the output data QB is supplied to the flip-flop 170B, and the output data QC is supplied to each data input terminal D of the flip-flop 170C.

  As a result, the loaded output data QA to QC are sampled in synchronization with the clock CK supplied to each (N, O, P in FIG. 12). Since the sampling flip-flops 170A to 170C are delayed by about one pulse of the high-speed clock NCK, the timing of T sampling by the clock CK is delayed by one clock. Therefore, sampling outputs S0 to S2 (0, 0, 0) of the output data QA to QC (0, 0, 0) in the section 1 are obtained in the section 2 as shown in FIG. In the same manner, parallel digital data S0 to S2 having sampling outputs are obtained in a state where the data is sequentially shifted by one section.

  By converting the three parallel digital data in the time axis direction of the clock CK in this way and then multiplexing the converted data on the clock CK, the three parallel digital data can be used even if one data line 90 is used. The data S0 to S2 can be transmitted simultaneously, and the parallel digital data S0 to S2 multiplexed on the clock CK can be extracted and separated from the transmitted digital data signal DO.

(8) Example of multiplexing in the time axis direction of the clock when n = 3 (part 4)
FIG. 14 is a modification of FIG. 11 and the same parts as those in FIG.

  The output circuit 10 is different from FIG. 11 in that the input three parallel digital data are encoded in advance by the encoding unit 190, and the encoded three outputs ENa to ENc are respectively converted into 3-bit digital data. This is the point that the input data of the 4-bit binary counter 81 is taken.

  In this example, when the input parallel digital data S0 to S2 are (0, 0, 0), the encoded outputs QA to QC are (1, 0, 1), and the parallel digital data S0 to S2 are (1, 1, When 0, 1), the encoded outputs QA to QC are encoded so as to be (0, 0, 0) (FIGS. 16C to H).

  Since the encoded output QA to QC is a 3-bit input and the 4-bit binary counter 81 operates, it is converted into output data CD having a pulse width corresponding to the combination of 3 bits. As a result, the output data CD (carry output Cy) becomes FIG. 16I, and the output data CD bar obtained by inverting the phase of the output data CD is multiplexed with the clock CK to obtain the digital data signal DO shown in FIG. 16J. This digital data signal DO is transmitted to the other LSI 2 side through one data line 90.

  Even in the decoding circuit 100 for the digital data signal DO, the difference from FIG. 11 is that a decoding unit (decoder) 191 is provided at the final stage. The input output data CD bar is temporarily returned to the 4-bit binary outputs QA to QC by the 4-bit binary counter 161 and the D-type flip-flops 170A to 170C having the data sampling function in the subsequent stage (FIG. 16N, O, P). Further, the binary outputs QA to QC thus returned are converted back into encoded outputs ENa to ENc (FIG. 16M, Q to S). By decoding (decoding) the inversely converted encoded outputs ENa to ENc by the decoding unit (decoder) 181, the original parallel digital data S0 to S2 are restored (FIGS. 16T to U).

  Also in this embodiment, three digital data S0 to S2 can be simultaneously transmitted using one data line 90 as in FIG. 11, and the parallel digital data S0 to S2 can be restored.

  In the embodiment described above, the case where n = 2 and n = 3 is illustrated, but n may be 4 or more.

  The present invention can be applied to a data transmission system in which a plurality of LSIs mounted on an IC substrate are connected to exchange data.

It is a systematic diagram of the principal part which shows the Example of the transmission system of the digital data signal which concerns on this invention (the 1). It is a wave form diagram with which the operation | movement description is provided. It is a systematic diagram of the principal part which shows the Example of the transmission system of the digital data signal which concerns on this invention (the 2). It is a wave form diagram with which the operation | movement description is provided. It is a systematic diagram of the principal part which shows the Example of the transmission system of the digital data signal which concerns on this invention (the 3). It is a wave form diagram with which the operation | movement description is provided. It is a systematic diagram of the principal part which shows the Example of the transmission system of the digital data signal which concerns on this invention (the 4). It is a wave form diagram with which the operation | movement description is provided. It is a systematic diagram of the principal part which shows the Example of the transmission system of the digital data signal which concerns on this invention (the 5). It is a wave form diagram with which the operation | movement description is provided. It is a systematic diagram of the principal part which shows the Example of the transmission system of the digital data signal which concerns on this invention (the 6). It is a wave form diagram with which the operation | movement description is provided. It is a figure which shows the input / output data relationship used for the operation | movement description. It is a systematic diagram of the principal part which shows the Example of the transmission system of the digital data signal which concerns on this invention (the 7). It is a wave form diagram with which the operation | movement description is provided. It is a systematic diagram which shows an example of the data transmission system which uses for description of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Output circuit, 100 ... Decoding circuit, 20, 30, 50, 60, 80 ... Multiplexing part, 110, 120, 140, 150, 160 ... Data decoding part,
Data generation unit, clock extraction unit, 22 ... D / A conversion unit, 102 ... A / D conversion unit, 42 ... encoding unit (encoder), 126 ... decoding unit (decoder), 3 , 16, 36, 57, 69, 90 ... data lines, 1, 2 ... LSI

Claims (54)

A digital data signal transmission method comprising the steps of synchronizing n (n ≧ 2) parallel digital data with a clock and multiplexing the n parallel digital data on the clock. The multiplexing step for multiplexing the parallel digital data includes:
2. The method of transmitting a digital data signal according to claim 1, wherein the step of multiplexing in the amplitude direction of the clock is performed. The multiplexing step is:
D / A converting the n digital data,
Sampling D / A converted analog data with the clock;
3. The digital data signal transmission method according to claim 2, further comprising the step of multiplexing the sampled analog data in an amplitude direction of the clock. The multiplexing step is:
Encoding the parallel digital data;
D / A converting the encoded digital data;
Sampling D / A converted analog data with the clock;
3. The digital data signal transmission method according to claim 2, further comprising the step of multiplexing the sampled analog data in an amplitude direction of the clock. The multiplexing step is:
2. The method of transmitting a digital data signal according to claim 1, wherein the step of multiplexing in the time axis direction of the clock is performed. 6. The digital data signal transmission method according to claim 5, wherein the n parallel digital data are multiplexed in a time axis direction by changing a pulse width of the parallel digital data multiplexed on the clock. The multiplexing step is:
Encoding the parallel digital data;
Sampling a plurality of encoded digital data with a plurality of delay clocks associated with the clock;
7. The digital data signal transmission method according to claim 6, further comprising the step of multiplexing a plurality of sampled digital data in a time axis direction of the clock. The multiplexing step is:
Converting the parallel digital data in the time axis direction of the clock using the clock and a clock of m times (m ≧ n + 1) thereof;
7. The digital data signal transmission method according to claim 6, further comprising the step of multiplexing a plurality of digital data converted in the time axis direction in the time axis direction of the clock. The multiplexing step is:
Encoding the parallel digital data;
Converting the plurality of encoded digital data into the time axis direction of the clock using the clock and a clock of m times (m ≧ n + 1) thereof;
7. The digital data signal transmission method according to claim 6, further comprising the step of multiplexing a plurality of digital data converted in the time axis direction in the time axis direction of the clock. The multiplexing step is:
Considering the parallel digital data as n-bit digital data, and performing (n + 1) -bit binary count processing to convert the parallel digital data in the time axis direction of the clock;
7. The digital data signal transmission method according to claim 6, further comprising the step of multiplexing the plurality of converted digital data in a time axis direction of the clock. In the step of converting the parallel digital data in the time axis direction of the clock,
11. The digital data transmission method according to claim 10, wherein the parallel digital data is converted in a time axis direction of the clock using a high-speed clock of (2 ⁿ +1) times or more with respect to the clock. The multiplexing step is:
Encoding the parallel digital data;
The encoded parallel n-bit digital data is regarded as n-bit digital data and (n + 1) -bit binary count processing is performed to convert the parallel digital data in the time axis direction of the clock; ,
7. The digital data signal transmission method according to claim 6, further comprising the step of multiplexing the plurality of converted digital data in a time axis direction of the clock. In the step of converting the parallel digital data in the time axis direction of the clock,
13. The digital data transmission method according to claim 12, wherein the parallel digital data is converted in a time axis direction of the clock using a high-speed clock of (2 ⁿ +1) times or more with respect to the clock. A data decoding unit that is synchronized with the transmission clock and is supplied with a digital data signal in which n-bit parallel digital data is multiplexed on the transmission clock;
A digital data signal decoding method, wherein the data decoding unit decodes the digital data signal into the n-bit parallel digital data.   15. The method of decoding a digital data signal according to claim 14, wherein the parallel digital data is multiplexed in the amplitude direction of the transmission clock. The decoding process step in the data decoding unit is as follows:
Receiving a digital data signal in which n (n ≧ 2) parallel digital data are multiplexed on a transmission clock, and extracting the transmission clock from the received digital data signal;
16. The digital data signal decoding method according to claim 15, further comprising: a digital data generation step of decoding the digital data signal based on the extracted transmission clock to generate n parallel digital data. . The parallel digital data generation step includes:
17. The digital data signal decoding method according to claim 16, wherein the digital data signal is A / D converted based on the transmission clock. The parallel digital data generation step includes:
A / D converting the parallel digital data with a delayed transmission clock associated with the transmission clock;
16. The method for decoding a digital data signal according to claim 15, further comprising a step of decoding a plurality of A / D converted digital data. 15. The digital data signal decoding method according to claim 14, wherein the parallel digital data is multiplexed in a time axis direction of the transmission clock. 20. The method of decoding a digital data signal according to claim 19, wherein the n parallel digital data are multiplexed in a time axis direction by changing a pulse width of the parallel digital data multiplexed on the clock. The step of generating the parallel digital data multiplexed in the time axis direction is as follows:
Sampling with a plurality of delayed transmission clocks associated with the transmission clock extracted from the received digital data signal;
20. The method for decoding a digital data signal according to claim 19, further comprising the step of decoding a plurality of digital data obtained by sampling into the parallel digital data. The step of generating the parallel digital data multiplexed in the time axis direction is as follows:
From the received digital data signal, generating a transmission clock and parallel digital data multiplexed in the time axis direction with respect to the transmission clock;
Generating m times (m ≧ n + 1) transmission clocks from the extracted transmission clocks;
Obtaining m parallel digital data obtained by sequentially shifting the parallel digital data in the time axis direction based on the m times transmission clock;
20. The digital data signal according to claim 19, further comprising the step of: sampling the m parallel digital data thus shifted with the transmission clock to obtain n parallel digital data converted on the original time axis. Decryption method. The step of generating the parallel digital data multiplexed in the time axis direction is as follows:
Generating a transmission clock and encoded parallel digital data multiplexed in the time axis direction with respect to the transmission clock from the received digital data signal;
Generating m times (m ≧ n + 1) transmission clocks from the extracted transmission clocks;
Obtaining m parallel digital data obtained by sequentially shifting the parallel digital data in the time axis direction based on the m times transmission clock;
Sampling the m parallel digital data thus shifted with the transmission clock to obtain n parallel digital data converted on the original time axis;
20. The method for decoding a digital data signal according to claim 19, further comprising the step of decoding the n parallel digital data. The step of generating the parallel digital data multiplexed in the time axis direction is as follows:
Extracting a transmission clock from the received digital data signal;
Extracting parallel digital data multiplexed in the time axis direction with respect to the transmission clock from the received digital data signal;
(N + 1) -bit binary count processing is performed on the extracted parallel digital data, thereby obtaining n parallel digital data corresponding to the pulse width of the parallel digital data;
20. The n parallel digital data is sampled with the transmission clock to obtain n parallel digital data converted on the original time axis. Decryption method. In the step of converting the parallel digital data in the time axis direction of the clock,
25. The digital data decoding method according to claim 24, wherein the extracted parallel digital data is converted into n parallel digital data using a high-speed clock that is (2 ⁿ +1) times or more of the clock. . The step of generating the parallel digital data multiplexed in the time axis direction is as follows:
Extracting a transmission clock from the received digital data signal;
Extracting parallel digital data multiplexed and encoded in the time axis direction with respect to the transmission clock from the received digital data signal;
Obtaining n encoded parallel digital data corresponding to the pulse width of the parallel digital data by performing (n + 1) -bit binary count processing on the extracted parallel digital data;
Sampling the n parallel digital data with the transmission clock to obtain n encoded parallel digital data converted on the original time axis;
20. The method for decoding a digital data signal according to claim 19, further comprising the step of decoding the n parallel digital data. In the step of converting the parallel digital data in the time axis direction of the clock,
27. The digital data decoding method according to claim 26, wherein the parallel digital data extracted is converted in a time axis direction of the clock using a high-speed clock of (2 ⁿ +1) times or more with respect to the clock. . A multiplexing unit to which a clock and n (n ≧ 2) parallel digital data synchronized with the clock are respectively supplied;
A digital data signal output circuit characterized in that a digital data signal in which the parallel digital data is multiplexed in the amplitude direction of the clock is output by the multiplexing unit. The multiplexing unit is
A D / A converter that is supplied with the clock and parallel digital data and adds the parallel digital data in the amplitude direction of the clock;
A sampling unit that samples the analog output data output from the D / A conversion unit;
29. The digital data signal output circuit according to claim 28, further comprising: an adder that adds the clock to the sampled analog output data. 30. The digital data signal output circuit according to claim 29, wherein an adder is used as said adder. The multiplexing unit is
An encoding unit for encoding the parallel digital data;
A D / A converter for D / A converting the encoded digital data;
A sampling unit for sampling D / A converted analog output data with the clock;
30. The digital data signal output circuit according to claim 29, further comprising an adder that adds the sampled analog output data in an amplitude direction of the clock. A multiplexing unit to which a clock and n (n ≧ 2) parallel digital data synchronized with the clock are respectively supplied;
A digital data signal output circuit, wherein the multiplexing unit outputs a digital data signal in which the parallel digital data is multiplexed in the time axis direction of the clock. 33. The digital data signal output circuit according to claim 32, wherein the n parallel digital data are multiplexed in a time axis direction by changing a pulse width of the parallel digital data. The multiplexing unit is
An encoding unit for encoding the parallel digital data;
A sampling unit that samples a plurality of encoded digital data with a plurality of delay clocks related to the clock;
34. The digital data signal output circuit according to claim 33, further comprising: an adder that adds a plurality of sampled digital data in a time axis direction of the clock. The multiplexing unit is
A data converter for converting the parallel digital data in the time axis direction of the clock using the clock and a clock of m times (m ≧ n + 1) thereof;
34. The digital data signal output circuit according to claim 33, further comprising a multiplexing unit that multiplexes a plurality of digital data converted in the time axis direction in the time axis direction of the clock. The multiplexing unit is
An encoding unit for encoding the parallel digital data;
A data converter that converts a plurality of encoded digital data into the time axis direction of the clock using the clock and a clock of m times (m ≧ n + 1) thereof;
34. The digital data signal output circuit according to claim 33, further comprising a multiplexing unit that multiplexes a plurality of digital data converted in the time axis direction in the time axis direction of the clock. The multiplexing unit is
A data conversion unit including a binary counter that converts the parallel digital data in the time axis direction of the clock by regarding the parallel digital data as n-bit digital data and performing (n + 1) -bit binary count processing;
34. The digital data signal output circuit according to claim 33, further comprising a multiplexing unit that multiplexes the plurality of converted digital data in the time axis direction of the clock. In the data conversion unit that converts the parallel digital data in the time axis direction of the clock,
38. The digital data output circuit according to claim 37, wherein the parallel digital data is converted in the time axis direction of the clock using a high-speed clock of (2 ⁿ +1) times or more with respect to the clock. The multiplexing unit is
An encoding unit for encoding the parallel digital data;
A binary counter that converts the parallel digital data in the time axis direction of the clock by treating the encoded parallel n-bit digital data as n-bit digital data and performing (n + 1) -bit binary count processing. A data converter having
34. The digital data signal output circuit according to claim 33, further comprising a multiplexing unit that multiplexes the plurality of converted digital data in the time axis direction of the clock. In the data conversion unit that converts the parallel digital data in the time axis direction of the clock,
40. The digital data output circuit according to claim 39, wherein the parallel digital data is converted in the time axis direction of the clock using a high-speed clock of (2 ⁿ +1) times or more with respect to the clock. A data decoding unit to which a digital data signal in which parallel digital data is multiplexed in a transmission clock is supplied;
The data decoding unit separates the transmission clock and uses the separated transmission clock to decode the parallel digital data multiplexed in the amplitude direction of the transmission clock. Digital data signal decoding circuit. The data decoding unit
A transmission clock extracting unit that receives a digital data signal in which n (n ≧ 2) parallel digital data is multiplexed on the transmission clock, and extracts the transmission clock from the received digital data signal;
42. The digital data signal decoding circuit according to claim 41, further comprising a data generation unit that decodes the digital data signal based on the extracted transmission clock to generate n parallel digital data. The parallel digital data generator is
43. The digital data signal decoding circuit according to claim 42, wherein the digital data signal decoding circuit is an A / D converter for A / D converting the digital data signal based on the transmission clock. The parallel digital data generator is
An A / D converter for A / D converting the parallel digital data with a delayed transmission clock associated with the transmission clock;
43. The digital data signal decoding circuit according to claim 42, further comprising: a decoding unit that decodes the plurality of digital data subjected to A / D conversion. A data decoding unit to which a digital data signal in which parallel digital data is multiplexed in a transmission clock is supplied;
The data decoding unit separates the transmission clock and uses the separated transmission clock to decode the parallel digital data multiplexed in the time axis direction of the transmission clock. A digital data signal decoding circuit. 46. The digital data signal decoding circuit according to claim 45, wherein the n parallel digital data are multiplexed in a time axis direction by changing a pulse width of the parallel digital data multiplexed on the clock. The data decoding unit
A transmission clock extraction unit that receives a digital data signal in which n (n ≧ 2) parallel digital data is multiplexed on the transmission clock, and extracts the transmission clock from the received digital data signal;
45. The digital data signal decoding circuit according to claim 44, further comprising a data generation unit that decodes the digital data signal based on the extracted transmission clock to generate n parallel digital data. The parallel digital data generator is
A sampling unit for sampling with a plurality of delayed transmission clocks related to the transmission clock extracted from the digital data signal;
48. The digital data signal decoding circuit according to claim 47, further comprising: a decoding unit that decodes a plurality of digital data obtained by sampling into the parallel digital data. The parallel digital data generator is
A transmission clock extraction unit that extracts a transmission clock from the received digital data signal;
A multiple data extraction unit for extracting parallel digital data multiplexed in the time axis direction of the transmission clock from the received digital data signal;
A clock generation unit for generating a transmission clock m times (m ≧ n + 1) from the extracted transmission clock;
A data shift unit for obtaining m parallel digital data obtained by sequentially shifting the parallel digital data in the time axis direction based on the m times transmission clock;
48. The digital data according to claim 47, further comprising: a sampling unit that samples the shifted m parallel digital data with the transmission clock and obtains n parallel digital data converted on the original time axis. Signal decoding circuit. The parallel digital data generator is
A transmission clock extraction unit that extracts a transmission clock from the received digital data signal;
Multiplex data extraction unit for extracting encoded parallel digital data multiplexed in the time axis direction with respect to the transmission clock;
A clock generation unit for generating a transmission clock m times (m ≧ n + 1) from the extracted transmission clock;
A data shift unit for obtaining m parallel digital data obtained by sequentially shifting the parallel digital data in the time axis direction based on the m times transmission clock;
A sampling unit that samples the shifted m parallel digital data with the transmission clock and obtains n parallel digital data converted on the original time axis;
48. The digital data signal decoding circuit according to claim 47, further comprising: a decoding unit that decodes the n pieces of parallel digital data. The parallel digital data generator is
A transmission clock extraction unit that extracts a transmission clock from the received digital data signal;
A parallel digital data extraction unit for extracting parallel digital data multiplexed in the time axis direction with respect to the transmission clock from the received digital data signal;
A data conversion unit having a binary counter that obtains n parallel digital data corresponding to the time axis width of the parallel digital data by performing (n + 1) -bit binary count processing on the extracted multiplexed data; ,
48. The digital data signal according to claim 47, further comprising a sampling unit that samples the n parallel digital data with the transmission clock to obtain n parallel digital data converted on the original time axis. Decoding circuit. In the binary counter provided in the data converter,
52. The digital data signal decoding circuit according to claim 51, wherein a high-speed clock of (2 ⁿ +1) times or more with respect to the clock is supplied. The parallel digital data generator is
A transmission clock extraction unit that extracts a transmission clock from the received digital data signal;
A multiplexed data extraction unit that extracts parallel digital data that is multiplexed and encoded in the time axis direction with respect to the transmission clock from the received digital data signal;
A binary counter that obtains n encoded parallel digital data corresponding to the time axis width of the parallel digital data by performing binary count processing of (n + 1) bits on the extracted multiplexed data. A data converter;
A sampling unit that samples the n parallel digital data with the transmission clock and obtains n encoded parallel digital data converted on the original time axis; and
48. The digital data signal decoding circuit according to claim 47, further comprising: a decoding unit that decodes the n pieces of parallel digital data. In the binary counter provided in the data converter,
54. The digital data signal decoding circuit according to claim 53, wherein a high-speed clock of (2 ⁿ +1) times or more with respect to the clock is supplied.

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