JP2005079699A - Video, audio signal processing apparatus, and video display, audio output apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video display, audio output apparatus such as a television receiver having a display device with fixed pixels that solves a delay of a displayed video image from an audio signal depending on the presence of a pixel number conversion circuit (scaler) for matching pixel arrangement of a video signal with pixel arrangement of the display device by digital signal processing and the presence of a high image quality signal processing circuit for bringing high image quality to the video image by digital signal processing. <P>SOLUTION: The video display, audio output apparatus including: the display device 7 with the fixed pixels; the scaler 5 for matching the pixel arrangement of the video signal in the received video signal and audio signal with the pixel arrangement of the display device 7 by the digital signal processing; and the high image quality signal processing circuit 4 for bringing high image quality to the video image through the digital signal processing, is provided with: a storage means 15 for storing a time required for the processing by the scaler 5 and the high image quality signal processing circuit 4; and a delay means 10 for delaying the audio signal by the time stored in the storage means 15. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a video / audio signal processing apparatus and a video display / audio output apparatus suitable for application to, for example, a television receiver having a fixed pixel display device.

  An image display device that displays an image on a fixed pixel display device such as a plasma display or a liquid crystal display has a pixel number conversion circuit (scaler) that adjusts the pixel arrangement of an input video signal to the pixel arrangement of the display device by digital signal processing. (For example, refer to Patent Document 1).

  In recent years, television receivers having fixed pixel display devices such as plasma televisions and liquid crystal televisions have become widespread. As such a television receiver, in addition to the scaler, a circuit provided with a circuit for improving the image quality by digital signal processing has appeared.

  FIG. 1 shows a configuration example of a video / audio signal processing system of a conventional television receiver having a fixed pixel display device. A television signal is sent from an antenna 1 that receives radio waves of an analog television broadcast to a tuner 2 of the television receiver. The television signal of the channel selected by the tuner 2 is sent to the demodulation circuit 3, and the demodulation circuit 3 demodulates the television signal to generate an analog video signal (NTSC signal with 483 effective scanning lines) and an analog audio signal. obtain.

  The demodulated analog video signal is sent to the image quality enhancement signal processing circuit 4. Although not shown, the high image quality signal processing circuit 4 digitally converts the analog video signal by the ITU 4: 2: 2 method (the number of effective pixels per scanning line of the luminance signal is set to 720 pixels). A / D converter is included, and a circuit for improving the image quality by digital signal processing (for example, a circuit that performs progressive conversion of an interlace signal) is included in the subsequent stage.

  The digital video signal that has been subjected to digital signal processing by the image quality enhancement signal processing circuit 4 is sent to a scaler (pixel number conversion circuit) 5. In the scaler 5, digital signal processing is performed to match the pixel arrangement of the input digital video signal with the pixel arrangement of a fixed pixel panel (plasma display panel or liquid crystal display panel) 7 included in the television receiver.

  Specifically, for example, if the pixel arrangement of the fixed pixel panel 7 is 1024 pixels in the horizontal direction × 768 pixels in the vertical direction, the scaler 5 has the number of effective pixels 720 pixels / number of effective scanning lines 483 per scanning line of the luminance signal. One input digital video signal is converted into a digital video signal of 1024 effective pixels per scanning line and 768 effective scanning lines per luminance line.

  The digital video signal whose number of pixels has been converted by the scaler 5 is sent to a display driver 6 that drives the fixed pixel panel 7. The display driver 6 applies a voltage corresponding to the input digital video signal to the fixed pixel panel 7.

On the other hand, the analog audio signal demodulated by the demodulation circuit 3 is amplified by the audio amplification circuit 8 and then output from the speaker 9.
JP 2001-242820 A (paragraph numbers 0003 to 0010, FIG. 4)

  However, in this conventional television receiver, it takes time for the digital signal processing in the high image quality signal processing circuit 4 and the scaler 5 (the time may be about 100 milliseconds depending on the processing contents). Therefore, a phenomenon occurs in which the video displayed on the fixed pixel panel 7 is delayed with respect to the sound output from the speaker 9 (the sound can be heard faster).

  In the natural world, even if the sound (the sound generated from the object being viewed) is delayed with respect to the image (the object being viewed by a human being), the sound is not heard more quickly. Therefore, such a phenomenon gives an unpleasant feeling to the viewer of the program.

  In view of the above, the present invention provides a video display / audio output device such as a television receiver having a fixed pixel display device. The problem was to eliminate the phenomenon of delay.

  In order to solve this problem, the applicant of the present application has disclosed a pixel number conversion circuit (scaler) that adjusts a pixel arrangement of a video signal of input video signals and audio signals to a pixel arrangement of a display device of fixed pixels by digital signal processing. A video / audio signal processing apparatus comprising: storage means for storing the time required for processing by the scaler; and delay means for delaying the audio signal by the time stored in the storage means A processing device is proposed.

  In this video / audio signal processing apparatus, the time required for the digital signal processing by the scaler for the video signal of the input video signal and audio signal is stored in advance in the storage means. Then, the audio signal is delayed by the delay means by the time stored in the storage means, so that the output timing of the video signal and the output timing of the audio signal are matched.

  Therefore, if this video / audio signal processing device is installed in a video display / audio output device such as a television receiver having a fixed pixel display device, the video displayed on the display device is not compatible with audio due to the presence of the scaler. Can be eliminated.

  When this video / audio signal processing apparatus further includes a high image quality signal processing circuit for improving the video quality by digital signal processing, the storage means includes a scaler and a high image quality signal processing circuit. It is preferable to memorize the time required for processing in the above.

  As a result, in video display / audio output devices such as television receivers having a fixed pixel display device, the phenomenon that video is delayed not only by the scaler but also by the presence of a high image quality signal processing circuit is eliminated. Will be able to.

  Further, whether the video / audio signal processing apparatus having such a high image quality signal processing circuit performs processing on the video signal by the high image quality signal processing circuit, and / or processing by the high image quality signal processing circuit. When it is possible to switch between two or more modes depending on the contents, the storage means stores the time required for the processing in the scaler and the image quality enhancement signal processing circuit for each mode, and the audio signal, It is preferable to further comprise control means for controlling the delay means so as to delay the current mode by the time stored in the storage means.

  As a result, in video display / audio output devices such as television receivers having a fixed pixel display device, even if the image quality of the video to be displayed is switched, the video is not affected by the presence of the scaler and the high image quality signal processing circuit. The phenomenon can be solved.

  Next, the present applicant applies a display device having a fixed pixel and a pixel number conversion circuit (scaler) that matches the pixel arrangement of the video signal of the input video signal and audio signal to the pixel arrangement of the display device by digital signal processing. A video display / audio output device having a storage means for storing the time required for processing by the scaler, and a delay means for delaying the audio signal by the time stored in the storage means. A display / audio output device is proposed.

  In this video display / audio output device, the time required for the digital signal processing by the scaler for the video signal of the input video signal and audio signal is stored in advance in the storage means. Then, the audio signal is delayed by the delay means by the time stored in the storage means, so that the output timing of the video signal and the output timing of the audio signal are matched.

  This eliminates the phenomenon that the video displayed on the fixed pixel display device is delayed with respect to the sound due to the presence of the scaler.

  When the video display / audio output device further includes a high image quality signal processing circuit for improving the video quality by digital signal processing, the storage means includes a scaler and a high image quality signal processing circuit. It is preferable to memorize the time required for processing in the above.

  As a result, it is possible to eliminate the phenomenon that the video displayed on the fixed pixel display device is delayed not only by the scaler but also by the presence of the high image quality signal processing circuit.

  Further, whether or not the video display / audio output device having such a high image quality signal processing circuit performs processing on the video signal by the high image quality signal processing circuit and / or processing by the high image quality signal processing circuit. When it is possible to switch between two or more modes depending on the contents, the storage means stores the time required for the processing in the scaler and the image quality enhancement signal processing circuit for each mode, and the audio signal, It is preferable to further comprise control means for controlling the delay means so as to delay the current mode by the time stored in the storage means.

  As a result, even if the image quality of the video to be displayed is switched, the phenomenon of the video displayed on the fixed pixel display device can be eliminated due to the presence of the scaler and the image quality enhancement signal processing circuit.

  According to the present invention, in a video display / audio output device such as a television receiver having a fixed pixel display device, a video image to be displayed is converted into a pixel array of the display device by digital signal processing. The effect that the phenomenon of delaying with respect to sound due to the presence of the pixel number conversion circuit (scaler) to be combined can be solved.

  In addition, in such a video display / audio output device, the phenomenon that the displayed video is delayed with respect to the sound due to the existence of a high image quality signal processing circuit that improves the image quality by digital signal processing as well as the scaler is also eliminated. The effect that it can be obtained.

  Further, in such a video display / audio output device, even if the image quality of the displayed video is switched, the phenomenon that the displayed video is delayed with respect to the sound due to the presence of the scaler and the image quality enhancement signal processing circuit can be solved. An effect is obtained.

  Hereinafter, an example in which the present invention is applied to a television receiver having a fixed pixel display device such as a plasma television or a liquid crystal television will be specifically described with reference to the drawings.

  FIG. 2 shows a configuration example of a video / audio signal processing system of a television receiver to which the present invention is applied, and the same reference numerals are given to portions common to FIG. A television signal is sent from an antenna 1 that receives radio waves of an analog television broadcast to a tuner 2 of the television receiver. The television signal of the channel selected by the tuner 2 is sent to the demodulation circuit 3, and the demodulation circuit 3 demodulates the television signal to generate an analog video signal (NTSC signal with 483 effective scanning lines) and an analog audio signal. obtain.

  The demodulated analog video signal is sent to the image quality enhancement signal processing circuit 4. Although not shown, the high image quality signal processing circuit 4 digitally converts the analog video signal by the ITU 4: 2: 2 method (the number of effective pixels per scanning line of the luminance signal is set to 720 pixels). A / D converter is included, and a circuit for improving the image quality by digital signal processing (for example, a circuit that performs progressive conversion of an interlace signal) is included in the subsequent stage.

  In this television receiver, a high image quality mode for displaying a high image quality image by processing the digital image signal output from the A / D converter in a subsequent circuit in the image quality enhancement signal processing circuit 4. Then, the normal image quality video is displayed by outputting the digital video signal output from the A / D converter in the high image quality signal processing circuit 4 as it is (without being processed in the subsequent circuit). The mode can be switched by operating a remote controller (not shown).

  The digital video signal output from the image quality enhancement signal processing circuit 4 is sent to a scaler (pixel number conversion circuit) 5. In the scaler 5, digital signal processing is performed to match the pixel arrangement of the input digital video signal with the pixel arrangement of a fixed pixel panel (plasma display panel or liquid crystal display panel) 7 included in the television receiver.

  Specifically, for example, if the pixel arrangement of the fixed pixel panel 7 is 1024 pixels in the horizontal direction × 768 pixels in the vertical direction, the scaler 5 has the number of effective pixels 720 pixels / number of effective scanning lines 483 per scanning line of the luminance signal. One input digital video signal is converted into a digital video signal of 1024 effective pixels per scanning line and 768 effective scanning lines per luminance line.

  The digital video signal whose number of pixels has been converted by the scaler 5 is sent to a display driver 6 that drives the fixed pixel panel 7. The display driver 6 applies a voltage corresponding to the input digital video signal to the fixed pixel panel 7.

  On the other hand, the analog audio signal demodulated by the demodulation circuit 3 is sent to the audio delay circuit 10. The audio delay circuit 10 temporarily converts an input analog audio signal into an A / D converter 11 for digital conversion at a predetermined sampling frequency (for example, 44.1 kHz or 48 kHz) and a digital audio signal output from the A / D converter 11. It comprises a RAM 12 for storing, a D / A converter 13 for converting a digital audio signal read from the RAM 12 into an analog signal, and a timing circuit 14.

  The timing circuit 14 supplies an operation clock to the A / D converter 11 and the D / A converter 13, and supplies a write / read clock for digital audio signals to the RAM 12. The timing circuit 14 sets the digital audio signal read timing from the RAM 12 (sets the read clock output timing) under the control of the microprocessor 15.

  The analog audio signal output from the D / A converter 13 is sent from the audio delay circuit 10 to the audio amplifier circuit 8 and amplified, and then output from the speaker 9.

  When designing this television receiver, the time required for the processing in the scaler 5 and the time required for the processing in the image quality enhancement signal processing circuit 4 are summed up (referred to as “processing time during high image quality display”). And the time required for processing in the scaler 5 (referred to as “processing time during normal display”) is determined as processing time specific to the model.

  The ROM in the microprocessor 15 stores in advance processing time data during high-quality display and processing time data during normal display. The microprocessor 15 is also supplied with display mode information that informs the current display mode (whether it is the high image quality mode or the normal mode) based on the operation of the remote controller.

  FIG. 3 is a flowchart showing a process executed by the microprocessor 15 each time the display mode information is supplied. In this process, first, it is determined whether or not the current display mode is the high image quality mode (step S1).

  If yes, the processing time data during high-quality display is read from the ROM in the microprocessor 15. Then, the timing circuit 14 is set as a timing for reading the digital audio signal from the RAM 12 in the audio delay circuit 10 with a timing delayed by the processing time at the time of high image quality display from the timing of writing the digital audio signal to the RAM 12 ( Step S2). Then, the process ends.

  On the other hand, if the answer is no (if the current display mode is the normal mode), the processing time data during normal display is read from the ROM in the microprocessor 15. Then, as a timing for reading the digital audio signal from the RAM 12 in the audio delay circuit 10, a timing delayed by the processing time at the time of normal display is set in the timing circuit 14 from the timing of writing the digital audio signal to the RAM 12 (step S14). S3). Then, the process ends.

  In this television receiver, when switched to the high image quality mode by the remote controller, the digital video signal written in the RAM 12 in the audio delay circuit 10 is processed by the microprocessor 15 in steps S1 and S2 in FIG. Since it is read from the RAM 12 at a timing delayed by the processing time at the time of display (the time required for the processing in the scaler 5 and the time required for the processing in the image quality enhancement signal processing circuit 4), the audio delay circuit 10 In FIG. 5, the analog audio signal is delayed by the processing time during the high image quality display, whereby the output timing of the digital video signal from the scaler 5 and the output timing of the analog audio signal from the audio delay circuit 10 are matched.

  Even when the remote controller is switched to the normal mode, the digital video signal written in the RAM 12 in the audio delay circuit 10 is processed in the normal display by the processing of the microprocessor 15 in steps S1 and S3 in FIG. Since the data is read from the RAM 12 at a timing delayed by the time (the time required for processing by the scaler 5), the audio delay circuit 10 delays the analog audio signal by the processing time at the time of normal display. And the output timing of the analog audio signal from the audio delay circuit 10 are matched.

  As described above, the output timing of the digital video signal from the scaler 5 and the output timing of the analog audio signal from the audio delay circuit 10 can be matched in both the high image quality mode and the normal mode. The phenomenon that the displayed video is delayed with respect to the sound due to the presence of the high image quality signal processing circuit 4 and the scaler 5 can be solved.

  In the above example, the analog video signal and the analog audio signal selected by the tuner 2 and demodulated by the demodulation circuit 3 are sent to the image quality enhancement signal processing circuit 4 and the audio delay circuit 10, respectively. However, the present invention is not limited to this, for example, when an analog video signal and an analog audio signal input from the VTR or DVD player to the television receiver are sent to the image quality enhancement signal processing circuit 4 and the audio delay circuit 10, respectively. In exactly the same manner, the phenomenon that the image displayed on the fixed pixel panel 7 is delayed with respect to the sound due to the presence of the image quality enhancement signal processing circuit 4 and the scaler 5 can be eliminated.

  In the above example, in the normal mode, the digital video signal output from the A / D converter in the high image quality signal processing circuit 4 is output as it is (without being processed in the subsequent circuit). The present invention is applied to a television receiver. However, as another example, a television that performs digital video signal processing on the video signal in the high image quality signal processing circuit even in the normal mode, but the processing contents differ between the high image quality mode and the normal mode. The present invention may also be applied to a receiver.

  In that case, as the “processing time at the time of high image quality display”, the time required for processing in the scaler 5 and the time required for processing in the high image quality signal processing circuit in the high image quality mode are obtained, As the “processing time for normal display”, the total time of the processing time in the scaler 5 and the processing time in the high image quality signal processing circuit in the normal mode is obtained. What is necessary is just to make it memorize | store in the ROM in the processor 15 previously.

  In the above example, the present invention is applied to a television receiver capable of switching between a high image quality mode and a normal mode. However, as another example, the present invention may be applied to a television receiver in which only the high image quality mode exists.

  In that case, only the “processing time at the time of high-quality display” is obtained, and the data of that time is stored in advance in the ROM in the microprocessor 15 and is read out as the digital audio signal read timing from the RAM 12 in the audio delay circuit 10. The timing circuit 14 may always be set to a timing delayed from the timing of writing the digital audio signal to the RAM 12 by the processing time at the time of high image quality display.

  In the above example, the present invention is applied to a television receiver provided with the scaler 5 and the high image quality signal processing circuit 4. However, as another example, the present invention may be applied to a television receiver provided with a scaler 5 but not provided with a high image quality signal processing circuit.

  In that case, only the time required for processing in the scaler 5 is obtained, and the data of that time is stored in advance in the ROM in the microprocessor 15, and the reading timing of the digital audio signal from the RAM 12 in the audio delay circuit 10 is as follows. The timing circuit 14 may always be set to a timing delayed by this time from the timing of writing the digital audio signal to the RAM 12.

  In the above example, the present invention is applied to a television receiver. However, the present invention is also applied to a video display / audio output device other than the television receiver, which has a fixed pixel display device. The present invention may be applied.

It is a block diagram which shows the structural example of the video / audio signal processing system of the conventional television receiver which has a display device of a fixed pixel. It is a block diagram which shows the structural example of the video / audio signal processing system of the television receiver to which this invention is applied. It is a flowchart which shows the process which the microprocessor of FIG. 2 performs.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Antenna 2 Tuner 3 Demodulation circuit 4 Image quality improvement signal processing circuit 5 Scaler (pixel number conversion circuit)
6 Display driver 7 Fixed pixel panel 8 Audio amplifier circuit 9 Speaker 10 Audio delay circuit 11 A / D converter 12 RAM
13 D / A converter 14 Timing circuit 15 Microprocessor

Claims (6)

In a video / audio signal processing apparatus having a pixel number conversion circuit for matching a pixel arrangement of a video signal of input video signals and audio signals with a pixel arrangement of a display device of fixed pixels by digital signal processing,
Storage means for storing time required for processing in the pixel number conversion circuit;
A video / audio signal processing apparatus comprising delay means for delaying the audio signal by a time stored in the storage means. The video / audio signal processing device according to claim 1,
It further has a high image quality signal processing circuit that improves the image quality by digital signal processing.
The video / audio signal processing apparatus, wherein the storage means stores time required for processing in the pixel number conversion circuit and the image quality enhancement signal processing circuit. The video / audio signal processing device according to claim 2,
Two or more modes can be switched depending on whether or not the video signal processing is performed by the image quality improving signal processing circuit and / or processing contents in the image quality improving signal processing circuit,
The storage means stores time required for processing in the pixel number conversion circuit and the image quality enhancement signal processing circuit for each of the modes,
A video / audio signal processing apparatus, further comprising a control means for controlling the delay means so as to delay the audio signal by a time stored in the storage means for the current mode. A fixed pixel display device;
In a video display / audio output device having a pixel number conversion circuit for adjusting a pixel arrangement of a video signal of an input video signal and an audio signal to a pixel arrangement of the display device by digital signal processing,
Storage means for storing time required for processing in the pixel number conversion circuit;
A video display / audio output device comprising delay means for delaying the audio signal by a time stored in the storage means. The video display / audio output device according to claim 4,
It further has a high image quality signal processing circuit that improves the image quality by digital signal processing.
The video display / audio output device, wherein the storage means stores time required for processing in the pixel number conversion circuit and the image quality enhancement signal processing circuit. The video display / audio output device according to claim 5,
Two or more modes can be switched depending on whether or not the video signal processing is performed by the image quality improving signal processing circuit and / or processing contents in the image quality improving signal processing circuit,
The storage means stores time required for processing in the pixel number conversion circuit and the image quality enhancement signal processing circuit for each of the modes,
A video display / audio output device further comprising control means for controlling the delay means so as to delay the audio signal by a time stored in the storage means for the current mode.

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