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JP2005072349A - Method of manufacturing semiconductor element - Google Patents

Method of manufacturing semiconductor element Download PDF

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JP2005072349A
JP2005072349A JP2003301445A JP2003301445A JP2005072349A JP 2005072349 A JP2005072349 A JP 2005072349A JP 2003301445 A JP2003301445 A JP 2003301445A JP 2003301445 A JP2003301445 A JP 2003301445A JP 2005072349 A JP2005072349 A JP 2005072349A
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semiconductor wafer
auxiliary substrate
adhesive
adhesive material
semiconductor
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Takashi Arita
隆史 有田
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Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
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Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem in the conventional semiconductor element manufacturing method that the treating liquid such as acids or organic solvents, etc. used for processing the backside penetrates through through-holes 4 to dissolve a resist layer 3, this lowering the adhesive strength of a semiconductor wafer 2 to a subsidiary substrate 1 to result in the peel off and damage of the wafer 2. <P>SOLUTION: The semiconductor element manufacturing method comprises a step of adhering a subsidiary substrate 1 having many through-holes 4 to a semiconductor wafer surface 2a through two adhesive layers, i.e., a resist layer 3 and a fluoric resin layer 101, a step of processing the semiconductor wafer backside 2b, a step of drilling holes 102 in the fluoric resin layer 101 by plasma etching, and a step of penetrating an organic solvent 5 through the holes 102 to peel off the wafer 2 from the subsidiary substrate 1. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、裏面研磨で半導体ウェーハが薄くなっても割れないように、半導体ウェーハを補助基板に貼付けて補強して裏面加工する半導体素子の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, in which a semiconductor wafer is attached to an auxiliary substrate and reinforced so that the semiconductor wafer does not break even when the semiconductor wafer is thinned by backside polishing.

例えば、GaAsなどの化合物で成る半導体ウェーハの場合、半導体ウェーハ表面に素子を形成した後、熱抵抗を低減するために半導体ウェーハの裏面側から、その厚さを極めて薄く研磨するが、これによって機械的強度が低下し、半導体ウェーハが工程中のストレスで割れるのを防止するため、予め、剛性を有する石英やガラスなどで成る補助基板に貼付材で貼付けて加工する。   For example, in the case of a semiconductor wafer made of a compound such as GaAs, after forming elements on the surface of the semiconductor wafer, the thickness is polished very thinly from the back side of the semiconductor wafer in order to reduce the thermal resistance. In order to prevent the mechanical strength from being reduced and the semiconductor wafer from cracking due to stress during the process, it is previously processed by being attached to an auxiliary substrate made of quartz or glass having rigidity with an adhesive.

従来の半導体素子の製造方法の一例を図3に示す。図3は、工程順を示す要部断面図である。   An example of a conventional method for manufacturing a semiconductor device is shown in FIG. FIG. 3 is a cross-sectional view of the main part showing the order of steps.

従来の半導体素子の製造方法は、先ず、図3(a)に示すように、ガラスで成る補助基板1と半導体ウェーハ2とを貼付ける。貼付手順は、半導体ウェーハ2の表面2aに貼付材として、例えば、レジスト層3を形成し、加熱しながらその形成面を補助基板1に押付けて貼付ける。   In the conventional method of manufacturing a semiconductor device, first, as shown in FIG. 3A, an auxiliary substrate 1 made of glass and a semiconductor wafer 2 are attached. In the sticking procedure, for example, a resist layer 3 is formed on the surface 2a of the semiconductor wafer 2 as a sticking material, and the formed surface is pressed against the auxiliary substrate 1 while being heated.

ここで、半導体ウェーハ2に形成する貼付材としては、レジスト以外にも、例えば、アクリル系樹脂や専用ワックスなどでもよく、通常、剥離の際にメチルエチルケトンやアセトンやイソプロピルアルコールなどの有機溶剤で溶解させるため、これらの有機溶剤に対して可溶性に優れた貼付材とする。尚、上記では、貼付材を半導体ウェーハ2側に形成することで説明したが、補助基板1側に形成してもよい。   Here, the adhesive material formed on the semiconductor wafer 2 may be, for example, an acrylic resin or a special wax other than the resist, and is usually dissolved with an organic solvent such as methyl ethyl ketone, acetone, or isopropyl alcohol at the time of peeling. For this reason, the patch is excellent in solubility in these organic solvents. In the above description, the adhesive material is formed on the semiconductor wafer 2 side. However, the adhesive material may be formed on the auxiliary substrate 1 side.

また、図4に示すように、補助基板1には多数の貫通穴4(直径;数百μm程度)が設けられている。この貫通穴4を設ける目的は、半導体ウェーハ2と補助基板1とを貼付ける際に生じる気泡を逃がすためと、剥離の際に有機溶剤が、この貫通穴4を通して浸入し貼付材を溶解しやすくするためである。   As shown in FIG. 4, the auxiliary substrate 1 is provided with a large number of through holes 4 (diameter: about several hundred μm). The purpose of providing the through-hole 4 is to escape bubbles generated when the semiconductor wafer 2 and the auxiliary substrate 1 are pasted, and an organic solvent can easily enter through the through-hole 4 and dissolve the pasting material at the time of peeling. It is to do.

次に、図3(b)に示すように、半導体ウェーハ2の裏面2bを裏面研磨装置(図示せず)で所望の厚さになるように薄く研磨(図中、研磨部分を一点鎖線で示す)した後、例えば、フォトリソグラフィ法を用いて半導体ウェーハ2の裏面2b側から表面2a側に貫通するビアホール(図示せず)を形成したり、前処理としての酸処理後、真空蒸着法などで所定の金属膜形成をしたり、各処理毎に洗浄や乾燥作業をするなどの裏面加工を施す。このとき、これらの処理に使用される酸や有機溶剤は、補助基板1の貫通穴4に浸入するため、レジスト層3は酸や有機溶剤に晒されることになる。   Next, as shown in FIG. 3B, the back surface 2b of the semiconductor wafer 2 is thinly polished with a back surface polishing apparatus (not shown) so as to have a desired thickness (the polishing portion is indicated by a one-dot chain line in the drawing). After that, for example, a via hole (not shown) penetrating from the back surface 2b side to the front surface 2a side of the semiconductor wafer 2 is formed using a photolithography method, or after an acid treatment as a pretreatment, a vacuum deposition method or the like. A predetermined metal film is formed, and backside processing such as washing and drying is performed for each treatment. At this time, since the acid and organic solvent used in these treatments enter the through holes 4 of the auxiliary substrate 1, the resist layer 3 is exposed to the acid and organic solvent.

次に、裏面加工が完了したら、図3(c)に示すように、補助基板1と半導体ウェーハ2との接合体を剥離用の有機溶剤5(例えば、メチルエチルケトンやアセトンやイソプロピルアルコールなど)に浸漬しレジスト層を溶解させ、補助基板1と半導体ウェーハ2とを剥離させる。   Next, when the back surface processing is completed, as shown in FIG. 3C, the joined body of the auxiliary substrate 1 and the semiconductor wafer 2 is immersed in an organic solvent 5 for peeling (for example, methyl ethyl ketone, acetone, isopropyl alcohol, etc.). Then, the resist layer is dissolved, and the auxiliary substrate 1 and the semiconductor wafer 2 are peeled off.

このとき、有機溶剤5は半導体ウェーハ2の外周部から内部に浸入することに加えて、補助基板1に設けられた多数の貫通穴4を通して浸入するためレジスト層の溶解速度をより速めることができる。   At this time, the organic solvent 5 penetrates through the numerous through holes 4 provided in the auxiliary substrate 1 in addition to entering the inside from the outer peripheral portion of the semiconductor wafer 2, so that the dissolution rate of the resist layer can be further increased. .

このように、予め、半導体ウェーハ2を補助基板1に貼付けて裏面加工すると、半導体ウェーハ2の厚みが薄くなって機械的強度が低下しても、工程中のストレスで割れることを防止できる。また、補助基板1に多数の貫通穴4を設けておくと剥離スピードの向上が図れる。   As described above, when the semiconductor wafer 2 is attached to the auxiliary substrate 1 in advance and processed on the back surface, even if the thickness of the semiconductor wafer 2 is reduced and the mechanical strength is reduced, it is possible to prevent cracking due to stress during the process. Further, if a large number of through holes 4 are provided in the auxiliary substrate 1, the peeling speed can be improved.

そして、その後、ダイシング(図示せず)などで半導体ウェーハ2を個別のペレット(図示せず)に分割する(例えば、特許文献1参照。)。
特開2002−184845号公報 (第2頁、0003〜0005段落,図5)
Thereafter, the semiconductor wafer 2 is divided into individual pellets (not shown) by dicing (not shown) or the like (see, for example, Patent Document 1).
JP 2002-184845 A (2nd page, paragraphs 0003 to 0005, FIG. 5)

しかしながら、上述の半導体素子の製造方法では、補助基板1に多数の貫通穴4が設けられているため、裏面加工の各処理において使用される酸や有機溶剤などの処理液が補助基板1の貫通穴4を通して浸入し、レジスト層3を不所望にも溶解して補助基板1と半導体ウェーハ2との貼付強度を低下させ、その結果、工程途中で半導体ウェーハ2が剥離して破損するという問題があった。   However, in the above-described semiconductor element manufacturing method, since the auxiliary substrate 1 is provided with a large number of through holes 4, a treatment liquid such as an acid or an organic solvent used in each processing of the back surface penetrates the auxiliary substrate 1. It penetrates through the holes 4 and undesirably dissolves the resist layer 3 to reduce the bonding strength between the auxiliary substrate 1 and the semiconductor wafer 2, resulting in a problem that the semiconductor wafer 2 is peeled off and damaged during the process. there were.

本発明の目的は、裏面加工の各処理で使用される酸や有機溶剤などの処理液が、補助基板の貫通穴を通して浸入し、補助基板と半導体ウェーハとの貼付強度を低下させることのない半導体素子の製造方法を提供することである。   An object of the present invention is a semiconductor in which a treatment liquid such as an acid or an organic solvent used in each processing of backside processing enters through a through hole of the auxiliary substrate and does not reduce the bonding strength between the auxiliary substrate and the semiconductor wafer. It is providing the manufacturing method of an element.

本発明の半導体素子の製造方法は、
少なくとも、
半導体ウェーハ表面と、多数の貫通穴を設けた補助基板とを異なる貼付材から成る2層の貼付材層を介して貼付ける貼付工程と、
露呈した半導体ウェーハ裏面に所定の加工を施す裏面加工工程と、
貫通穴を通して2層の貼付材層の内、補助基板側の貼付材層に穴を開ける穿孔工程と、
補助基板側の貼付材層に開けた穴を通して、半導体ウェーハ側の貼付材層を除去して、補助基板と半導体ウェーハとを剥離する剥離工程とを含むことを特徴とする半導体素子の製造方法である。
The method for manufacturing a semiconductor device of the present invention includes:
at least,
A pasting step of pasting a semiconductor wafer surface and an auxiliary substrate provided with a large number of through-holes through two layers of adhesive layers made of different adhesive materials;
A back surface processing step of performing predetermined processing on the exposed semiconductor wafer back surface;
A perforating step of making a hole in the adhesive layer on the auxiliary substrate side of the two adhesive layers through the through hole;
A method for manufacturing a semiconductor element, comprising: a peeling step of removing the adhesive material layer on the semiconductor wafer side through a hole opened in the adhesive material layer on the auxiliary substrate side and separating the auxiliary substrate and the semiconductor wafer. is there.

本発明の半導体素子の製造方法によると、補助基板と半導体ウェーハとを貼付ける貼付材を異なる貼付材から成る2層とし、半導体ウェーハ側の貼付材を剥離用の有機溶剤に対して可溶性に優れた貼付材とするため剥離スピードの向上が図れる。また一方、補助基板側の貼付材を裏面加工で使用される処理液に対して可溶性の低い貼付材とするため補助基板に設けられた貫通穴から処理液が浸入しても貼付強度を低下させる心配がない。   According to the method for manufacturing a semiconductor element of the present invention, the adhesive material for adhering the auxiliary substrate and the semiconductor wafer is made of two layers made of different adhesive materials, and the adhesive material on the semiconductor wafer side is excellent in solubility in an organic solvent for peeling. Since it is a sticking material, the peeling speed can be improved. On the other hand, the adhesive strength on the auxiliary substrate side is reduced even if the processing liquid enters from the through hole provided in the auxiliary substrate in order to make the adhesive material on the side of the auxiliary substrate less soluble in the processing liquid used in the back surface processing. There is no worry.

本発明の半導体素子の製造方法の一例を図1,図2に示す。図1,図2は、工程順を示す要部断面図である。尚、図3と同一部分には同一符号を付す。   An example of a method for manufacturing a semiconductor device of the present invention is shown in FIGS. 1 and 2 are cross-sectional views of the main part showing the order of steps. The same parts as those in FIG. 3 are denoted by the same reference numerals.

本発明の半導体素子の製造方法は、先ず、図1(a)に示すように、ガラスで成る補助基板1と半導体ウェーハ2とを貼付ける。貼付手順は、半導体ウェーハ2の表面2aに貼付材として、例えば、レジスト層3を形成する。また一方、補助基板1に貼付材として、例えば、フッ素系樹脂層101を形成する。そして、加熱しながら、その形成面同士を押付けて両者を貼付ける。   In the method of manufacturing a semiconductor element of the present invention, first, as shown in FIG. 1A, an auxiliary substrate 1 made of glass and a semiconductor wafer 2 are attached. In the sticking procedure, for example, a resist layer 3 is formed on the surface 2a of the semiconductor wafer 2 as a sticking material. On the other hand, for example, a fluorine resin layer 101 is formed on the auxiliary substrate 1 as a sticking material. And while heating, the formation surfaces are pressed against each other and pasted together.

ここで、半導体ウェーハ2に形成する貼付材としては、レジスト以外にも、例えば、アクリル系樹脂や専用ワックスなどでもよく、通常、剥離の際にメチルエチルケトンやアセトンやイソプロピルアルコールなどの有機溶剤で溶解させるため、これらの有機溶剤に対して可溶性に優れた貼付材がよい。   Here, the adhesive material formed on the semiconductor wafer 2 may be, for example, an acrylic resin or a special wax other than the resist, and is usually dissolved with an organic solvent such as methyl ethyl ketone, acetone, or isopropyl alcohol at the time of peeling. Therefore, a patch having excellent solubility in these organic solvents is preferable.

また一方、補助基板1に形成する貼付材としては、後の裏面加工工程で使用される酸や有機溶剤などの処理液に対する保護層とするため、耐有機溶剤性、耐酸性に優れた貼付材とする。例えば、フッ素系樹脂は機械的強度や耐熱性にも優れており好適である。また、形成層の厚さは、保護膜としての強度と後工程での除去のしやすさの両者を考慮して決定する。   On the other hand, as the adhesive material to be formed on the auxiliary substrate 1, an adhesive material excellent in organic solvent resistance and acid resistance is used as a protective layer against a treatment liquid such as acid and organic solvent used in the subsequent back surface processing step. And For example, a fluororesin is suitable because it is excellent in mechanical strength and heat resistance. The thickness of the formation layer is determined in consideration of both the strength as a protective film and the ease of removal in a subsequent process.

尚、上記では、貼付材をそれぞれ半導体ウェーハ2,補助基板1に各1層ずつ形成することで説明したが、一方側に2層を積層形成してもよい。   In the above description, the adhesive material is described as being formed on the semiconductor wafer 2 and the auxiliary substrate 1 by one layer each. However, two layers may be laminated on one side.

また、図4に示すように、補助基板1には、多数の貫通穴4(直径;数百μm程度)が設けられている。この貫通穴4を設ける目的は、半導体ウェーハ2と補助基板1とを貼付ける際に生じる気泡を逃がすためと、剥離の際に有機溶剤が、この貫通穴4を通して浸入し貼付材を溶解しやすくするためである。   As shown in FIG. 4, the auxiliary substrate 1 is provided with a large number of through holes 4 (diameter: about several hundred μm). The purpose of providing the through-hole 4 is to escape bubbles generated when the semiconductor wafer 2 and the auxiliary substrate 1 are pasted, and an organic solvent can easily enter through the through-hole 4 and dissolve the pasting material at the time of peeling. It is to do.

次に、図1(b)に示すように、半導体ウェーハ2の裏面2bを裏面研磨装置(図示せず)で所望の厚さになるように薄く研磨(図中、研磨部分を一点鎖線で示す)した後、例えば、フォトリソグラフィ法を用いて半導体ウェーハ2の裏面2b側から表面2a側に貫通するビアホール(図示せず)を形成したり、前処理としての酸処理後、真空蒸着法などで所定の金属膜形成をしたり、各処理毎に洗浄や乾燥作業をするなどの裏面加工を施す。   Next, as shown in FIG. 1B, the back surface 2b of the semiconductor wafer 2 is thinly polished with a back surface polishing apparatus (not shown) so as to have a desired thickness (in the figure, the polishing portion is indicated by a one-dot chain line). ), For example, a via hole (not shown) penetrating from the back surface 2b side of the semiconductor wafer 2 to the front surface 2a side is formed using a photolithography method, or after an acid treatment as a pretreatment, a vacuum deposition method or the like. A predetermined metal film is formed, and backside processing such as washing and drying is performed for each treatment.

このとき、裏面加工に使用される酸や有機溶剤が補助基板1の貫通穴4に浸入するが、レジスト層3はフッ素系樹脂層101によって保護されているため溶解して貼付強度を低下させることがない。   At this time, an acid or an organic solvent used for the back surface processing enters the through hole 4 of the auxiliary substrate 1, but the resist layer 3 is protected by the fluororesin layer 101, so that it melts to lower the adhesive strength. There is no.

次に、裏面加工が完了したら、図2(c)に示すように、補助基板1の裏面側から貫通穴4を通してフッ素系樹脂層101をプラズマエッチングで除去し、フッ素系樹脂層101に穴102を開けレジスト層3を露出させる。   Next, when the back surface processing is completed, as shown in FIG. 2C, the fluorine-based resin layer 101 is removed by plasma etching from the back surface side of the auxiliary substrate 1 through the through holes 4, and the holes 102 are formed in the fluorine-based resin layer 101. To open the resist layer 3.

次に、図2(d)に示すように、補助基板1と半導体ウェーハ2との接合体を、剥離用の有機溶剤5(例えば、メチルエチルケトンやアセトンやイソプロピルアルコールなど)に浸漬し、有機溶剤5を半導体ウェーハ2外周部およびフッ素系樹脂層101に開けた穴102を通して浸入させて、レジスト層3を溶解させ補助基板1と半導体ウェーハ2とを剥離させる。   Next, as shown in FIG. 2D, the joined body of the auxiliary substrate 1 and the semiconductor wafer 2 is immersed in a peeling organic solvent 5 (for example, methyl ethyl ketone, acetone, isopropyl alcohol, etc.), and the organic solvent 5 Is introduced through the hole 102 formed in the outer peripheral portion of the semiconductor wafer 2 and the fluorine-based resin layer 101 to dissolve the resist layer 3 and peel off the auxiliary substrate 1 and the semiconductor wafer 2.

このとき、有機溶剤5は、半導体ウェーハ2外周部から内部に浸入することに加えて、補助基板1に設けられた多数の貫通穴4を通して浸入するため、レジスト層3の溶解速度をより速めることができる。   At this time, since the organic solvent 5 permeates through the numerous through holes 4 provided in the auxiliary substrate 1 in addition to intrusion from the outer periphery of the semiconductor wafer 2, the dissolution rate of the resist layer 3 can be further increased. Can do.

このように、予め、半導体ウェーハ2を補助基板1に貼付けて裏面加工すると、半導体ウェーハ2の厚みが薄くなって機械的強度が低下しても、工程中のストレスで割れることを防止できる。また、補助基板1に多数の貫通穴4を設けて、裏面加工中は耐処理液性に優れたフッ素系樹脂層101で保護するため、貫通穴4から処理液が浸入して貼付強度を低下させる心配がない。また、剥離の際には、予め、フッ素系樹脂層101をプラズマエッチングで除去し、貫通穴4を通して有機溶剤5を浸入させるので剥離スピードの向上が図れる。   As described above, when the semiconductor wafer 2 is attached to the auxiliary substrate 1 in advance and processed on the back surface, even if the thickness of the semiconductor wafer 2 is reduced and the mechanical strength is reduced, it is possible to prevent cracking due to stress during the process. In addition, since a large number of through holes 4 are provided in the auxiliary substrate 1 and the back surface processing is protected by the fluorine-based resin layer 101 having excellent treatment liquid resistance, the treatment liquid intrudes from the through holes 4 to reduce the adhesive strength. There is no worry to let you. Further, at the time of peeling, the fluorine-based resin layer 101 is previously removed by plasma etching, and the organic solvent 5 is infiltrated through the through holes 4, so that the peeling speed can be improved.

そして、その後、ダイシング(図示せず)などで半導体ウェーハ2を個別のペレット(図示せず)に分割する。   Thereafter, the semiconductor wafer 2 is divided into individual pellets (not shown) by dicing (not shown) or the like.

裏面加工の各処理に使用される酸や有機溶剤などが補助基板の貫通穴から浸入し貼付材の貼付強度を低下させる心配がない半導体ウェーハの裏面加工プロセスに適用できる。   The present invention can be applied to a backside processing process of a semiconductor wafer where there is no fear that the acid or organic solvent used for each processing of the backside permeates through the through hole of the auxiliary substrate and lowers the pasting strength of the pasting material.

本発明の半導体素子の製造方法の一例の工程順の要部断面図Sectional drawing of the principal part of process order of an example of the manufacturing method of the semiconductor element of this invention 本発明の半導体素子の製造方法の一例の工程順の要部断面図Sectional drawing of the principal part of process order of an example of the manufacturing method of the semiconductor element of this invention 従来の半導体素子の製造方法の工程順の要部断面図Cross-sectional view of relevant parts in the order of steps in a conventional method for manufacturing a semiconductor device 補助基板の平面図および断面図Plan view and sectional view of auxiliary board

符号の説明Explanation of symbols

1 補助基板
2 半導体ウェーハ
2a 半導体ウェーハの表面
2b 半導体ウェーハの裏面
3 レジスト層
4 貫通穴
5 剥離用の有機溶剤
101 フッ素系樹脂層
102 フッ素系樹脂層に開けた穴
DESCRIPTION OF SYMBOLS 1 Auxiliary substrate 2 Semiconductor wafer 2a The surface of a semiconductor wafer 2b The back surface of a semiconductor wafer 3 Resist layer 4 Through-hole 5 The organic solvent for peeling 101 Fluorine-based resin layer 102 The hole opened in the fluorine-based resin layer

Claims (5)

少なくとも、
半導体ウェーハ表面と、多数の貫通穴を設けた補助基板とを異なる貼付材から成る2層の貼付材層を介して貼付ける貼付工程と、
露呈した前記半導体ウェーハ裏面に所定の加工を施す裏面加工工程と、
前記貫通穴を通して前記2層の貼付材層の内、前記補助基板側の貼付材層に穴を開ける穿孔工程と、
前記補助基板側の貼付材層に開けた前記穴を通して、前記半導体ウェーハ側の貼付材層を除去して、前記補助基板と前記半導体ウェーハとを剥離する剥離工程とを含むことを特徴とする半導体素子の製造方法。
at least,
A pasting step of pasting a semiconductor wafer surface and an auxiliary substrate provided with a large number of through-holes through two layers of adhesive layers made of different adhesive materials;
A back surface processing step of performing predetermined processing on the exposed semiconductor wafer back surface;
A punching step of making a hole in the adhesive layer on the auxiliary substrate side of the two adhesive layers through the through hole;
A semiconductor device comprising: a peeling step for removing the adhesive material layer on the semiconductor wafer side through the holes formed in the adhesive material layer on the auxiliary substrate side and separating the auxiliary substrate and the semiconductor wafer. Device manufacturing method.
前記2層の貼付材層の内、前記補助基板側の貼付材層は、前記裏面加工工程で使用される処理液に対して可溶性が低い貼付材で成り、前記半導体ウェーハ側の貼付材層は、有機溶剤可溶性に優れた貼付材で成ることを特徴とする請求項1に記載の半導体素子の製造方法。   Of the two adhesive layers, the auxiliary substrate side adhesive layer is made of an adhesive material that is less soluble in the processing liquid used in the back surface processing step, and the semiconductor wafer side adhesive material layer is The method for producing a semiconductor element according to claim 1, wherein the semiconductor element is made of an adhesive material excellent in solubility in an organic solvent. 前記補助基板側の貼付材層は、フッ素系樹脂で成り、前記半導体ウェーハ側の貼付材層は、レジストで成ることを特徴とする請求項2に記載の半導体素子の製造方法。   3. The method of manufacturing a semiconductor element according to claim 2, wherein the adhesive material layer on the auxiliary substrate side is made of a fluorine-based resin, and the adhesive material layer on the semiconductor wafer side is made of a resist. 前記穿孔方法は、ドライエッチングであることを特徴とする請求項1から3のいずれかに記載の半導体素子の製造方法。   4. The method for manufacturing a semiconductor device according to claim 1, wherein the perforating method is dry etching. 前記剥離方法は、前記半導体ウェーハ側の貼付材層に対して可溶性に優れた溶剤を前記半導体ウェーハの外周部および前記補助基板側の貼付材層に開けた前記穴を通して浸入させて、前記半導体ウェーハ側の貼付材層を溶解させる方法であることを特徴とする請求項1から4のいずれかに記載の半導体素子の製造方法。   In the peeling method, a solvent excellent in solubility in the adhesive layer on the semiconductor wafer side is allowed to enter through the hole formed in the outer peripheral portion of the semiconductor wafer and the adhesive layer on the auxiliary substrate side, and the semiconductor wafer The method of manufacturing a semiconductor element according to claim 1, wherein the method is a method of dissolving the side adhesive material layer.
JP2003301445A 2003-08-26 2003-08-26 Method of manufacturing semiconductor element Pending JP2005072349A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010109007A (en) * 2008-10-28 2010-05-13 Fujitsu Ltd Method of manufacturing semiconductor device
CN112289734A (en) * 2020-11-25 2021-01-29 绍兴同芯成集成电路有限公司 A process for organic solvent infiltration and debonding of ultra-thin wafer to dissociate glass carrier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010109007A (en) * 2008-10-28 2010-05-13 Fujitsu Ltd Method of manufacturing semiconductor device
CN112289734A (en) * 2020-11-25 2021-01-29 绍兴同芯成集成电路有限公司 A process for organic solvent infiltration and debonding of ultra-thin wafer to dissociate glass carrier

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