JP2005062440A - Device and method for image display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase a number of gradations that can be expressed with simple constitution by applying a device and a method for image display to, for example, a liquid crystal display device which has a driving circuit formed on an insulating substrate in one body. <P>SOLUTION: With a driving pattern which varies in logical level with the value of image data D5R[2:0] allocated to low-order bits D1R[0] of gradation data D1R, logical values of the low-order bits D1R[0] of the gradation data D1R are set and the number of gradations based upon the low-order bits D1R[0] of the gradation data D1R is increased up to the number of gradations of the image data D5R[2:0] to drive a display part 12. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an image display device and an image display method, and can be applied to, for example, a liquid crystal display device in which a drive circuit is integrally formed on an insulating substrate. The present invention sets the logical value of the lower bits of the gradation data by a drive pattern whose logical level changes according to the value of the image data assigned to the lower bits of the gradation data. By driving the display unit by increasing the number of gradations by the side bits to the number of gradations of the image data, the number of gradations that can be expressed with a simple configuration can be increased.

  In recent years, in liquid crystal display devices, as colorization progresses, size increase and image quality increase, so that high precision is also required in processing in white balance, gamma correction, and the like. In such processing, processing with different characteristics is required depending on the optical characteristics of the backlight, which is the light source, and the target model, but processing with a simple configuration has been required. Conventionally, for example, a table has been used. Such processing is executed by processing image data.

  That is, FIG. 17 is a block diagram showing a liquid crystal display device according to this type of processing. In the liquid crystal display device 1, the display unit 2 includes a liquid crystal display panel in which red, green, and blue pixels are sequentially arranged, and corresponding pixels by gradation data D 1 that sequentially indicates the gradation of each pixel. Thus, for example, an image is displayed by gradation data D1 input in the order of raster scanning. In the figure, D1 [5: 0] indicates the 0th to 5th bits of the corresponding data.

  The display memory 3 is a memory that holds image data for display, and sequentially outputs corresponding image data D2 in an order corresponding to the pixel arrangement of the display unit 2, for example.

  The correction table 4 is constituted by, for example, a random access memory, and outputs correction data D3 for correcting the value of the image data D2 in accordance with the value of the image data D2. The arithmetic circuit 5 uses the correction data D3 to output the image data D2. The gradation data D1 is output after correcting the value.

  As a result, in this type of liquid crystal display device 1, for example, as shown in FIG. 18, correction is performed according to the value of the image data D1 so that the image data D1 is corrected to a characteristic that saturates on the larger value side of the image data D1. Data D3 is generated so that gamma correction can be performed.

  However, in this type of liquid crystal display device 1, as shown in FIG. 19, for example, an image is finally displayed with a gradation with a resolution B that can be expressed by the display unit 2, and thus gamma correction is performed. Even in this case, adjacent gradations in the image data D1 are displayed with the same gradation on the high luminance side, whereas the adjacent gradation differences in the image data D1 are large on the low luminance side. The gradation is emphasized and displayed, so that the gradation is eventually lost in the low luminance part and the high luminance part.

  As a result, this type of image display apparatus is required to express gradation with a higher resolution. Thus, if the gradation can be expressed with such a high resolution, the quality of the display image can be further improved regardless of the processing related to such white balance adjustment and gamma correction.

  However, if the resolution of gradation display is simply increased in the display unit 2, there is a problem that the configuration of the drive circuit in the display unit 2 becomes complicated, and further, the versatility of the display unit 2 is deteriorated.

  On the other hand, for example, Japanese Patent No. 3402602 proposes a method in which a light emitting diode is applied to the backlight and the number of gradations that can be expressed by the display unit 2 is increased by controlling the lighting pattern of the light emitting diode. Has been made. Japanese Patent Laid-Open No. 10-153982 proposes a method of increasing the number of gradations that can be expressed by the display unit 2 by dividing the period of one field into subfields and switching the gradation control in each subfield. It is made to be done. However, these methods also have a problem that the configuration of the display unit 2 is complicated.

Further, for example, a method of increasing the apparent number of gradations by combining with adjacent pixels by applying an error diffusion method or the like is conceivable. However, this method has a drawback that the resolution is deteriorated.
Japanese Patent No. 3402602 Japanese Patent Laid-Open No. 10-153982

  The present invention has been made in consideration of the above points, and intends to propose an image display apparatus and an image display method capable of increasing the number of gradations that can be expressed with a simple configuration.

  In order to solve such a problem, in the invention of claim 1, an image display device for sequentially inputting gradation data indicating the gradation of each pixel to the display unit and displaying an image corresponding to the gradation data on the display unit. To which at least the upper bits excluding the least significant bit of the gradation data are assigned corresponding upper bits of the image data having a larger number of bits than the gradation data, and the image data processing circuit The low-order bits in which the gradation data remains in accordance with the drive pattern that changes in logic level according to the value of the low-order bits in the image data remaining in consecutive frames for one pixel and that differs for adjacent pixels By driving the display unit, the number of gradations in the display unit due to the lower bits in which the gradation data remains is expanded to the number of gradations in the lower bits that remain in the image data. To display an image according to image data to the display unit.

  Further, in the invention of claim 9, the present invention is applied to an image display method in which gradation data instructing the gradation of each pixel is sequentially input to the display unit, and an image corresponding to the gradation data is displayed on the display unit, At least high-order bits excluding the least significant bit of gradation data are assigned corresponding high-order bits of image data having a larger number of bits than gradation data, and image data in consecutive frames for one pixel The logic level changes according to the value of the remaining low-order bits, and the gradation value is set by setting the logical value of the low-order bits of the remaining gradation data with a drive pattern that differs for adjacent pixels. The display unit is driven by expanding the number of gradations of the display unit due to the lower-order bits of the remaining data to the number of gradations of the lower-order bits of the remaining image data, and an image of the image data is displayed on the display unit.

  According to the configuration of claim 1, at least a floor is applied to an image display device that sequentially inputs gradation data indicating the gradation of each pixel to the display unit and displays an image corresponding to the gradation data on the display unit. The higher-order bits excluding the least significant bit of the tone data are assigned the higher-order bits corresponding to the image data having a larger number of bits than the gradation data, and the image data processing circuit continues to one pixel. The logic level changes in accordance with the value of the lower-order bits of the image data remaining in the frame, and the logic value of the lower-order bits of the remaining gradation data is set by a driving pattern that differs for adjacent pixels. Thus, the display unit is driven by expanding the number of gradations of the display unit by the lower-order bits in which the gradation data remains to the number of gradations by the lower-order bits in which the image data remains, and the image by the image data is If displayed on the display section, for example, when displaying a still image, the gradation is increased in any one of the predetermined fields according to this drive pattern, and the number of gradations of each pixel is apparently increased. The image quality can be improved accordingly. Further, the temporary gradation start-up can be made inconspicuous by setting the drive pattern. In this case, the gradation can be increased by simply processing the image data using the drive pattern, thereby increasing the number of gradations that can be expressed with a simple configuration.

  Further, according to the configuration of the ninth aspect, it is possible to provide an image display method capable of increasing the number of gradations that can be expressed with a simple configuration.

  According to the present invention, the number of gradations that can be expressed with a simple configuration can be increased.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.

(1) Configuration of Embodiment FIG. 2 is a block diagram showing a liquid crystal display device which is an image display device applied to an embodiment of the present invention. In the liquid crystal display device 11, the display unit 12 includes a liquid crystal display panel in which pixels made of liquid crystals are arranged in a matrix, a vertical drive circuit that sequentially selects the pixels of the liquid crystal display panel in units of lines, and gradation data D1R [5: 0], D1G [5: 0], and D1B [5: 0] are output to the signal lines of the liquid crystal display panel by outputting drive signals corresponding to the pixels of the line selected by the vertical drive circuit to the gradation data D1R [ 5: 0], D1G [5: 0], D1B [5: 0], a horizontal drive circuit for setting gradations, a vertical generator circuit, a timing generator for generating an operation reference for the horizontal drive circuit, and the like. .

  The display unit 12 includes a horizontal drive circuit corresponding to 6-bit gradation data D1R [5: 0], D1G [5: 0], and D1B [5: 0], whereby each pixel Can be driven with 64 gradations. In the display unit 12, the red, green, and blue digital signal processing circuits 14R, 14G, and 14B, respectively, the red, green, and blue gradation data D1R [5: 0], D1G [5: 0] and D1B [5: 0] are supplied simultaneously in parallel, whereby each gradation data D1R [5: 0], D1G [5: 0], D1B [5: 0] Accordingly, the corresponding pixels are driven to display a color image of 64 × 64 × 64 colors.

  The display memory 13 is a memory that holds image data to be displayed. The image data D2R [5: 0] for red, green, and blue by 6 bits, respectively, in the order corresponding to the pixel arrangement of the display unit 12. ], D2G [5: 0] and D2B [5: 0] are output to red, green and blue digital signal processing circuits 14R, 14G and 14B, respectively.

  The digital signal processing circuits 14R, 14G, and 14B for red, green, and blue correct the gradations of the corresponding image data D2R [5: 0], D2G [5: 0], and D2B [5: 0], respectively. This digital signal processing circuit performs white balance adjustment and gamma correction processing by this gradation correction, and further increases the apparent gradation of the image displayed on the display unit 12. The red, green, and blue digital signal processing circuits 14R, 14G, and 14B are configured in the same manner except that characteristics relating to processing target image data, white balance adjustment, and gamma correction processing are different. Thus, in the following, the red digital signal processing circuit 14R will be described in detail, and the description of the other digital signal processing circuits 14G and 14B will be omitted.

  Here, the digital signal processing circuit 14R receives 6-bit gradation data D2R [5: 0], and inputs the gradation data D2 to the precision expansion circuit 16. Here, the accuracy extension circuit 16 increases the gradation of the image data D2 by a simple interpolation method and outputs 9-bit gradation data D4R [8: 0]. Specifically, the precision extension circuit 16 copies the upper 2 bits of the gradation data D2R [5: 0] and adds them to the lower 2 bits of the gradation data D2, and further adds a 0 bit indicating polarity to the uppermost position. Thus, the gradation data D2 having 64 gradations is converted into gradation data D4R [8: 0] having 256 gradations and output. In the process of increasing the gradation of the image data, various methods such as an interpolation process using peripheral pixel values can be applied.

  The correction table 17 is composed of, for example, a random access memory that records correction data D3R [8: 0] corresponding to the output data D4R [8: 0] of the precision expansion circuit 16, and addresses the image data D2R [5: 0]. By outputting the correction data D3R [8: 0] recorded as described above, the correction data D3R [8: 8] for correcting the gradation data D4R [8: 0] according to the value of the image data D2R [5: 0]. 0] is output. As a result, in this correction table 17, a 64 × 9-bit memory space is applied to the recording of the correction data D3R [8: 0]. For example, the correction table recording is updated according to the color temperature of the subject. Thus, the white balance can be adjusted, and the gamma adjustment can be performed by sequentially setting different correction data values in the high luminance portion and the low luminance portion.

  In the digital signal processing circuit 14R, as described above, a polarity bit is added to the most significant bit of the gradation data D4R [8: 0] by the accuracy extension circuit 16, and the correction table 17 corresponds to this accuracy. Corresponding to the output data D4R [8: 0] of the expansion circuit 16, the correction data D3R [8: 0] is stored in a two's complement format, and thereby the gradation data D4R [8: 0] related to the white balance adjustment and the like. ] Is simplified.

  Thus, in the digital signal processing circuit 14R, the arithmetic circuit 18 corrects the gradation data D4R [8: 0] with the correction data D3R [8: 0] and outputs the corrected data. Specifically, the arithmetic circuit 18 adds the gradation data D4R [8: 0] and the correction data D3R [8: 0] by the addition circuit 19 to thereby add the gradation data D4R [8: 0] to the correction data. Correction is performed by D3R [8: 0]. Further, the output data of the adder circuit 19 is input to the subsequent saturation processing circuit 20, where a value of 0 or less is set to the value 0, and a value of 255 or more is set to the value 255, whereby correction by the adder circuit 19 is performed. The result is corrected to a value that can be expressed by 8-bit gradation data. The saturation processing circuit 20 removes the most significant polarity bit from the processing result and outputs 8-bit gradation data D5R [7: 0] as a correction result.

  Thus, FIG. 3 is a chart showing a series of data changes related to processing up to the arithmetic circuit 18 in the digital signal processing circuit 14R. Through these processes, the digital signal processing circuit 14R adjusts the image quality of the image data D2R [5: 0] to increase the gradation.

  The digital signal processing circuit 14R applies this gradation to the upper bits D1R [5: 1] excluding at least the least significant bit D1R [0] of the gradation data D1R [5: 0] input to the display unit 12. The gradation data D5R [7: 3] is assigned so that the higher-order bits D5R [7: 3] corresponding to the gradation data D5R [7: 0], which is image data having a larger number of bits than the data D1R [5: 0], are assigned. 7: 0] are output to the display unit 12 as they are. Here, specifically, in this embodiment, among the 8-bit gradation data D5R [7: 0] output from the arithmetic circuit 18, the upper 5 bits D5R [7: 3] are input to the display unit 12. Assigned to the upper 5 bits D1R [5: 1] of the gradation data D1R [5: 0] to be output.

  On the other hand, the lower 3 bits D5R [2: 0] which are the remaining lower bits of the gradation data D5R [7: 0] are input to the time modulation circuit 21 which is an image data processing circuit. The grayscale data D1R [5: 0] is driven by a drive pattern in which the logical level changes in accordance with the value of the lower 3 bits of the image data in successive frames for the pixels and is different for adjacent pixels. Is set to the logical value of the lower bit D1R [0].

  Thus, in this embodiment, the 8-bit gradation data D5R [7: 0] is converted into 6-bit gradation data D1R [5: 0] by the processing of the lower 3 bits, and the display unit 12 is driven. The number of gradations of the display unit 12 by the lower-order bits D1R [0] of the gradation data D1R [5: 0] is the number of gradations of the lower-order bits D5R [2: 0] of the image data D5R [7: 0]. The display unit 12 is driven to be enlarged, and an image based on the image data D5R [7: 0] is displayed on the display unit 12.

  Here, in this drive pattern, the number of gradations of the lower-order bits D5R [2: 0] of the image data D5R [7: 0] is 8 gradations, whereas the gradation data D1R [5: 0] Since the number of gradations by the lower-order bit D1R [0] is one gradation, 1 corresponding to the number of gradations to be increased by the value 7 by 8 gradations-1 gradation corresponding to these gradation numbers. For one pixel, the logic level is set to sequentially and cyclically change in units of 7 frames.

  As a result, the time modulation circuit 21 changes the gradation related to the gradation data D1R [0] during the period of these seven consecutive frames when the logical value of the lower-order bits D5R [2: 0] is 0 (000). In contrast, when the logical value of the lower-order bits D5R [2: 0] sequentially increases, the gradation data D1R [0] is related to the increase in seven consecutive frames corresponding to the increase. When the number of times of starting up the gradation is increased and the logical value of the lower-order bit D5R [2: 0] is 7 (111), the gradation related to the gradation data D1R [0] is displayed in all of the seven consecutive frames. Launch continuously.

  The time modulation circuit 21 sufficiently disturbs the rising period so that the rising of the gradation for one pixel in such seven consecutive frames does not overlap on the time axis. That is, the gradation start timing is diffused on the time axis.

  Further, by the synchronized processing in the time modulation circuit 21 of each of the digital signal processing circuits 14R, 14G, and 14B, gradation increase by this drive pattern is simultaneously executed between corresponding pixels of red, green, and blue.

  On the other hand, in the adjacent pixels for the same color, when the values of the lower 3 bits are the same, this drive pattern is made different so that the instantaneous increase in gradation is inconspicuous. That is, the timing for raising the gradation is also diffused spatially. Here, in the range in which this drive pattern is made different, the drive pattern itself is made different in the horizontal direction and set to the range of two adjacent pixels of the same color. On the other hand, in the vertical direction, the drive pattern is set to be different by sequentially shifting the phase of the drive pattern, and as a result, the same drive pattern is defined by a range of 7 consecutive lines as in the repetition cycle of the drive pattern. Is repeated to set the gradation. In addition, by changing the driving pattern in different ranges in the horizontal direction and the vertical direction in this way, the driving pattern can be made different for the pixels of the same color adjacent in the oblique direction. The gradation change is made inconspicuous.

  Accordingly, in this embodiment, an image is displayed with a gradation finer than the minimum gradation that can be displayed on the display unit 12, and a high gradation image is displayed with a simple structure without a sense of incongruity.

  Specifically, the time modulation circuit 21 is configured as shown in FIG. Here, in the time modulation circuit 21, the counter 31 sequentially counts the first timing signal synchronized with the image data D2R in a cyclic manner within a range from 0 to 6 corresponding to the number of frames of the drive pattern. In this embodiment, a 3-bit counter is applied, and the count value is set simultaneously with the corresponding counter provided in the time modulation circuit 21 of the other digital signal processing circuits 14G and 14B by a reset pulse (not shown). After the reset, the count value is updated by the frame pulse FP supplied at a timing corresponding to the vertical blanking period of the image data D2R. As a result, as shown in FIG. 4, the counter 31 corresponds to the frame of the gradation data D5R [7: 0], and the lower 3 of the gradation data D5R [7: 0] assigned to the time axis modulation circuit 21. The count value is sequentially and cyclically changed in a range from a value 0 (000) to a value 6 (110) corresponding to the number of bits of the bits D5R [2: 0].

  Similarly to the counter 31, the counter 32 is a second counter that sequentially and cyclically counts the second timing signal synchronized with the image data D2R in a range from a value 0 to a value 6 corresponding to the number of frames of the drive pattern. In this embodiment, a 3-bit counter is applied, the count value of the counter 31 is loaded by the frame pulse FP, this count value is set to the initial value, and at a timing corresponding to the horizontal blanking period. The count value is sequentially and cyclically updated by the supplied horizontal pulse LP. As a result, as shown in FIG. 4, the counter 31 corresponds to the line of the gradation data D5R [7: 0], and the lower 3 of the gradation data D5R [7: 0] assigned to the time axis modulation circuit 21. The count value is sequentially and cyclically changed from the count value by the counter 31 in the range of the value 0 (000) to the value 6 (110) corresponding to the number of bits of the bits D5R [2: 0].

  The rearrangement circuit 33 disturbs the count value C1 by exchanging the most significant bit and the least significant bit of the count value C1 output from the counter 32, and thereby the lower side of the image data D5R [7: 0]. A value (value 0 to value 6) in a range corresponding to the number of gradations by bits D5R [2: 0] and the number of gradations by lower-order bits D1R [0] of gradation data D1R [5: 0] A first criterion value that is cyclically repeated in a random order is generated.

  The subsequent comparison circuit 34 compares the first determination reference value C2 by the rearrangement circuit 33 with the lower 3 bits D5R [2: 0] of the gradation data D5R [7: 0], and the comparison result is an even column. Is output as the gradation data Red [2] e for use, the lower bit D1R [0] of the gradation data D1R [5: 0] is set.

  Therefore, FIG. 5 shows the count value C1 of the counter 31 and the gradation data Red [2] e for even columns, which is the comparison result by the comparison circuit 34, and the lower 3 bits D5R of the gradation data D5R [7: 0]. It is a graph which shows the relationship with [2: 0]. As a result, the time modulation circuit 21 generates the drive pattern for the even-numbered columns according to the change of the logic level shown in FIG. 5, and the logic value of the least significant bit of the gradation data D1 is set by this drive pattern. It is made like that.

  In addition, the time axis modulation circuit 21 inverts the count value C1 of the counter 32 by the inverter 35, and similarly processes by the rearrangement circuit 36 and the comparison circuit 37, so that the odd-numbered driving pattern for the even-numbered column is different Create a drive pattern for the column. That is, in the time modulation circuit 21, the inverter 35 inverts the count value C1 of the counter 32 and outputs the count value C3, and the rearrangement circuit 36 replaces the most significant bit and the least significant bit of the count value C3. Thus, the count value C3 is disturbed and output, and the subsequent comparison circuit 37 receives the output value C4 of the rearrangement circuit 36 and the lower 3 bits D5R [2: 0] of the gradation data D5R [7: 0]. And output grayscale data Red [2] o for odd-numbered columns according to the comparison result.

  Thus, in this embodiment, the inverter 35 indirectly generates the second determination reference value by inverting the value of each bit of the first determination reference value by the rearrangement circuit 33 described above. The comparison circuit 34 determines the value of the first determination reference value and the remaining lower bits of the image data, and sets the logical value of the remaining lower bits of the gradation data. The comparison circuit 37 determines the value of the second determination reference value and the remaining lower bits of the image data, and sets the logical value of the lower bits of the gradation data. The second comparison circuit is configured.

  Further, the counters 31 and 32 constitute a determination reference value generating unit that generates such a first determination reference value.

  6 is compared with FIG. 5 by comparing the gradation data Red [2] o for odd columns, which is the comparison result by the comparison circuit 37, and the lower 3 bits D5R [5] of the gradation data D5R [7: 0]. 2: 0]. As a result, the time modulation circuit 21 generates a drive pattern for the odd-numbered columns using a drive pattern different from that for the even-numbered columns, and the selector 38 generates the gradation data Red [2] e for the even-numbered columns and the odd-numbered columns and the levels. The tone data Red [2] o are alternately output, so that the time modulation circuit 21 generates a drive pattern in units of a combination of two pixels in the horizontal direction.

  In the comparison circuit 34, when the output value C2 of the rearrangement circuit 33 is equal to the value of the gradation data D5R [2: 0], the output value C2 of the rearrangement circuit 33 is equal to the gradation data D5R [2: 0]. The output value is set to 0 as in the case where the value is larger than the value, whereas in the comparison circuit 37, the output value C3 of the rearrangement circuit 36 is equal to the value of the gradation data D5R [2: 0]. The output value is set to the value 1 in the same manner as when the output value C3 of the rearrangement circuit 36 is smaller than the value of the gradation data D5R [2: 0]. That is, when each bit of the count value D1 of the counter 32 is set to C3 [2], C3 [1], C3 [0], the comparison circuit 34 has D5R [2: 0]> [C3 [0], C3 [1]. ], C3 [2]] is output when the value is true, whereas the comparison circuit 34 indicates that D5R [2: 0] ≧ [IC3 [0], IC3 [1], IC3 [2]] is true. In this case, the value 1 is output. Here, I indicates inversion of the logical value.

  As a result, as shown in FIG. 7, in this liquid crystal display device 11, in accordance with the value of the lower 3 bits D5R [2: 0] of the gradation data D5R [7: 0], the corresponding pixel levels in the continuous lines are displayed. For example, when the lower 3 bits D5R [2: 0] of the gradation data D5R [7: 0] are held at the value 011 in the entire screen, continuous frames are displayed as shown in FIG. As indicated by the order of A) to (C), the gradation of the corresponding pixel is raised. In FIGS. 7 and 8 and FIGS. 9 to 14 below, the start-up of one gradation is shown by painting.

  Thus, the drive pattern is sequentially and cyclically switched in units of 7 frames and 7 lines, and the two adjacent pixels of the same color in the horizontal direction are switched, thereby switching these 7 lines adjacent in the vertical direction in the horizontal direction. With respect to two consecutive pixels of the same color, the rise of gradation in seven consecutive frames corresponds as shown in FIGS. 9 to 14 according to the value of the lower 3 bits D5R [2: 0]. The gradation of the pixel is raised. Here, when the value of the lower 3 bits D5R [2: 0] is 0 (000), no gradation is raised, whereas the value of the lower 3 bits D5R [2: 0] is 7 ( In the case of (111), it goes without saying that the gradation is held up.

  As a result, the liquid crystal display device 11 apparently increases the gradation and is correct even in the high-luminance portion and the low-luminance portion obtained by performing gamma correction as shown in FIG. 15 in comparison with FIG. Displaying with gradation, the image quality deterioration due to the decrease in gradation is effectively avoided accordingly.

(2) Operation of Embodiment In the above configuration, in the liquid crystal display device 11 (FIG. 2), three systems of image data D2R [5: 0] and D2G [ 5: 0] and D2B [5: 0] are output simultaneously and in parallel in raster scan order, and these image data D2R [5: 0], D2G [5: 0], and D2B [5: 0] are digital signal processed, respectively. Processed by the circuits 14R, 14G, and 14B and converted into gradation data D1R [5: 0], D1G [5: 0], and D1B [5: 0]. These gradation data D1R [5: 0] and D1G [ The display unit 12 is driven by 5: 0] and D1B [5: 0], and the image data D2R [5: 0], D2G [5: 0], and D2B [5: 0] are displayed.

  The image data D2R [5: 0], D2G [5: 0], and D2B [5: 0] provided for display in this way are converted by the precision extension circuit 16 in the digital signal processing circuits 14R, 14G, and 14B, respectively. After the number of bits is increased, the value is corrected by the adder circuit 19 by the correction data D3R [8: 0] output from the correction table 17, and the values on the high luminance side and the low luminance side are rounded by the subsequent saturation processing circuit 20. Thus, white balance adjustment and gamma correction are performed.

  In the liquid crystal display device 11, the upper 5 bits D5R [7: 3] among the gradation data D5R [7: 0], which is 8-bit image data that has been subjected to white balance adjustment and gamma correction in this way, is assigned to the floor. The time modulation circuit, which is an image data processing circuit, is assigned to the upper bits of the key data D1R [5: 0] and directly output to the display unit 12 while the remaining lower 3 bits D5R [2: 0] 21, the logic level changes in successive frames in accordance with the value of the lower 3 bits D5R [2: 0], and the drive pattern is different for adjacent pixels (FIGS. 4 to 5). 6) The logical value of the remaining lower bits D1R [0] of the gradation data D1R [5: 0] is set.

  Thus, for example, when a still image is displayed, if the lower 3 bits D5R [2: 0] are set to the value 000 in 7 consecutive frames, the lower bits D1R [5: 0] When the lower 3 bits D5R [2: 0] are set to the value 001, no increase is made in the gradation of the corresponding pixel held at the value 0, but when the consecutive 7 frames are set. In one frame, the low-order bits D1R [5: 0] are raised to the value 1, and the corresponding gradation is raised for the period of one frame. Key is expressed. Similarly, when the lower 3 bits D5R [2: 0] are set to the value 010, the lower bits D1R [5: 0] are raised to the value 1 in 2 of the 7 consecutive frames. When the corresponding gradation is raised for a period of 2 frames, and the lower 3 bits D5R [2: 0] are set to the value 011, the lower bits D1R in 3 of the 7 consecutive frames [5: 0] is raised to the value 1, and the gradation of the corresponding pixel is raised for a period of 3 frames, and the gradation that is finer than the gradation that can be displayed on the display unit 12 is expressed accordingly. . Similarly, in accordance with the value of the lower 3 bits D5R [2: 0], the number of frames for raising the gradation in these 7 consecutive frames is increased, and the value of the lower 3 bits D5R [2: 0] is increased. In the case of 111, the gradation is raised in all of these seven consecutive frames. As a result, in the liquid crystal display device 11, the display unit 12 can display an image with an apparently increased gradation corresponding to the resolution of the gradation data D1R, and can display a high-quality image accordingly. Has been made.

  In this way, when displaying the image by setting the least significant bit of the gradation data D1R, the liquid crystal display device 11 uses a drive pattern in which the logic level changes according to the value of the lower bit of the image data. By setting, it is possible to increase the number of gradations without a sense of incongruity without making the rise of gradations inconspicuous by setting the drive pattern. In other words, by setting the logical value of the lower-order bit of the gradation data with a different driving pattern for adjacent pixels, it is possible to increase the number of gradations without a sense of incongruity by making the gradation rise inconspicuous. it can. As a result, for example, as described above with reference to FIGS. 18 and 19, it is possible to prevent deterioration of gradation in the high luminance portion and the low luminance portion due to gamma correction. Further, colors that can be expressed on the display unit 12 can be increased. In this embodiment, 4 × 64 × 4 × 64 × 4 × 64 colors are expressed using the display unit 12 with 64 × 64 × 64 colors. be able to.

  In addition, the number of gradations can be increased simply by processing the image data input to the display unit 12, and the gradation is increased with a simple configuration by setting the least significant bit according to the drive pattern. Can be made.

  Specifically, in this embodiment (FIG. 1), the number of gradations 2 by the least significant bit D1R [0] of the gradation data D1R [5: 0] and the corresponding lower side of the image data D5R [7: 0]. A frame pulse FP, which is a first timing signal synchronized with the image data D5R [7: 0], is sequentially and cyclically within a range of count values 0 to 6 according to the number of gradations 8 by the bits D5R [2: 0]. First, the first counter 31 counts. Further, the count value of the first counter 31 is loaded into the second counter 32 by the first timing signal FP, and in a similar range of 0 to 6, the cycle is shorter than that of the first timing signal FP. A horizontal pulse LP, which is a second timing signal synchronized with the image data, is sequentially and cyclically counted by the second counter 32. Further, by replacing the upper bits and lower bits of the count value C1 by the second counter 32 by the rearrangement circuit 33, the number of gradations 2 by the least significant bits D1R [0] of the gradation data D1R [5: 0] And 0 to 6 in a range corresponding to the number of gradations 8 by the corresponding lower-order bits D5R [2: 0] of the image data D5R [7: 0] are sequentially and cyclically repeated in a random order. Is generated, and the comparison reference value C2 and the lower-order bits D5R [2: 0] are sequentially compared by the comparison circuit 34 to set the logical value of the least significant bit D1R [0]. Thus, the logical value of the least significant bit D1R [0] is set by the previous driving pattern.

  Thus, in the vertical direction, the phase of the drive pattern is shifted by one frame unit (FIGS. 7, 9 to 14), and even when the same logical value is assigned to adjacent pixels, The rise of gradation can be made inconspicuous.

  Further, a second determination reference value obtained by inverting each logical value is generated by the inverter 35 and the rearrangement circuit 36 with respect to the determination reference value C2 generated in this way, and this second determination reference value is obtained. And the corresponding lower-order bits D5R [2: 0] of the image data D5R [7: 0] are compared by the comparison circuit to set the logical value of the least significant bit D1R [0], and the first determination reference value is used. By alternately selecting the setting and the setting based on the second determination reference value by the selector 38, which is a selection circuit, the gradation of the pixels adjacent in the horizontal direction can be changed by changing the drive pattern itself based on the same generation reference. Even when the same logical value is assigned to adjacent pixels (see FIG. 7, FIG. 9 to FIG. 14), the gradation rise can be made inconspicuous.

(3) Advantages of the embodiment According to the configuration described above, the gradation data is generated by the drive pattern whose logical level changes in synchronization with the image data in accordance with the value of the image data assigned to the lower bits of the gradation data. By setting the logical value of the lower-order bits and expanding the number of gradations by the lower-order bits of the gradation data to the number of gradations of the image data, the display unit is driven, and the levels that can be expressed with a simple configuration. The logarithm can be increased.

  Specifically, by changing the phase of the drive pattern between adjacent pixels, the drive pattern is set different for adjacent pixels, and the logical value of the lower-order bits of the gradation data is set. By increasing the number of gradations that can be expressed with a simple configuration, an image due to the increase in gradation can be displayed without a sense of incongruity.

  That is, the first timing signal synchronized with the image data is sequentially and cyclically counted within the range of the count value according to the number of gradations by the lower order bits of the gradation data and the number of gradations by the lower order bits of the image data. The first counter and the count value of the first counter are loaded by this first timing signal, and the same count value range is synchronized with the image data having a shorter period than the first timing signal. A second counter that sequentially and cyclically counts the second timing signal, and the upper and lower bits of the count value by the second counter are replaced, and the number of gradations by the lower bits remaining in the gradation data A reference value is generated by cyclically repeating values in a range corresponding to the number of gradations of the remaining lower bits of the image data in a random order. By determining the value of the low-order bits of the image data based on the replacement circuit and the determination reference value and setting the logical value of the low-order bits of the gradation data, the low-order side of the gradation data remaining according to the drive pattern By providing the comparison circuit for setting the logical value of the bit, the number of gradations that can be expressed by a digital signal processing circuit with a simple configuration can be increased, and an image due to the increase in gradation can be displayed without a sense of incongruity.

  In addition, by making the drive pattern itself different between adjacent pixels, the logical value of the lower-order bits of the gradation data can be set with a different drive pattern for the adjacent pixels. By increasing the number of gradations that can be expressed by this, it is possible to display an image due to the increase in gradations without a sense of incongruity.

  Specifically, a first value in which a value in a range corresponding to the number of gradations by the lower-order bits of the gradation data and the number of gradations by the lower-order bits of the image data is sequentially and cyclically repeated in a random order. A first determination reference value generating means for generating a determination reference value; a second determination reference value generating means for generating a second determination reference value by inverting the value of each bit of the first determination reference value; The value of the lower bit of the image data is determined by the first and second determination reference values, the logical value of the lower bit of the gradation data is set, and the setting based on the first and second determination criteria is alternately performed. Even if it is selected and output to the display unit, the number of gradations that can be expressed by a digital signal processing circuit with a simple configuration is increased, and an image due to an increase in gradation can be displayed without a sense of incongruity.

  In addition, by combining these in the vertical direction and the horizontal direction, that is, by changing the drive pattern for the pixels adjacent in the horizontal direction, the drive pattern of the pixels adjacent in the vertical direction is changed. By differentiating the phase between adjacent pixels, it is possible to efficiently configure such a digital signal processing circuit by changing the drive pattern when the remaining lower bits of the image data for the adjacent pixels have the same value. Thus, the number of gradations that can be expressed can be increased, and an image due to the increase in gradation can be displayed without a sense of incongruity.

  In this embodiment, in place of the time modulation circuit shown in FIG. 1, a time modulation circuit shown in FIG. 16 is applied to constitute a liquid crystal display device. In this embodiment, the configuration is the same as that of the liquid crystal display device 11 according to the first embodiment except that the configuration of the time modulation circuit 41 is different.

  In this time modulation circuit 41, a counter 43 is further provided after the counter 32 provided in the time modulation circuit 21 described above for the first embodiment, and the count value of the counter 43 is input to the rearrangement circuit 33. . Here, the counter 43 loads the count value of the counter 32 by the horizontal pulse LP, and counts the clock CK synchronized with the image data D5R in the same value range 0 to 6 as the counter 32.

  Thereby, in this embodiment, the phase of the drive pattern is sequentially changed both in the vertical direction and in the horizontal direction, and image data D5R [7: 0] or the like having the same logical value is assigned to adjacent pixels of the same color. Even in such a case, the drive pattern is made different so as to eliminate the uncomfortable feeling accompanying the increase in gradation.

  As in this embodiment, even if the drive pattern phase is sequentially changed in both the horizontal direction and the vertical direction and the drive pattern is made different between adjacent pixels, the same effect as in the first embodiment can be obtained. it can.

  In the above-described embodiment, the case where the phase of the drive pattern is sequentially changed in the vertical direction has been described. However, the present invention is not limited to this, and the drive pattern itself is also used in the vertical direction by using an inverter. You may make it differ.

  Further, in the above-described embodiment, as described above with reference to FIG. 1, the case where the bits are rearranged by the rearrangement circuit after the polarity is inverted through the inverter has been described. The configuration order may be reversed.

  In the above-described embodiment, the case where the determination reference value is generated by counting the frame pulse and the horizontal pulse by the counter has been described. However, the present invention is not limited to this. For example, the determination reference value is obtained by sequentially reading records from the memory. For example, various generation methods can be widely applied.

  In the above-described embodiments, the case where the gradation of 1 bit is expanded to the gradation of 3 bits has been described. However, the present invention is not limited to this, and various numbers of bits can be used as necessary. Can be set to

  In the above-described embodiment, the case where the number of bits of the input image data is enlarged and displayed on the display unit has been described. However, the present invention is not limited to this, and the number of bits is larger than the gradation data of the display unit. The present invention can be widely applied to a case where a large number of image data is input and processed.

  In the above-described embodiments, the case where the display unit is driven by the liquid crystal display panel has been described. However, the present invention is not limited to this, and the present invention can be widely applied to the case where the display unit is driven by EL (Electro Luminescence). Can do.

  The present invention can be applied to a liquid crystal display device in which a drive circuit is integrally formed on an insulating substrate.

It is a block diagram which shows the time modulation circuit applied to the liquid crystal display device which concerns on Example 1 of this invention. It is a block diagram which shows the liquid crystal display device which concerns on Example 1 of this invention. 3 is a chart for explaining the operation of the liquid crystal display device of FIG. 2. 2 is a chart for explaining the operation of the counter of the time modulation circuit of FIG. 1. 2 is a chart for explaining a driving pattern in the time modulation circuit of FIG. 1. 3 is a chart for explaining driving patterns of adjacent pixels in the time modulation circuit of FIG. 1. It is a graph which shows the relationship of the adjacent pixel of a horizontal direction and a vertical direction. It is an approximate line figure used for explanation of a rise of gradation in a frame direction. FIG. 10 is a schematic diagram for explaining the start of gradation when the lower 3 bits of the gradation data D5R have a value of 001. FIG. 11 is a schematic diagram for explaining the start-up of a gray scale when the lower 3 bits of the gray scale data D5R have a value of 010. FIG. 10 is a schematic diagram for explaining the start of gradation when the lower 3 bits of the gradation data D5R are the value 011. FIG. 10 is a schematic diagram for explaining the start of gradation when the lower 3 bits of gradation data D5R have a value of 100. FIG. 11 is a schematic diagram for explaining the start of gradation when the lower 3 bits of the gradation data D5R are a value 101. FIG. 10 is a schematic diagram for explaining the start of gradation when the lower 3 bits of the gradation data D5R are a value 110; It is a basic diagram with which it uses for description of the improvement of the precision in a gamma correction. FIG. 6 is a block diagram illustrating a time modulation circuit according to a second embodiment. It is a block diagram with which it uses for description of the conventional gamma correction. It is a characteristic curve figure which shows the characteristic of a gamma correction. It is an approximate line figure used for explanation of image quality degradation by gamma correction.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,11 ... Liquid crystal display device, 2, 12 ... Display part, 3, 13 ... Display memory, 4, 17 ... Correction table, 14R, 14G, 14B ... Digital signal processing circuit, 16 ... Accuracy expansion Circuit, 21, 41 ... Time modulation circuit, 31, 32, 43 ... Counter, 33, 36 ... Rearrangement circuit, 35 ... Inverter, 34, 37 ... Comparison circuit, 38 ... Selector

Claims (9)

In an image display device that sequentially inputs gradation data indicating the gradation of each pixel to the display unit and displays an image corresponding to the gradation data on the display unit.
Assigning upper bits corresponding to image data having a larger number of bits compared to the gradation data to the upper bits excluding at least the least significant bit of the gradation data;
Image data processing circuit
The lower level where the gradation data remains due to the drive pattern that changes in logic level according to the value of the lower side bits remaining in the image data in successive frames for one pixel and is different for adjacent pixels By setting the logical value of the bit,
The display unit is driven by expanding the number of gradations of the display unit by the lower-order bits remaining in the gradation data to the number of gradations by the lower-order bits remaining in the image data, and the image by the image data is displayed. An image display device characterized by being displayed on a screen. The image data processing circuit includes:
By making the phase of the drive pattern different between adjacent pixels,
The image display device according to claim 1, wherein a logical value of a lower-order bit that remains in the gradation data is set according to a driving pattern that is different for the adjacent pixels. The image data processing circuit includes:
A first timing signal synchronized with the image data is sequentially applied within a range of count values corresponding to the number of gradations by the remaining lower bits of the gradation data and the number of gradations by the remaining lower bits of the image data. A first counter that cyclically counts;
The count value of the first counter is loaded by the first timing signal, and the number of gradations according to the remaining lower bits of the gradation data and the number of gradations according to the remaining lower bits of the image data are determined. A second counter that sequentially and cyclically counts a second timing signal synchronized with the image data in a cycle shorter than that of the first timing signal within a range of count values;
Replacing the upper and lower bits of the count value by the second counter according to the number of gradations by the remaining lower bits of the gradation data and the number of gradations by the remaining lower bits of the image data A rearrangement circuit for generating a criterion value in which the values of the range are cyclically repeated sequentially in a random order; and
By determining the value of the lower-order bits remaining in the image data based on the determination reference value and setting the logical value of the lower-order bits remaining in the gradation data, the lower-order side remaining in the gradation data is determined according to the driving pattern. The image display apparatus according to claim 2, further comprising a comparison circuit that sets a logical value of the bit. The image data processing circuit includes:
By making the drive pattern itself different in the adjacent pixels,
The image display device according to claim 1, wherein a logical value of a lower-order bit that remains in the gradation data is set according to a driving pattern that is different for the adjacent pixels. The image data processing circuit includes:
A value in a range corresponding to the number of gradations by the lower-order bits remaining in the gradation data and the number of gradations by the lower-order bits remaining in the image data is sequentially and cyclically repeated in a random order. A first determination reference value generation circuit for generating a determination reference value of
A second determination reference value generation circuit that generates a second determination reference value by inverting the value of each bit of the first determination reference value;
A first comparison circuit configured to determine a value of the first determination reference value and the lower-order bits remaining in the image data and set a logical value of the lower-order bits remaining in the gradation data;
A second comparison circuit for determining a value of the second determination reference value and the remaining lower bits of the image data and setting a logical value of the remaining lower bits of the gradation data;
The image display device according to claim 4, further comprising: a selector that alternately selects a comparison result by the first and second comparison circuits and outputs the comparison result to the display unit. The image data processing circuit includes:
For pixels adjacent in the horizontal direction, the drive pattern itself is made different,
For pixels adjacent in the vertical direction, the phase of the drive pattern differs between adjacent pixels,
The image display device according to claim 1, wherein a logical value of a lower-order bit that remains in the gradation data is set according to a driving pattern that is different for the adjacent pixels. The image data processing circuit includes:
A first timing signal synchronized with the image data is sequentially applied within a range of count values corresponding to the number of gradations by the remaining lower bits of the gradation data and the number of gradations by the remaining lower bits of the image data. A first counter that cyclically counts;
The count value of the first counter is loaded by the first timing signal, and the number of gradations according to the remaining lower bits of the gradation data and the number of gradations according to the remaining lower bits of the image data are determined. A second counter that sequentially and cyclically counts a second timing signal synchronized with the image data in a cycle shorter than that of the first timing signal within a range of count values;
Replacing the upper and lower bits of the count value by the second counter according to the number of gradations by the remaining lower bits of the gradation data and the number of gradations by the remaining lower bits of the image data A rearrangement circuit for generating a first determination reference value in which the values of the range are cyclically repeated sequentially in a random order;
Second determination reference value generating means for generating a second determination reference value by inverting the value of each bit of the first determination reference value;
A first comparison circuit configured to determine a value of the first determination reference value and the lower-order bits remaining in the image data and set a logical value of the lower-order bits remaining in the gradation data;
A second comparison circuit for determining a value of the second determination reference value and the remaining lower bits of the image data and setting a logical value of the remaining lower bits of the gradation data; and the first and second The image display device according to claim 6, further comprising: a selector that alternately selects a comparison result by the comparison circuit and outputs the comparison result to the display unit. The first timing signal is a frame pulse supplied in a period corresponding to a vertical blanking period;
The image display apparatus according to claim 7, wherein the second timing signal is a horizontal pulse supplied in a period corresponding to a horizontal blanking period. In the image display method of sequentially inputting gradation data instructing the gradation of each pixel to the display unit and displaying an image corresponding to the gradation data on the display unit,
Assigning upper bits corresponding to image data having a larger number of bits compared to the gradation data to the upper bits excluding at least the least significant bit of the gradation data;
The lower level where the gradation data remains due to the drive pattern that changes in logic level according to the value of the lower side bits remaining in the image data in successive frames for one pixel and is different for adjacent pixels By setting the logical value of the bit,
The display unit is driven by expanding the number of gradations of the display unit by the lower-order bits remaining in the gradation data to the number of gradations by the lower-order bits remaining in the image data, and the image by the image data is displayed. An image display method characterized by displaying on a screen.

Images