JP2005056334A - Data taking-in circuit for taking in data from synchronous memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data taking-in circuit for taking in data from a synchronous memory that enables a DDR interface for taking in input signal data to eliminate a difference in delay between signals of the input signal data at the rising and trailing edges of each data strobe signal. <P>SOLUTION: The data taking-in circuit, which takes in data bus signals (DQn) from a synchronous memory at the rising and trailing edges of each data strobe signal (DQS), is provided with a variable delay circuit for delaying each data bus signal by a predetermined delay time and a delay time setting circuit for adjustably setting the delay time used in the variable delay circuit. More preferably, the data taking-in circuit for taking in the data from the synchronous memory is provided with a means for automatically controlling signals outputted from the delay time setting circuit to the variable delay circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit using a high-speed parallel data bus interface.

  Conventionally, a data bus signal (DQ) is synchronized with a data strobe signal (DQS) in a high-speed parallel interface such as a method of transferring data using both rising and falling of a clock signal (so-called DDR method). Therefore, it is important to suppress the variation between the data bus signals when capturing the data. Factors that cause variations in each data bus signal include differences in layout and wiring length inside the LSI chip, differences in bonding length within the LSI package in which the LSI chip is embedded, distance from the bonding location to the lead, or mounting the LSI chip There may be a difference in wiring layout and wiring length on the substrate.

  FIG. 13A is a timing chart showing a state in which the above-described variation occurs between data bus signals. T1 shown in FIG. 13A is a variation between data bus signals generated in the package and the substrate, and T2 is a sum of the variation in T1 and the variation between data bus signals generated inside the LSI. is there. Here, W represents a data valid window in which the data bus signal can be normally captured by the data strobe signal. Further, FIG. 13B shows a mode in which the variation between the data bus signals is increased. Due to the large variation between the data bus signals, there is a possibility that the data valid window W becomes small, and there is a possibility that the data cannot be taken in normally.

  In order to prevent such a problem, it is necessary to suppress the delay difference between the data bus signals in consideration of the total variation. Conventionally, in order to suppress this delay difference, a method of optimizing a layout or inserting a buffer or the like corresponding to the delay difference at the time of LSI development is known (see, for example, Patent Document 1). Such a method is effective when the package is fixed or when a delay difference between data bus signals on the board side is also guaranteed.

JP 2002-042498 A

  However, since products for specific applications such as ASICs are required to have a variety of packages and flexibility to change the printed circuit board associated therewith, LSI chips can be connected between buses even after their completion. It is desirable to be able to change the signal delay.

  The present invention has been made in view of the above technical problem, and eliminates the delay difference between each signal of the input signal data in the DDR interface that takes in the input signal data at the rising edge and falling edge of the data strobe signal. It is an object of the present invention to provide a data fetch circuit from a synchronous memory that can be used.

  In a first aspect of the present invention, there is provided a data fetch circuit that fetches a data bus signal (DQn) from a synchronous memory at the rising and falling edges of a data strobe signal (DQS). A variable delay circuit for delaying the bus signal by a predetermined delay time; and a delay time setting circuit for setting the delay time used in the variable delay circuit to be adjustable.

  In the second aspect of the present invention, the data fetch circuit from the synchronous memory further has means for automatically controlling an output signal from the delay time setting circuit to the variable delay circuit.

  According to the invention of claim 1 of the present application, the data fetch circuit that fetches the data bus signal (DQn) from the synchronous memory at the rising and falling edges of the data strobe signal (DQS) Since it has a variable delay circuit that delays by the delay time and a delay time setting circuit that sets the delay time used in the variable delay circuit to be adjustable, it is possible to change the package after the LSI is completed and the printed circuit board The variation between the data bus signals can be suppressed flexibly corresponding to the change.

  According to the second invention of the present application, the data fetch circuit from the synchronous memory has means for automatically controlling the output signal from the delay time setting circuit to the variable delay circuit. It is possible to cope with the change of the package or the change of the printed board after the completion of the LSI without adjustment.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
Embodiment 1 FIG.
FIG. 1 is a block diagram of a data acquisition circuit according to the first embodiment of the present invention that is mounted on an LSI using a high-speed parallel data bus interface and performs data transmission / reception with a DDR-SDRAM. The data fetch circuit 10 includes, as a basic configuration, a DLL (Delay Locked Loop) circuit 1, a DQS delay calculation circuit 2, a DQS variable delay circuit 3, a DQ0 to DQ7 variable delay circuit 4, and a delay time setting register 5. Register control circuit 6 and flip-flops FF1 to FF16.

  The DLL circuit 1 receives the reference clock signal (CLK) output from the DDR-SDRAM and measures its cycle. The DQS delay calculation circuit 2 calculates the delay time of the DQS variable delay circuit 3 by using the CLK cycle measured by the DLL circuit 1 and the delay angle input (GEAR) with respect to the CLK cycle.

  The DQS variable delay circuit 3 is a circuit that delays the data strobe signal (DQS) output from the DDR-SDRAM, while the DQ0 to DQ7 variable delay circuit 4 is a data bus input (DQ0) output from the DDR-SDRAM. Delay ~ 7). The delay time setting register 5 sets a delay time used for the DQS variable delay circuit 3 and DQ0 to DQ7 variable delay circuit 4, and a signal DQSSEL is also input to the DQS variable delay circuit 3 as a signal representing the delay time. The signals DQ0SEL, DQ1SEL, DQ2SEL, DQ3SEL, DQ4SEL, DQ5SEL, DQ6SEL, and DQ7SEL are output to the DQ0-7 variable delay circuit 4, respectively. The register control circuit 6 rewrites the delay time set in the delay time setting register 5 based on signals SCLK (serial clock), SYNC (synchronization data), and SDATA (serial data) input from outside the LSI. The time setting register 5 is controlled. The flip-flops FF1 to FF16 take in DQO0 to DQO7 output from each of the DQ0 to DQ7 variable delay circuits 4 at the rise or fall of the output DQSO of the DQS variable delay circuit 3.

  More specifically, the DQS delay calculation circuit 2 calculates CLK cycle / 360 ° × GEAR using the CLK cycle and GEAR. This calculation result (DEGDATA) is output to the delay time setting register 5 and supplied from the delay time setting register 5 to the DQS variable delay circuit 3 as a signal DQSSEL. As shown in FIG. 14, the data bus input (DQ0 to DQ7) and the data strobe signal (DQS) are input at the same timing, but in order to capture data internally, the rising and falling edges of DQS are data. It needs to be located at the center value of the effective window, ie delayed by 90 °. The processing in the DQS delay calculation circuit 2 copes with such a need. By this processing, the DQS variable obtained by delaying the DQS by 90 ° is output from the DQS variable delay circuit 3, and the DQ0 to DQ7 variable delay circuit 4 is output. Is latched in FF1-8 at the rising edge of DQSO, and is latched in FF9-16 at the falling edge of DQSO. As can be seen from FIG. 1, in this embodiment, the signal DQSO output from the DQS variable delay circuit 3 is output to each of the FF1 to FF16, and the DQO0 output from the DQ0 variable delay circuit 4 is FF1 and The DQO1 output from the DQ1 variable delay circuit 4 to the FF9 is transferred to the FF2 and FF10, the DQO2 output from the DQ2 variable delay circuit 4 is transferred to the FF3 and FF11, and the DQO3 output from the DQ3 variable delay circuit 4 is transferred to the FF4 and FF12. DQO4 output from the DQ4 variable delay circuit 4 is transferred to the FF4 and FF13, DQO5 output from the DQ5 variable delay circuit 4 is transferred to the FF5 and FF14, DQO6 output from the DQ6 variable delay circuit 4 is transferred to the FF6 and FF15, and DQ7. The DQO 7 output from the variable delay circuit 4 is output to the FF 7 and FF 16. That.

  For example, in the specification of DDR266 which is an interface for DDR-SDRAM, the data rate is 266 MHz, the clock frequency is 133 MHz, and 7.5 ns (7500 ps) per cycle. That is, in the specification of DDR266, when DQS is delayed by 90 ° of one cycle, 7.5 ns ÷ 4 = 1.8 ns is delayed by DQS variable delay circuit 3. Note that the ideal delay amount for DQS is 90 °, but it may not be 90 ° depending on the internal wiring of the LSI. For this reason, as is known in the art, GEAR is input to the DQS delay calculation circuit 2. This angle can be changed.

FIG. 2 is a circuit diagram common to each of the DQ0 to DQ7 variable delay circuits 4. In this variable delay circuit 4, the input signal IN (specifically, DQ 0 to DQ 7) is delayed by passing through the delay cells 42 of 1 to 5 stages. The number of delay cells 42 through which the input signal IN passes is determined by the input state of the signals SEL0 to SEL2 to the decode circuit 41, and the delay amount of the variable delay circuit 4 can be changed by changing the input state. Yes. The delayed signal is output to the flip-flops FF1 to FF16 through the output gate 43.
Specifically, for example, a delay of about 50 ps per delay cell is possible, and the delay time is variable in the range of 50 to 250 ps. Note that the number of stages of the delay cells 42 can be increased or decreased according to the delay time that is actually required because the specifications of the data rate and the delay value per stage of the delay cells vary depending on the LSI manufacturing process. It is not limited to five stages.

  FIG. 3 is a circuit diagram of the DQS variable delay circuit 3. In the DQS variable delay circuit 3, the input signal IN (specifically, DQS) is delayed by passing through the delay cell 32 having 1 to 256 stages. The number of delay cells 32 through which the input signal IN passes is determined by the input state of the signals SEL0 to SEL7 to the decode circuit 31, and the delay time can be changed by changing the input state. The delayed signal is output to the flip-flops FF1 to FF16 through the output gate 33.

  Specifically, for example, assuming that a delay of about 50 ps per delay cell is possible, the delay time is variable in the range of 50 to 12800 ps. Note that the number of stages of the delay cells 32 can be increased or decreased according to the required delay time, as in the case of the DQ0 to DQ7 variable delay circuit 4, and is not limited to 256 stages.

  FIG. 4 is a diagram showing a detailed configuration of the delay time setting register 5 and the register control circuit 6 for setting the delay amount in the DQS variable delay circuit 3 and the DQ0 to DQ7 variable delay circuits 4. FIG. 5 is a timing chart of signals input to the register control circuit 6 and signals written to the delay time setting register 5 via the register control circuit 6. The delay time setting register 5 includes a DQS delay register 51, DQ0 to DQ7 delay registers 52, and an adder circuit 53. On the other hand, the register control circuit 6 includes a serial-parallel conversion circuit 61, a write control circuit 62, and the like. It is composed of

  Serial data (SDATA), serial clock signal (SCLKK), and serial synchronization signal (SSYNC) are input to the register control circuit 6. More specifically, SDATA including register selection addresses A0 to A3 and register write data D0 to D7 is input to the serial-parallel conversion circuit 61, and SCLK and SSYNC are both serial-parallel conversion circuit 61 and write control circuit 62. Are input to both. The serial-parallel conversion circuit 61 converts the input SDATA into a register selection address and register write data in parallel format. Among them, the register write data (WDATA) is converted into the DQS delay register 51 and DQ0 on the delay time setting register 5 side. The DQ7 delay register 52 and the address are output to the write control circuit 62.

  The write control circuit 62 receives SCLK and SSYNC, outputs the clock signal WCKDQS to the DQS delay register 51 on the delay time setting register 5 side, and outputs the clock signals WCKDQ0, WCKDQ1, WCKDQ2, WCKDQ3, WCKDQ4, WCKDQ5 WCKDQ6 and WCKDQ7 are output to DQ0-7 delay register 52, respectively. At the same time, the write control circuit 62 designates where the register write data is written to the delay register 52 based on the register selection address from the serial-parallel conversion circuit 61.

  In the delay time setting register 5, the delay amounts of DQS and DQ0 to DQ7 are set based on the signal sent from the register control circuit 6 side. First, the DQS delay amount includes a signal generated by the DQS delay register 51 based on WDATA from the serial-parallel conversion circuit 61 and WCKDQS from the write control circuit 62, and DEGDATA sent from the DQS delay calculation circuit 2. Are added to obtain the signal DQSSEL. On the other hand, DQ0SEL to DQ7SEL are generated by the DQS delay register 51 based on WDATA from the serial-parallel conversion circuit 61 and WCKDQ0 to WCKDQ7 from the write control circuit 62 as delay amounts of DQ0 to DQ7.

  Signals DQSSEL and DQ0SEL to DQ7SEL are bus signals. As described above, the number of buses, that is, the number of bits, varies depending on the number of delay stages in each of the variable delay circuits 3 and 4. As described above, the delay amount output from the delay time setting register 5 can be rewritten from outside the LSI via the serial interface of SDATA, SCLK, and SSYNC.

  In this embodiment, a non-volatile memory is used as the delay register 52 on the delay time setting register 5 side, and data writing in the delay register 52 is executed once at the time of LSI shipping test or in the field. . When a flip-flop is used as the delay register 52, the address and data are written once when the system is initialized when the power is turned on. Further, in this embodiment, the example of the control for writing to the delay time setting register 5 is taken from the serial communication and the outside of the LSI, but the means for writing to the delay time setting register 5 and its path are not important. It is important that the value of the delay time setting register 5 can be changed after LSI development.

As is clear from the above description, by mounting the data acquisition circuit according to the first embodiment on an LSI, a variation occurs between data buses due to a package change after LSI development or a change in printed circuit board, Even when it is necessary to adjust the timing of the data bus, the adjustment can be easily performed by changing the delay amount of the variable delay circuit 52 arranged in the data bus and the data strobe.
In the present embodiment, for simplicity of explanation, eight data buses are used. However, the number of buses can be increased without being limited to this.

Next, another embodiment of the present invention will be described. In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and further description thereof is omitted.
Embodiment 2. FIG.
FIG. 6 is a block diagram of a DDR-SDRAM data fetch circuit incorporating the DQS variable delay circuit according to the second embodiment of the present invention. In the first embodiment described above, since the DQS data input to the DQS variable delay circuit 3 is taken in at both rising and falling edges, a single-stage delay cell is used when a plurality of delay cells are used. The difference between the rise and fall in the delay cell is accumulated for the number of stages. For example, as can be seen from FIG. 8 (a), when delays of D3 and D4 occur at the rise and fall, respectively, when a one-stage delay cell is used, a 100-stage delay cell is obtained. When used, as shown in FIG. 8 (b), it is considered that delays (D5 and D6) 100 times greater than D3 and D4 occur at the rise and fall, respectively. In order to eliminate the influence of such delay, the second embodiment employs a configuration in which rising and falling of the DQS signal are performed by different paths.

  That is, the data fetch circuit 70 has a DQS variable delay circuit 80 that causes the DQS signal to rise and fall by another path instead of the DQS variable delay circuit 3 used in the first embodiment. doing. Here, two signals of DQSOR and DQSOF are output from the DQS variable delay circuit 80, and DQSOR is output to the flip-flops FF1 to FF8, and DQSOF is output to the flip-flops FF9 to FF16.

  FIG. 7 is a circuit diagram of the DQS variable delay circuit 80. In this DQS variable delay circuit 80, an input signal IN (specifically, DQS) is first divided into two signals and delayed by passing through 1 to 256 stages of delay cells 82A and 82B, respectively. The number of delay cells 82A and 82B through which the input signal IN passes is determined by the state of input of the signals SEL0 to SEL7 to the decode circuit 81, and the delay time can be changed by changing the input state. The delayed signal is output to the flip-flops FF1 to FF16 through the output gates 83A and 83B.

  As described above, according to the second embodiment, only the rising edge of each delay cell is used, and the possibility that the delay difference between the rising edge and the falling edge of the delay cell may have other effects can be eliminated. .

Embodiment 3 FIG.
FIG. 9 is a block diagram of a DDR-SDRAM data fetch circuit according to the third embodiment of the present invention. The data take-in circuit 90 is configured to have an automatic adjustment function of variations between data buses, that is, to adjust the delay amount set by the delay time setting register 5 automatically. Specifically, as can be seen from FIG. 9, the CPU 110 sequentially detects the outputs from the flip-flops FF1 to FF16, and based on this output, the adjustment signal is sent to the register control circuit 100 via the CPU address bus and the data bus. To send to.

FIG. 10 is a block diagram showing a detailed configuration of the delay time setting register 5 and the register control circuit 100 for setting a delay amount in the DQS variable delay circuit 3 and the DQ0 to DQ7 variable delay circuits 4. The write control circuit 101 on the register control circuit 100 side selects the delay register 52 on the delay time setting register 5 side according to the value supplied from the CPU address bus, and sends the write signal WCKDQX to the selected delay register 52 according to the WR signal. Output. Each delay register 52 sets each delay amount of DQ0 to DQ7, and outputs it to the DQ0 to DQ7 variable delay circuit 4 as a SEL signal.
On the other hand, the DQS delay amount is output by adding DEGDATA from the DQS delay calculation circuit 2 and the value from the DQS delay register 51. The SEL signal representing the delay amount is a bus signal, and the number of buses, that is, the number of bits changes depending on the number of delay stages. Thus, the delay amount output from each delay register can be rewritten from the CPU 110.

  FIG. 11 shows a timing chart of signals written from the CPU 110 to the delay time setting register 5. DATA is written in the delay time setting register 5 based on the address, WR, and DREGCS sent from the CPU 110 via the CPU data bus. Here, the timing when 12h is written in the DQS delay register 51 and 2h is written in the DQ0 delay setting register 52 is shown. Note that the timings of WR, ADDRESS, and DATA may differ depending on the type of the CPU 110, but FIG. 11 is merely an example showing that the delay registers 51 and 52 can be accessed from the CPU 10.

  The LSI on which the data fetch circuit according to the third embodiment is mounted is connected to the DDR-SDRAM, and a known value can be written to the SDRAM as write data. Since the correctness of the read value can be determined using this, it is possible to change the delay amount of the DQ0-7 variable delay circuit 52 for each bit of the data buses DQ0 to DQ7, and to determine each change. Thereby, the CPU 110 can finally set the center value at which a normal value is obtained in the delay time setting register 5.

  FIG. 12 shows a flowchart of processing for setting a delay amount in the delay registers 51 and 52 by the CPU 110. In this process, first, a known value is written to the SDRAM (S11). Next, 0 (the delay amount is 1) is set in the DQ0 to DQ7 delay registers (S12). Note that the DQS delay register 51 is set to zero. In this case, the value of the DQS variable delay circuit 3 is set based on the delay amount of the DQS signal.

  Subsequently, a value is read from the SDRAM, and data corresponding to the value is stored (S13). Thereafter, it is determined whether or not the number of delay cell stages has been completed (S14). If NO, +1 is added to the set values of DQS0 to DQS7 (S16), the process returns to step S13, and the subsequent processing is repeated.

  On the other hand, if the result of S14 is YES, that is, if the reading up to the final stage of the delay is completed, the previously stored data is compared with the write data so that the center value of the set values coincides with each other. DQ0 to DQ7 are set in the delay register 52 (S15). Thereby, the optimum delay value of each bus is set according to the variation of the data bus.

  Subsequently, 0 is set in the DQS delay register 52 (S17). Thereafter, a value is read from the SDRAM, and data corresponding to the value is stored (S18). Subsequently, it is confirmed whether or not the delay stage has been completed (S19). If the result is NO, the process returns to step S18 and the subsequent processing is repeated.

  On the other hand, if YES, the value of the DQS delay register 51 is changed from 0 to the maximum value, the read data and the write data are compared, and the coincident center value is set in the DQS delay register 51 (S20). . Thus, the process ends.

  As described above, by mounting the data acquisition circuit according to the third embodiment on an LSI, even if the data bus timing is adjusted due to a package change or a printed board change after LSI development, automatic adjustment is performed. Is possible.

  Note that the present invention is not limited to the illustrated embodiments, and it goes without saying that various improvements and design changes are possible without departing from the scope of the present invention.

It is a block diagram which shows the data acquisition circuit from the synchronous memory which concerns on Embodiment 1 of this invention. It is a circuit diagram common to each of the variable delay circuits for data bus signals (DQ) incorporated in the data fetch circuit. It is a circuit diagram of a variable delay circuit for a data strobe signal (DQS) incorporated in the data fetch circuit. It is a block diagram which shows the detailed structure of the delay time setting register | resistor and register control circuit which are incorporated in the said data acquisition circuit. It is a figure which shows the timing chart of the signal input into the delay time setting register | resistor via the signal input into the said register control circuit, and a register control circuit. It is a block diagram of the data acquisition circuit from the synchronous memory which concerns on Embodiment 2 of this invention. FIG. 6 is a circuit diagram of a variable delay circuit for a data strobe signal (DQS) incorporated in the data fetch circuit according to the second embodiment. (A) It is a figure showing the rise and fall delay of the strobe signal by the delay cell of 1 stage. (B) It is a figure showing the rise and fall delay of the strobe signal by the delay cell of 100 stages. It is a block diagram of the data acquisition circuit from the synchronous memory which concerns on Embodiment 3 of this invention. It is a block diagram which shows the detailed structure of the delay time setting register | resistor and register control circuit which are incorporated in the data acquisition circuit based on the said Embodiment 3. FIG. 4 is a timing chart of signals written from a CPU to a delay time setting register. It is a flowchart of the process which sets the delay amount in a delay register by CPU. (A) is a timing chart showing a state in which the above-described variation occurs between data bus signals. (B) It is a timing chart showing the state where the variation between data bus signals increased.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 DLL circuit, 2 DQS delay calculation circuit, 3 DQS variable delay circuit, 4 DQ0-DQ7 variable delay circuit, 5 Delay time setting register, 6 Register control circuit, 31, 41 Decode circuit, 32, 42 Delay cell, 33, 34 Output gate, 61 serial-parallel conversion circuit, 62 write control circuit, 51 DQS delay register, 52 DQ0 to DQ7 delay register, 53 addition circuit, FF1 to FF16 flip-flop.

Claims (2)

In the data acquisition circuit that captures the data bus signal (DQ) from the synchronous memory at the rising and falling edges of the data strobe signal (DQS),
A variable delay circuit for delaying the data bus signal by a predetermined delay time;
And a delay time setting circuit for setting the delay time used in the variable delay circuit to be adjustable. 2. The data fetching circuit from the synchronous memory according to claim 1, further comprising means for automatically controlling an output signal from the delay time setting circuit to the variable delay circuit.

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