JP2005051178A - Semiconductor device and method for manufacturing the semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a plurality of transistors different in film thickness and type on the same substrate. <P>SOLUTION: An underlayer substrate is isolated into first, second and third regions for forming first, second and third transistors, respectively, to form a first insulating film in the first to third regions. Thereafter, the first insulating film in the second and third regions is selectively removed. Next, a high dielectric constant film is formed on the entire substrate, to remove the high dielectric constant film formed in the first and second regions. Gate electrodes are formed on the first to third regions, respectively. In this manner, a semiconductor device provided with the first to third transistors on one substrate is formed. In this semiconductor device, a gate insulating film of the first transistor is thicker than that of the second transistor. Further, the gate insulating film of the third transistor is composed of the material identical to that of the second transistor, and also is constructed of a laminated film containing an interface gate insulating film of an identical film thickness and the high dielectric constant film having a higher dielectric constant than the interface gate insulating film. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. More specifically, the present invention relates to a semiconductor device including a plurality of transistors having different types of gate insulating films and different film thicknesses in one semiconductor device, and a manufacturing method thereof.

  In recent years, with the progress of miniaturization technology of semiconductor integrated circuits, the dimensions of elements have been reduced, and it is possible to integrate 10 million or more transistors in one chip. As a result, functions that have been conventionally realized by using a plurality of semiconductor devices can be realized by a single semiconductor device. Thus, a semiconductor device having various functions in one device is called SoC (System on Chip) and has been widely used in recent years.

  As described above, in the SoC that realizes a plurality of functions, the input / output circuit section needs to be directly connected to an external voltage and directly driven by this voltage. Therefore, high voltage resistance is required for a MISFET (Metal Insulator Semiconductor Field Effect Transistor) used in the input / output circuit section. For this reason, in the MISFET of the input / output circuit portion, a gate insulating film that is thick to some extent is required. Specifically, for example, in a 3.3V input / output circuit MISFET, a thick gate insulating film of about 6.0 nm to 10 nm is used.

  On the other hand, in the logic circuit portion, the drive voltage is lowered in order to reduce power consumption. At the same time, the gate insulating film of the MISFET used in the logic circuit portion is being made thinner in order to prevent a decrease in the drive current due to a lower drive voltage.

  The MISFET used in the SoC logic circuit section includes a low power consumption version (LOP) that requires a relatively high speed operation and a low standby power version (LSTP) that has a low standby power. by Power). According to ITRS (The International Technology Roadmap for Semiconductor), the EOT (silicon oxide equivalent film thickness) of the gate insulating film of the MISFET for LOP is 1.0 nm to 1.4 nm in the 65 nm technology generation. The target value of the EOT of the gate insulating film of the LSTP MISFET is recommended to be 1.2 nm to 1.6 nm. On the other hand, the allowable leakage current of the gate insulating film of the LOP MISFET is 700 pA when the EOT has the largest value, and the allowable leakage current of the gate insulating film of the MISTP MISFET is 1 pA as the target value. .

Conventionally, a SiO ₂ film has been frequently used as the gate insulating film. However, when the film thickness of the SiO ₂ film is 2 nm or less, the problem of leakage current cannot be ignored. For this reason, in a 65 nm technology generation MISFET for LOP and LSTP that requires a film thickness of 2 nm or less, a single SiO ₂ film cannot be used as a gate insulating film. On the other hand, when the SiON film is a gate insulating film, the target value of the allowable leakage current in the LOP MISFET can be achieved if a film thickness of about 1 nm can be secured.

  However, in the LSTP MISFET, when the SiON film is used as the gate insulating film, the target value of 1 pA of the allowable leak current cannot be achieved at the same time when the EOT is set to the target value of about 1.2 nm to 1.6 nm. . Therefore, it is possible to suppress the increase in power consumption by making the physical film thickness thicker and preventing the tunnel current, while reducing the effective film thickness to determine the transistor current sufficiently. It is essential to use a film (see, for example, Patent Document 1).

  Incidentally, the EOT of the gate insulating film is the sum of the EOTs of the respective films when the gate insulating film is formed of a laminated film. That is, in the case of using a laminated film of the interface gate insulating film and the high dielectric constant film, the sum of the EOT of the interface gate insulating film and the EOT of the high dielectric constant film becomes the EOT of the entire gate insulating film. Here, when a high dielectric constant film is used as the gate insulating film, the interface gate insulating film is an essential film for manufacturing. For example, when a high dielectric constant film having a relative dielectric constant k = 20 and a film thickness of 3 nm is used to prevent leakage current, the EOT of this high dielectric constant film is 0.6 nm. Therefore, for example, in order to achieve EOT of the 65 nm technology generation as described above, the EOT of the interface gate insulating film is 0.4 to 0.8 nm, 0.00 mm in the MISFET for LOP and MISFET for LSTP, respectively. It is necessary to be 6 to 1.0 nm.

  However, it is technically difficult to form the interface gate insulating film with an EOT of 1 nm or less. Further, as described above, even when an interface gate insulating film having a thickness of 1 nm or less is formed, a high dielectric constant film needs to be laminated on the interface gate insulating film having a thickness of 1 nm or less to prevent leakage current. However, when a gate insulating film having a laminated structure of an interfacial gate insulating film of 1 nm or less and a high dielectric constant film is used, the effective mobility of the transistor is the effective mobility of the transistor using a single-layered silicon oxynitride gate insulating film. This is a problem because it becomes very small compared to the degree.

Further, it has been found that in a gate insulating film having a structure in which a high dielectric constant film of 3 nm is deposited on a 6 nm thick SiO ₂ film, the leakage current is locally large (for example, see Non-Patent Document 1). ).

JP 2002-110812 A 49th Applied Physics Related Conference Lecture Proceedings 820 pages 28P-A-10

  Therefore, the present invention solves the above problems, and forms transistors having gate insulating films having different film types and film thicknesses in accordance with required functions in one semiconductor device. An object of the present invention is to provide an improved semiconductor device and a method for manufacturing the same that suppress the leak current according to the allowable leak current and further suppress the decrease in effective mobility.

A semiconductor device according to the present invention includes a first transistor including a first gate insulating film and a first gate electrode;
A second transistor including a second gate insulating film and a second gate electrode;
With
The first gate insulating film comprises a first insulating film,
The second gate insulating film includes an interface gate insulating film having a smaller thickness than the first insulating film and a high dielectric constant film having a dielectric constant higher than that of the interface gate insulating film.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: separating a lower layer substrate into first and second regions for forming a first transistor and a second transistor;
A first insulating film forming step of forming a first insulating film in the first and second regions;
A first insulating film removing step for selectively removing the first insulating film formed in the second region;
A high dielectric constant film forming step of forming a high dielectric constant film on the entire substrate;
A high dielectric constant film removing step of removing the high dielectric constant film formed in the first region;
A gate electrode forming step of forming a gate electrode in each of the first and second regions;
Is provided.

  According to the present invention, in one semiconductor device, a transistor having a thick insulating film as a gate insulating film, a transistor having a thin insulating film as a gate insulating film, a thin insulating film, Then, a transistor having a gate insulating film made of a laminated film with a high dielectric constant film laminated thereon is formed. Therefore, each transistor formed in this semiconductor device can achieve the target value of the allowable leakage current while ensuring the necessary EOT according to the application.

  Further, according to the present invention, after forming a thick insulating film, the insulating film is selectively removed in a certain region, and a high dielectric constant film is formed in the removed portion. Further, a part of the high dielectric constant film is removed. As a result, three types of transistors, each having a thick insulating film, a thin insulating film, and a laminated film of a thin insulating film and a high dielectric constant film as gate insulating films, are formed in the semiconductor device. Can be formed. Therefore, the transistors can be easily formed according to the application, and each transistor can achieve the necessary EOT and the target value of the allowable leakage current.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof is simplified or omitted.

Embodiment.
FIG. 1 is a schematic cross-sectional view for explaining SoC 100 in the embodiment of the present invention.
As shown in FIG. 1, the SoC 100 has a field effect transistor (MISFET; Metal Insulator Semiconductor Field Effect Transistor) 110 (hereinafter referred to as an input / output MISFET 110) and an LSTP (low power) on an Si substrate 2. MISFET 120 for standby voltage (Low Stand-by Power) (hereinafter referred to as MISFET 120 for LSTP) and field effect transistor (MISFET) 130 for LOP (Low Operating Power) (Hereinafter referred to as LOP MISFET 130).

The input / output, LOP, and LSTP MISFETs 110, 120, and 130 are formed in respective regions of the P-type Si substrate 2 separated by an element isolation region (STI; Shallow Trench Isolation) 4.
In each region isolated by the element isolation region 4, a diffusion layer 6 into which an n-type impurity is implanted is formed in the Si substrate 2.

In the input / output MISFET 110, an SiO ₂ film (thermal oxide film) 10 having a nitrided surface is formed as a gate insulating film on the channel region sandwiched between the diffusion layers 6 of the Si substrate 2. The thickness of the SiO ₂ film 10 is about 7.0 nm. In each of the LSTP MISFET 120 and the LOP MISFET 130, the SiON film 12 is formed on the channel region. The EOT (silicon oxide film equivalent film thickness) of the SiON film 12 is about 1.0 nm. In the LSTP MISFET 120, an HfO ₂ film 14 is formed on the SiON film 12 and a SiN film 16 is formed on the HfO ₂ film 14 as a gate insulating film. That is, in the LSTP MISFET 120, the gate insulating film is a laminate of the SiON film 12 serving as an interface gate insulating film, the HfO ₂ film 14 that is a high dielectric constant film, and the SiN film 16 that is an upper gate insulating film. It has a structure. Here, the HfO ₂ film is about 2.0 nm, the EOT is about 0.4 nm, and the EOT of the SiON film 16 is about 0.2 nm. The gate insulating film of the LOP MISFET 130 is composed of a single layer of SiON film 12.

  In each of the input / output, LSTP, and LOP MISFETs 110, 120, and 130, a gate electrode 20 is formed on each gate insulating film. A sidewall 22 is formed on the side wall of the gate electrode 20. Further, the surface of each gate electrode 20 and the portion of the surface of the diffusion layer 6 of the Si substrate 2 where the gate electrode 20 and the sidewalls 22 are not formed are silicided, and a CoSi layer 24 is formed on each of them. Yes.

  Further, an interlayer insulating film 30 is formed on the Si substrate 2 so as to embed each gate insulating film, the gate electrode 20 and the sidewalls 22. In the interlayer insulating film 30, contact plugs 32 reaching from the surface to the CoSi layers 24 on the surface of the diffusion layer 6 are formed, and metal wirings 34 are formed on the contact plugs 32.

In the SoC 100 configured as described above, the gate insulating film of the input / output MISFET 110 is configured by the SiO ₂ film 10 having a thickness of about 7.0 nm. As a result, the input / output MISFET 110 has high durability against high voltage such as a voltage directly input from the outside. In the LSTP MISFET 120, the gate insulating film has a laminated structure of the SiON film 12, the HfO ₂ film 14, and the SiN film 16. The EOT of each film is about 1.0 nm, about 0.4 nm, and about 0.2 nm, respectively, and the entire gate insulating film is relatively thin, about 1.6 nm. Further, by using the HfO ₂ film 14 which is a high dielectric constant film as a gate insulating film, the leakage current is suppressed to 1 pA or less. The gate insulating film of the MISFET 130 for LOP is composed of the SiON film 12 having an EOT of about 1.0 nm. Thereby, a transistor with low power consumption is realized. In addition, by using the SiON film, the leak current cannot be suppressed to 700 pA or less, which is the target value of the 65 nm technology generation at EOT = 1.4 nm, but it is the target value of the leak current for high-speed applications among LOPs. It can be suppressed to 10 nA or less.

FIG. 2 is a flowchart for explaining a method of manufacturing SoC 100 in the embodiment of the present invention. 3 to 5 are schematic cross-sectional views for explaining the states of the SoC 100 in each manufacturing process.
Hereinafter, the manufacturing method of SoC100 in embodiment of this invention is demonstrated in detail using FIGS.

  First, as shown in FIG. 3, the element isolation region 4 is formed on the Si substrate 2 (step S2), and the Si substrate 2 is formed in regions where the input / output MISFET 110, the LSTP MISFET 120, and the LOP MISFET 130 are formed, respectively. To separate. Hereinafter, for the sake of simplification, the regions forming the input / output MISFET 110, the LSTP MISFET 120, and the LOP MISFET 130 are referred to as an input / output region, an LSTP region, and an LOP region, respectively. Further, the entire substrate including the entire region and including the Si substrate 2 and each film already laminated on the Si substrate 2 at that time is referred to as a substrate.

As shown in FIG. 3, the SiO ₂ film 40 is formed in each region on the Si substrate 2 (step S4). Here, the SiO ₂ film 40 is formed by thermal oxidation. The SiO ₂ film 40 is a film that will later become the SiO ₂ film 10 that is the gate insulating film of the input / output MISFET 110. The film thickness at this stage is about 6.9 nm, and at this stage, It is also formed in the LSTP and LOP areas.

Next, as shown in FIG. 4, a resist mask 42 covering the input / output region is formed by a lithography technique (step S6). Thereafter, the SiO ₂ film 40 in the LSTP region and the LOP region is removed using the resist mask 42 as a mask (step S8).

Next, the resist mask 42 is removed (step S10). Thereafter, as shown in FIG. 5, the SiON film 12 is formed in the LSTP region and the LOP region (step S12). The SiON film 12 is a film serving as an interface gate insulating film in the LSTP MISFET 120 and is a film serving as a gate insulating film in the LOP MISFET 130. The SiON film 12 is formed by plasma-excited thermal oxynitridation so that the film thickness becomes about 1.0 nm. At the same time, the thickness of the SiO ₂ film 40 in the input / output region is also increased, and the SiO ₂ film 10 having an EOT of about 7.0 nm is obtained.

Next, as shown in FIG. 6, the HfO ₂ film 14 is formed on the entire surface of the substrate (step S14). Here, the film is formed using a CVD (Chemical Vapor Deposition) method so that the film thickness becomes about 2.0 nm. At this time, the EOT of the HfO ₂ film 14 is about 0.4 nm. The HfO ₂ film 14 formed here is a film to be a high dielectric constant film in the gate insulating film of the LSTP MISFET 120. Thereafter, heat treatment is performed at about 1000 ° C. in a nitrogen atmosphere containing a small amount of oxygen (step S16).

Next, the SiN film 16 is formed on the HfO ₂ film 14 (step S18). Here, the SiN film 16 is formed using the CVD method so that the film thickness is about 0.4 nm. The EOT of the SiN film 16 is about 0.2 nm. The SiN film 16 formed here is a material film that becomes an upper gate film in the gate insulating film of the LSTP MISFET 120.

Next, as shown in FIG. 7, a resist mask 44 that covers the LSTP region is formed by lithography (step S20). Thereafter, using the resist mask 44 as a mask, the SiN film 16 and a part of the HfO ₂ film 14 in the input / output region and the LOP region are removed by dry etching (step S22).

Next, as shown in FIG. 8, the resist mask 44 is removed (step S24). Further, the HfO ₂ film 14 remaining in the input / output region and the LOP region is selectively removed by wet etching (step S26). Here, the previously formed SiN film 16 is a necessary part of the HfO ₂ film in the lithography process for forming the resist mask 44, particularly in the development process or the process of removing the resist mask 44. 14 serves to suppress simultaneous etching.

Next, as shown in FIG. 9, a polysilicon film 46 is formed on the entire surface of the substrate (step S28), and a 20 nm thick SiO ₂ film 48 is formed on the polysilicon film 46 by CVD. (Step S30). The polysilicon film 46 is a material film that becomes the gate electrode 20 by subsequent processing.

Next, as shown in FIG. 10, a resist mask 50 is formed on the portion of the SiO ₂ film 48 where the gate electrode 20 is to be formed (step S32). Thereafter, using the resist mask 50 as a mask, anisotropic etching is first performed on the SiO ₂ film 48 by dry etching (step S34).

Next, as shown in FIG. 11, the resist mass 50 is removed (step S36), and the polysilicon film 46 and the HfO ₂ film 14 are anisotropically etched using the SiO ₂ film 48 as a mask (step S38). Thereby, the gate electrode 20 is formed in each region.

  Next, arsenic ions are implanted into the surface of the Si substrate 2 by ion implantation (step S40). Here, a shallow n-type diffusion layer is formed on the surface of the p-type Si substrate 2 using the gate electrode 20 as a mask.

Next, as shown in FIG. 12, sidewalls 22 are formed on the side surfaces of the gate electrode 20 (step S42). Here, first, after depositing a laminated film of a silicon oxide film and a silicon nitride film, anisotropic etch back is performed. As a result, the silicon oxide film and the silicon nitride film remain only on the side surface of the gate electrode 20 and the sidewalls 22 are formed. In addition, at the time of this etch back, the SiO ₂ film 10 in the input / output region and the SiON film 12 in the LSTP region and the LOP region are etched back at the same time, so that the surface of the SiO ₂ film 10 and the SiON film 12 is formed. The exposed part is removed.

  Again, arsenic ions are implanted into the surface of the Si substrate 2 by ion implantation (step S44). Here, the gate electrode 20 and the sidewall 22 serve as a mask, and a portion having a relatively high impurity concentration in the diffusion layer 6 is formed in the portion where the surface of the Si substrate 2 is exposed. Thereafter, heat treatment is performed (step S46). Thereby, arsenic implanted into the Si substrate 2 is activated, and a diffusion layer 6 is formed in each region. Next, the CoSi layer 24 is formed in a self-aligned manner on the surface of the gate electrode 20 and the portion exposed on the surface of the Si substrate 2 (step S48).

  Thereafter, an interlayer insulating film 30 is formed on the Si substrate 2 so as to embed each gate insulating film, the gate electrode 20 and the sidewalls 22 by a normal process. Further, the interlayer insulating film 30 is coated with CoSi from the surface. A contact plug 32 reaching the layer 24 is formed. Further, a metal wiring 34 made of copper or the like is formed on the contact plug 32. Such a process is repeated to form a multilayer wiring, thereby forming a semiconductor device.

As described above, according to this embodiment, the MISFETs 110, 120, and 130 having different film thicknesses and film types are formed on the same substrate. Specifically, the input / output MISFET 110 is formed with a gate insulating film made of a single layer of SiO ₂ film 10 having a film thickness of about 6.5 nm. Therefore, the MISFET 110 can be used in a portion where durability against a relatively high voltage is required in the SoC 100, such as when it is necessary to directly connect to the outside. The gate insulating film of the LSTP MISFET 120 is composed of a laminated film of a SiON film 12 with an EOT of about 1.0 nm, a HfO ₂ film 14 with an EOT of about 0.4 nm, and a SiN film 16 with an EOT of about 0.2 nm. ing. In this gate insulating film, by using the HfO ₂ film 14 which is a high dielectric constant film, the actual film thickness is formed thick to prevent the tunnel current, and the effective film thickness for determining the transistor current is sufficient. To keep power consumption from increasing. Accordingly, the LSTP MISFET 120 can be used in the SoC 100 where the standby power needs to be lowered. The gate insulating film of the LOP MISFET 130 is composed of the SiON film 12 having an EOT of about 1 nm. Therefore, the MISFET 130 can be used in a portion where higher speed operation is required while suppressing a certain amount of leakage current. As described above, according to the SoC 100 of this embodiment, gate insulating films having different film thicknesses and film types can be realized according to various functions.

Further, according to the SoC of this embodiment, in the MISFET 110 for input / output, the gate insulating film is a single layer of SiO ₂ film and is thick and does not have a laminated structure with the HfO ₂ film. Therefore, it is possible to avoid the problem of a leak current that locally increases when a high dielectric constant film is laminated on the SiO ₂ film.

The LOP MISFET 130 is also a single gate insulating film of the SiON film 12 and does not have a laminated structure with the HfO ₂ film. Therefore, it is possible to avoid a decrease in effective mobility due to the laminated structure while securing a thin EOT so as to cope with higher speed operation. Further, the allowable values of EOT and leakage current required for the 65 nm technology generation LOP MISFET 130 can be cleared.

In the LSTP MISFET 120, a gate insulating film in which an HfO ₂ film is stacked on the SiON film 12 is used. As a result, although the film thickness is thicker than that of the LOP MISFET 130, the leak current can be suppressed to a small level at a high level while reducing the EOT to some extent and reducing the current consumption. Further, the allowable values of EOT and leakage current required for the LSTP MISFET 120 of the 65 nm technology generation can be cleared.

Further, according to this embodiment, after the SiO ₂ film is first formed and removed selectively, the SiON film 12 is formed, and the HfO ₂ film and the SiN film are formed. Alternatively, it is formed by removing the HfO ₂ film and the SiN film. Therefore, a complicated process is not required, and transistors having different film thicknesses and film types can be easily formed over the same substrate, so that the productivity of the semiconductor device can be improved.

  In this embodiment, the case where the input / output MISFET 110, the LSTP MISFET 120, and the LOP MISFET 130 are provided on one substrate has been described. However, in the present invention, each transistor is not limited to input / output, LSTP, and LOP. These may be used for other purposes as long as they are used for appropriate purposes according to the film type and film thickness of the gate insulating film.

  Further, in this embodiment, the case where the input / output, LSTP, and LOP MISFETs 110, 120, and 130 are formed one by one on one substrate has been described for convenience. However, the present invention is not limited to one in which each transistor is formed, and may be any one that forms a necessary number of transistors as required.

In this embodiment, the thick insulating film in the input / output MISFET 110 is the SiO ₂ film 10, the thin interface gate insulating film in the LSTP MISFET 120 and the thin gate insulating film in the LOP MISFET 130 are the SiON film 12. . Further, the SiN film 16 was used as the upper gate insulating film in the LSTP MISFET 120. However, in the present invention, the material of the gate insulating film is not limited to this. The material of these gate insulating films can be selected from, for example, a SiO ₂ (silicon oxide film) film, a SiN (silicon nitride film) film, a SiON (silicon oxynitride film) film, and the like. Further, for example, any _two of SiO ₂ film, SiN film, and SiON film, or a laminated structure in which all of these films are laminated may be used.

In the embodiment, the case where the SiON film 12 is formed in each of the LSTP region and the LOP region after the SiO ₂ film 40 is removed has been described. However, the present invention is not limited to this. For example, the natural oxide film formed on the Si substrate 2 may be used as it is without forming the SiON film 12.

In this embodiment, the case where the SiN film 16 is formed as the upper gate insulating film on the HfO ₂ film 14 has been described. However, the present invention is not limited to this, and the gate electrode 20 may be formed directly on the HfO ₂ film 14 without forming the upper gate insulating film.

In this embodiment, the case where the HfO ₂ film 14 is used as the high dielectric constant film has been described. However, in the present invention, the high dielectric constant film is not limited to the HfO ₂ film. The high dielectric constant film may be any film having a higher dielectric constant than the gate insulating film for input / output and LOP, such as a SiO ₂ film, a SiN film, and a SiON film. For example, as other high dielectric constant films, Hf _x Al _1-x O _y (hafnium aluminate) film, Al ₂ O ₃ (alumina) film, La ₂ O ₂ (lanthanum oxide), Pr ₂ O ₃ (praseodium oxide) ), Y ₂ O ₃ (yttrium oxide), Ta ₂ O ₅ (tantalum oxide), Nb ₂ O ₅ (niobium oxide), TiO ₂ (titanium oxide), CeO ₂ (cerium oxide), and other metal oxides, Further, a solid solution thereof, a solid solution of these metal oxides and SiO ₂ , or titanic acid such as (BaSr) TiO ₃ (strontium barium titanate) can be used.

  In the present invention, the method of forming each film is not limited to the method described in this embodiment. Any of these forming methods may be used as long as it is formed by an appropriate method in consideration of the material of the film.

In the present invention, the film thickness or EOT of each film is not limited to the film thickness described in this embodiment. These may have appropriate film thicknesses in consideration of required transistor functions, film materials to be used, and the like.
For example, the input / output circuit unit corresponds to 3.3V. However, the present invention is not limited to this, and may be, for example, one corresponding to 2.5V or 1.8V. In this case, each EOT is about 5.0 nm and 3.0 nm.

For example, in this embodiment, the input / output MISFET 110, the LSTP MISFET 120, and the LOP MISFET 130 correspond to the first, second, and third transistors of the present invention, respectively. Each gate insulating film and each gate electrode 20 correspond to the first, second, and third gate insulating films and the first, second, and third gate electrodes, respectively. Further, for example, the SiO ₂ film 10 which is the gate insulating film of the input / output MISFET in this embodiment corresponds to the first insulating film of the present invention, and the SiON film 12 which is the gate insulating film of the LOP MISFET 130 is This corresponds to the third insulating film of the present invention. For example, the SiON film 12 of the LSTP MISFET 120 corresponds to the interface gate insulating film of the present invention, the HfO ₂ film 14 corresponds to the high dielectric constant film, and the SiN film 16 corresponds to the upper gate insulating film. .

  In addition, for example, in this embodiment, by performing steps S2 and S4, the separation process and the first insulating film forming process of the present invention are respectively performed, and by performing steps S6 to S10, the first process is performed. 1 is performed. Further, for example, by executing steps S12, S14, and S18, the second insulating film forming step, the high dielectric constant film forming step, and the upper gate insulating film forming step of the present invention are executed, respectively. Further, for example, in this embodiment, the high dielectric constant film removing process of the present invention is executed by executing steps S20 to S26, and the gate electrode forming process is executed by executing steps S32 to S38. The

It is a cross-sectional schematic diagram for demonstrating the structure of SoC100 in embodiment of this invention. It is a flowchart for demonstrating the manufacturing method of SoC in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of SoC100 in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of SoC100 in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of SoC100 in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of SoC100 in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of SoC100 in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of SoC100 in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of SoC100 in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of SoC100 in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of SoC100 in embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of SoC100 in embodiment of this invention.

Explanation of symbols

100 SoC
110 MISFET for input / output
120 LSTP MISFET
130 MISFET for LOP
2 Si substrate 4 Element isolation region 6 Diffusion layer 10 SiO ₂ film 12 SiON film 14 HfO ₂ film 16 SiN film 20 Gate insulating film 22 Side wall 24 CoSi layer 30 Interlayer insulating film 32 Contact plug 34 Metal wiring 40 SiO ₂ film 42 Resist Mask 44 Resist mask 46 Polysilicon film 48 SiO ₂ film 50 Resist mask

Claims (13)

A first transistor including a first gate insulating film and a first gate electrode;
A second transistor including a second gate insulating film and a second gate electrode;
With
The first gate insulating film comprises a first insulating film,
The second gate insulating film includes an interface gate insulating film having a smaller thickness than the first insulating film, and a high dielectric constant film having a dielectric constant higher than that of the interface gate insulating film. apparatus.   The semiconductor device according to claim 1, wherein the second gate insulating film further includes an upper gate insulating film on the high dielectric constant film. The interface gate insulating film has a silicon oxide equivalent film thickness of about 1.0 nm,
3. The semiconductor device according to claim 1, wherein the high dielectric constant gate insulating film has an equivalent oxide equivalent film thickness of about 0.6 nm.   The semiconductor device according to claim 1, wherein the first insulating film has an equivalent oxide equivalent film thickness of about 3.0 to 7.0 nm.   The interface gate insulating film is a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a stacked film of a silicon oxide film and a silicon nitride film, a stacked film of a silicon oxide film and a silicon oxynitride film, or a silicon nitride film 5. The semiconductor device according to claim 1, wherein the semiconductor device is a laminated film of silicon oxynitride film.   The first insulating film is a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a stacked film of a silicon oxide film and a silicon nitride film, a stacked film of a silicon oxide film and a silicon oxynitride film, or silicon nitride 6. The semiconductor device according to claim 1, wherein the semiconductor device is a laminated film of a film and a silicon oxynitride film. The semiconductor device further includes a third transistor including a third gate insulating film and a third gate electrode,
The semiconductor device according to claim 1, wherein the third gate insulating film has the same material and the same thickness as the interface gate insulating film. A separation step of separating the lower layer substrate into first and second regions for forming a first transistor and a second transistor, respectively;
A first insulating film forming step of forming a first insulating film in the first and second regions;
A first insulating film removing step for selectively removing the first insulating film formed in the second region;
A high dielectric constant film forming step of forming a high dielectric constant film on the entire substrate;
A high dielectric constant film removing step of removing the high dielectric constant film formed in the first region;
A gate electrode forming step of forming a gate electrode in each of the first and second regions;
A method for manufacturing a semiconductor device, comprising: A separation step of separating the lower substrate into first, second, and third regions for forming a first transistor, a second transistor, and a third transistor, respectively;
A first insulating film forming step of forming a first insulating film in the first, second, and third regions;
A first insulating film removing step for selectively removing the first insulating film formed in the second and third regions;
A high dielectric constant film forming step of forming a high dielectric constant film on the entire substrate;
A high dielectric constant film removing step of removing the high dielectric constant film formed in the first and third regions;
A gate electrode forming step of forming a gate electrode in each of the first, second, and third regions;
A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 8, wherein the first insulating film forming step is performed by thermal oxidation.   After the first insulating film removing step and before the high dielectric constant film forming step, a second insulating film that is thinner than the first insulating film is formed in the second and / or third region. The method for manufacturing a semiconductor device according to claim 8, further comprising two insulating film forming steps.   The method for manufacturing a semiconductor device according to claim 11, wherein the second insulating film is formed by plasma-excited thermal oxynitridation.   13. The semiconductor according to claim 8, further comprising an upper gate insulating film forming step of forming an upper gate insulating film on the high dielectric constant film after the high dielectric constant film forming step. Device manufacturing method.

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