JP2005045443A - Image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To more exactly decide the movement of a picture to generate a good interpolating signal. <P>SOLUTION: The image processor for converting an interlaced picture signal into a progressive picture signal comprises a vertical difference detecting means for selecting and outputting either the difference between adjacent lines in a first field, or the difference between adjacent lines in a second field, based on the time change quantity and the special change quantity of the picture signals in the first field and the second field just before it; including interpolating signals, a means for detecting the movement of the input picture signals between continuous two fields, using the output of the vertical difference detecting means; and a means for generating the interpolating signals, based on the output of the movement detecting means. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image processing apparatus, and more particularly to an interpolation process of an image signal.
[0002]
[Prior art]
Currently, a general video signal system such as NTSC handles interlaced scanning image signals.
[0003]
In an interlaced image signal, there are interferences such as flicker occurring at very fine horizontal stripes. In order to improve this problem, a technique for interpolating interlaced scanning lines and outputting them as progressive scanning image signals is known.
[0004]
There is also known a technique for determining an image motion when converting to progressive scanning, and generating an interpolation signal by synthesizing a previous field signal and a current field according to the motion determination result. In this method, the state of the interpolation signal changes depending on the accuracy of the motion determination result.
[0005]
For example, if a still part is interpolated with an image signal in the current field, fine horizontal stripes disappear and flicker occurs. In addition, if interpolation is performed on the moving portion with the image signal of the previous field, motion blur occurs and the edges become jagged.
[0006]
A technique for increasing the accuracy of the motion determination result is described in Patent Document 1. In Patent Document 1, the maximum value of the inter-line difference signal of the previous field or the rear field and the maximum value of the inter-line difference signal of the current field is used as a vertical edge signal, and motion determination is performed using this vertical edge signal.
[0007]
[Patent Document 1]
Japanese Patent Laid-Open No. 7-131678
[Problems to be solved by the invention]
However, only by comparing the magnitude relationship between the differential signal between lines in the previous field and the differential signal between lines in the current field, even in a moving area that is an edge in the previous field but not an edge in the current field, the previous field The inter-line difference signal is used for motion determination, and the motion determination result becomes closer to static, interpolation is performed with the value of the previous field, and motion blur occurs.
[0009]
In other words, in the moving area, the inter-line difference value in the previous field becomes a value completely unrelated to the inter-line difference value that is originally necessary for the motion determination, which may cause an erroneous determination.
[0010]
The present invention solves the above-described problems, makes it possible to more accurately determine the motion of an image and generate a good interpolation signal.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, in the present invention, an interpolated signal is generated using an input interlaced scan image signal, and converted to a progressive scan image signal using the interpolated signal. Based on the temporal change amount and the spatial change amount of the image signal in the first field including the interpolated image signal and the second field immediately before the first field, the difference between adjacent lines in the first field and the second field Vertical difference detection means for selecting and outputting one of the differences between adjacent lines in the field, and detecting movement between two consecutive fields in the input image signal using the output of the vertical difference detection means An image processing apparatus is provided that includes a motion detection unit that performs the operation, and an interpolation signal generation unit that generates the interpolation signal based on the output of the motion detection unit. That.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0013]
FIG. 1 is a block diagram showing the configuration of a recording apparatus to which the present invention is applied.
[0014]
In FIG. 1, the subject image input through the lens 101 is converted into an image signal by the CCD 102, converted into a digital signal by the A / D 103, and then output to the camera signal processing circuit 104. The camera signal processing circuit 104 performs image processing signal processing such as aperture correction, gamma correction, and white balance, and outputs the result to the conversion circuit 105. The conversion circuit 105 converts the interlaced scanning image signal output from the camera signal processing circuit 104 into a progressive scanning image signal and outputs the progressive scanning image signal to the encoding circuit 106. The encoding circuit 106 encodes the image signal by a known encoding method such as MPEG and outputs it to the recording circuit 107. The recording circuit 107 records the encoded image signal on the recording medium 108.
[0015]
Next, the conversion circuit 105 which is a characteristic configuration of this embodiment will be described.
[0016]
FIG. 2 is a block diagram showing the configuration of the conversion circuit 105.
[0017]
In FIG. 2, interlaced scanning moving image signals from the camera signal processing circuit 104 are sequentially input. The line memory 201 outputs the input signal with a delay of one line. The field memory 202 accumulates the input image signal for one field, and outputs the input signal for interlace scanning with a delay of one field period.
[0018]
The output signal of the line memory 201 is supplied to the average value circuit 203 in the inter-field difference detection circuit, the subtracter 215 in the vertical edge detection circuit, and the average value circuit 218, and the output signal of the field memory 202 is subtracted in the inter-field difference detection circuit. Destination 204, the line memory 207 in the vertical edge detection circuit, the subtractor 211, the frequency analysis circuit 217, and the progressive conversion circuit 219.
[0019]
In the vertical edge detection circuit, the output signal from the field memory 202 is delayed by one line period by the line memories 207 and 208, respectively.
[0020]
FIG. 3 shows the relationship between the signals described above.
[0021]
3a is an output signal from the line memory 208, b is an output signal from the line memory 207, c is an output signal from the field memory 202, d is an output signal from the line memory 201, e is an input signal for interlaced scanning, and x is an input signal for interlace scanning. An interpolation line in the current field is shown.
[0022]
First, the operation of the inter-field difference detection circuit will be described.
[0023]
An output signal from the line memory 201 and an input signal for interlace scanning are supplied to the average value circuit 203. The average value circuit 203 calculates and outputs the average value of these two signals. The output signal of the average value circuit 203 indicates the average value of the upper and lower interpolation lines in the current field, and is the average value of the signal d and the signal e in FIG. A difference between the output signal of the average value circuit 203 and the output signal of the field memory 202 is obtained by a subtractor 204 and converted into an absolute value by an absolute value circuit 205. The output signal of the absolute value circuit 205 becomes a difference value between fields.
[0024]
Next, the operation of the vertical edge detection circuit will be described.
[0025]
The difference between the output signal of the line memory 201 and the input signal for interlaced scanning is obtained by the subtractor 215 and converted into an absolute value by the absolute value circuit 216. The output signal of the absolute value circuit 216 indicates the difference between the lines in the current field, and is the absolute value of the difference between the signals d and e in FIG.
[0026]
On the other hand, the output signals of the field memory 202 are delayed by one line period by the line memories 207 and 208, respectively. Therefore, the output signal of the line memory 208 is delayed by two lines with respect to the output signal of the field memory 202, and the line memories 207 and 208 cause the three continuous lines of signals a, b, and c in FIG. A signal is obtained.
[0027]
Then, the difference between the output signal of the line memory 207 and the output signal of the field memory 202 is obtained by the subtractor 211 and converted into an absolute value by the absolute value circuit 212. Similarly, the difference between the output signal of the line memory 207 and the output signal of the line memory 208 is obtained by the subtracter 209 and converted into an absolute value by the absolute value circuit 2107. The output signals of the absolute value circuit 210 and the absolute value circuit 212 are the difference between two lines in the previous field, that is, the absolute value of the difference between the signal a and the signal b and the absolute value of the difference between the signal b and the signal c in FIG. Become.
[0028]
The maximum value circuit 213 selects and outputs the larger one of the absolute values of the difference between these two lines. The control circuit 214 selects and outputs one of the output signal from the absolute value circuit 216 and the output signal from the maximum value circuit 213.
[0029]
That is, the control circuit 214 selects the output signal of the absolute value circuit 216 when the output signal of the frequency analysis circuit 217 is 1, and selects the output signal of the maximum value circuit 213 when it is 0.
[0030]
The frequency analysis circuit 217 measures the amount of change around the interpolation line in the current field and the previous field from the input signal of interlace scanning and the output signal of the field memory 202, and the difference between the two values is a predetermined value. If it is larger than the threshold 1, a logic 1 is output as a moving area. When the threshold value is smaller than 1, the amount of change in the current field and the previous field is measured from the upper and lower lines, and the median value is obtained to determine the amount of change in the values around the interpolation line in the current field and the previous field. If the difference between the difference and the median is larger, a logic 1 is output as a moving area, and if it is smaller, a logic 0 is output as a stationary area.
[0031]
As a result, the control circuit 214 outputs the output signal of the absolute value circuit 216 which is the detection result of the vertical edge of the current field in the moving area, and the edge signal of the current field and the edge of the previous field in the stationary area. The maximum value of the signal, that is, the larger one of the output signal of the absolute value circuit 212 and the output signal of the maximum value circuit 210 is selected. By this processing, it is possible to prevent the occurrence of motion blur by using the value of the vertical edge of the previous field in the moving area, and to detect a thin edge as an edge in the stationary area. The output signal of the control circuit 214 becomes a vertical edge signal used for motion determination.
[0032]
The motion determination circuit 206 divides the inter-field difference detection signal output from the absolute value circuit 205 by the vertical edge detection signal from the control circuit 214, and outputs the ratio as a motion determination value. If the motion judgment value is 1 or more, it is output as 1. In this way, the motion determination value is obtained as a multi-value as a ratio of two values.
[0033]
Further, the output signal of the line memory 201 and the input signal for interlace scanning are supplied to the average value circuit 218. The average value circuit 218 calculates an average value of these two signals and outputs this signal as an intra-field interpolation signal. That is, the output of the average value circuit 218 is the average value of the upper and lower lines of the interpolation line in the current field, and in FIG. 4, is the average value of the signal d and the signal e.
[0034]
The progressive conversion circuit 219 receives an output signal from the field memory 202, an input signal for interlace scanning, and an output signal from the average value circuit 218, and generates an interpolation signal based on the motion determination result output from the motion determination circuit 206. To convert to an image signal for progressive scanning.
[0035]
That is, the progressive conversion circuit 219 synthesizes the output signal from the average value circuit 218 and the output signal from the field memory 202 at a rate corresponding to the degree of motion output from the motion determination circuit 206 for the image signal in the current field. Thus, an interpolation signal is generated. That is, the signal b of the line corresponding to the interpolation line x in the previous field shown in FIG. 3 and the output signal of the average value circuit 218 are synthesized according to the degree of motion.
[0036]
Then, an image signal for progressive scanning is generated by alternately outputting an input image signal and an interpolation signal for each line.
[0037]
As described above, in this embodiment, the movement is performed by selecting the detection result of the vertical edge between lines in the previous field and the detection result of the vertical edge in the current field according to the change amount of the image signal in the current field and the previous field. The vertical field value of the previous field is used to prevent motion blur in areas that are moving, and thin edges can be detected as edges in areas that are stationary, improving the accuracy of motion determination. Is possible.
[0038]
Therefore, it is possible to improve the resolution of the stationary part and prevent the moving edge from being interpolated as motion blur while preventing the stationary fine horizontal stripe-shaped edge part from flickering. .
[0039]
In this embodiment, the frequency analysis circuit 217 is used, but the same effect can be obtained by image processing such as pattern matching.
[0040]
Next, a second embodiment of the present invention will be described.
[0041]
FIG. 4 is a block diagram showing the configuration of the conversion circuit 105 in this embodiment.
[0042]
4, the same components as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0043]
In this embodiment, the selection circuit 214 selects and outputs one of the output signal of the maximum value circuit 213 and the output signal of the absolute value circuit 216 based on the output of the inter-field difference detection circuit.
[0044]
That is, the selection circuit 214 selects the output signal of the absolute value circuit 216 when the output signal of the absolute value circuit 205 is larger than the predetermined threshold 2, and outputs the output of the maximum value circuit 213 when it is smaller than the threshold 2. The larger of the signal and the output signal of the absolute value circuit 216 is selected. The threshold value 2 may be a predetermined fixed value or a fluctuation value obtained by frequency analysis or the like.
[0045]
In this manner, the selection circuit 214 selects the output signal of the absolute value circuit 216 which is the edge signal of the current field in the moving area, and the edge signal of the current field and the edge signal of the previous field in the stationary area. Is selected, that is, the larger one of the output signal of the absolute value circuit 216 and the output signal of the maximum value circuit 213. By this processing, it is possible to prevent the occurrence of motion blur by using the value of the vertical edge of the previous field in the moving area, and to detect a fine edge as an edge in the stationary area.
[0046]
The motion determination circuit 206 performs motion determination as described above using the output signal from the vertical edge detection circuit selected in this way, and outputs the result to the progressive conversion circuit 219.
[0047]
Next, a third embodiment of the present invention will be described.
[0048]
FIG. 5 is a block diagram showing a configuration of the conversion circuit 105 in this embodiment. The same reference numerals are given to the same configurations as those in FIGS. 2 and 4, and a detailed description thereof will be omitted.
[0049]
In this embodiment, the selection circuit 214 selects and outputs one of the output signal of the maximum value circuit 211 and the output signal of the absolute value circuit 216 based on the output signal of the region determination circuit 220.
[0050]
The area determination circuit 220 receives the output signal of the field memory 202 and the output signals of the line memories 207 and 208, respectively. First, the absolute value A of the difference between the output signal of the field memory 202 and the output signal of the line memory 208 is obtained. If this value A is larger than the predetermined threshold 3, a logic 0 is output. If the value A is smaller than the threshold 3, an absolute value C of the difference between the output signal of the field memory 202, the average value B of the output signal of the line memory 208, and the output signal of the line memory 207 is obtained. When the value C is larger than the predetermined threshold value 4, a logic 0 is output. Further, when the value C is smaller than the threshold value 4, a logic 1 is output.
[0051]
Next, processing of the selection circuit 214 will be described.
[0052]
First, the selection circuit 214 compares the output signal of the absolute value circuit 205 and the threshold value 2 described above, and if smaller than the threshold value 2, the output signal of the maximum value circuit 211 and the output signal of the absolute value circuit 216 are larger. Select the method to output. Further, when the output signal of the absolute value circuit 205 is larger than the threshold 2, if the output signal of the area determination circuit 220 is 0, the output signal of the absolute value circuit 216 is selected. The larger one of the output signal of the circuit 211 and the output signal of the absolute value circuit 216 is selected and output.
[0053]
As described above, the selection circuit 214 selects the output signal of the absolute value circuit 216 which is the edge signal of the current field in the moving region, and the edge signal of the current field and the previous field in the stationary region. By selecting the maximum value of the edge signal, that is, the larger one of the output signal of the absolute value circuit 216 and the output signal of the maximum value circuit 211, motion blur using the value of the vertical edge of the previous field in the moving region is selected. Can be prevented, and a fine edge can be detected as an edge in a stationary region.
[0054]
The configuration using the region determination circuit 220 shown in FIG. 5 can be changed as shown in FIG.
[0055]
Processing of the area determination circuit 220 in the configuration of FIG. 6 will be described.
[0056]
The region determination circuit 220 receives the output signal of the HPF 221 in addition to the output signal of the field memory 220 and the output signals of the line memories 207 and 208. The HPF 221 filters the output signal of the field memory 202, extracts the high frequency component, and outputs it.
[0057]
First, the absolute value A of the difference between the output signal of the field memory 202 and the output signal of the line memory 208 is obtained, and when this value A is larger than the threshold 3, a logic 0 is output. When the value A is smaller than the threshold 3, the output signal of the HPF 221 is compared with the predetermined threshold 5, and when it is smaller than the threshold 5, a logic 0 is output. Further, when the output signal of the HPF 221 is larger than the threshold 5, the logic 1 is output.
[0058]
The selection circuit 214 selects one of the output signal of the maximum value circuit 211 and the output signal of the absolute value circuit 216 based on the output from the region determination circuit 220 output in this way, as described above.
[0059]
The threshold value 3 and the threshold value 5 may be predetermined fixed values or fluctuation values obtained by frequency analysis or the like. The processing of the area determination circuit 220 determines whether the interpolation line is a fine edge by image recognition such as pattern matching, and outputs 1 if it is a fine edge and outputs 0 if it is not a fine edge. Such a configuration can also be adopted.
[0060]
Next, a fourth embodiment will be described.
[0061]
FIG. 7 is a diagram showing the configuration of the conversion circuit 105 in this embodiment. The configuration and operation of the inter-field difference detection circuit, vertical edge detection circuit, motion determination circuit 206, average value circuit 218, and progressive conversion circuit 219 are shown in FIG. It is the same as that shown.
[0062]
In FIG. 7, the input signal of the inter-field difference detection circuit is an interlaced scanning input signal that has passed through the LPF 223, an output signal of the line memory 201 that has passed through the LPF 222, and an output signal of the field memory 202 that has passed through the LPF 224. . In the vertical edge detection circuit, an output signal from the field memory 202 is input via the LPF 225, and an input signal for interlace scanning and an output signal of the line memory 201 are input via the LPF 227 and LPF 226, respectively.
[0063]
By inputting the signal through the LPF in this way, it is possible to prevent the field difference detection circuit, the vertical edge detection circuit, and the region determination circuit 220 from outputting an incorrect value due to the influence of noise.
[0064]
In this embodiment, LPF is taken as an example of processing for suppressing noise. However, this processing may be a filter such as a median filter or a processing such as coring. Further, not all of these noise suppression circuits may be used.
[0065]
【The invention's effect】
As described above, it is possible to improve the accuracy of motion determination.
[0066]
Therefore, the resolution of the stationary part can be improved, and the moving edge can be prevented from being interpolated as motion blur while preventing the stationary fine horizontal stripe-shaped edge part from flickering. .
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of a recording apparatus to which the present invention is applied.
FIG. 2 is a diagram illustrating a configuration of a conversion circuit.
FIG. 3 is a diagram illustrating a state of an image signal.
FIG. 4 is a diagram illustrating another configuration of a conversion circuit.
FIG. 5 is a diagram showing another configuration of the conversion circuit.
FIG. 6 is a diagram illustrating another configuration of the conversion circuit.
FIG. 7 is a diagram showing another configuration of the conversion circuit.

Claims (11)

An apparatus for generating an interpolated signal using an input interlaced scanning image signal and converting the generated interlaced signal into a progressive scanning image signal using the interpolated signal,
Based on the temporal change amount and the spatial change amount of the image signal in the first field including the interpolation signal and the second field immediately before the first field, the difference between adjacent lines in the first field and the second field Vertical difference detection means for selecting and outputting one of the differences between adjacent lines in
Motion detection means for detecting motion between two consecutive fields in the input image signal using the output of the vertical difference detection means;
An image processing apparatus comprising: interpolation signal generation means for generating the interpolation signal based on the output of the motion detection means. An apparatus for generating an interpolated signal using an input interlaced scanning image signal and converting the generated interlaced signal into a progressive scanning image signal using the interpolated signal,
Field difference detection means for detecting a difference value between the image signal of the first field including the interpolation signal in the input image signal and the image signal of the second field immediately before the input signal;
Based on the output of the field difference detection means, one of the difference between the image signals of the adjacent lines in the first field and the difference between the image signals of the adjacent lines in the second field is selected. Vertical difference detection means for outputting;
Motion detection means for detecting motion between two consecutive fields in the input image signal using the output of the vertical difference detection means;
An image processing apparatus comprising: interpolation signal generation means for generating the interpolation signal based on the output of the motion detection means. 3. The field difference detection unit according to claim 2, wherein a difference value between an average value between image signals of adjacent lines in the first field and an image signal of the second field is obtained and output. Image processing device. The vertical difference detection unit selects and outputs a difference between image signals of adjacent lines in the first field when the field difference detection unit is larger than a predetermined threshold, If the difference is smaller, the maximum value of the difference between the image signals of adjacent lines in the first field and the image signal of adjacent lines in the second field is selected and output. The image processing apparatus according to claim 2. The vertical difference detection means further includes area determination means for detecting a change amount of a value between image signals of N lines including a line at a position corresponding to the line of the interpolation signal in the second field, Of the difference between the image signal of the adjacent line in the first field and the image signal of the adjacent line in the second field based on the output of the region determination unit and the output of the field difference detection unit The image processing apparatus according to claim 2, wherein one of the two is selected. The region determination means outputs a binary signal of logic 1 or 0, and the difference between the image signals of two lines adjacent above and below the line at the position corresponding to the interpolation signal in the second field and the first threshold value 6. The image processing apparatus according to claim 5, wherein when the difference between the image signals of the two lines is larger, a logic 0 signal is output. The area determination unit further includes, when the difference between the image signals of the two lines is smaller than the first threshold value, the average value of the image signals of the two lines and the line at the position corresponding to the interpolation signal. The difference between the image signal and the second threshold value is compared, and if the average value of the image signals of the two lines is larger, a logic 0 signal is output, and the image signal of the two lines is output. 7. The image processing apparatus according to claim 6, wherein when the average value is smaller, a logic 1 signal is output. The region determination means further applies a high-pass filter to the image signal of the line at the position corresponding to the interpolation signal in the second field when the difference between the image signals of the two lines is smaller than the first threshold. The processed signal is compared with the second threshold value, and when the second threshold value is smaller, a logic 0 signal is output, and when the second threshold value is larger, a logic 1 signal is output. The image processing apparatus according to claim 6, wherein the image processing apparatus outputs the image. When the output signal of the field difference detection circuit is smaller than a third threshold value, the vertical difference detection means detects the difference between the image signals of the adjacent lines in the first field and the adjacent lines in the second field. If the maximum value of the differences between the image signals is selected and output, and is larger than the third threshold value, the adjacent line in the first field is further output when the output signal of the region determination means is logic 0 The difference between the image signals of the adjacent lines in the first field and the difference between the image signals of the adjacent lines in the second field when logic 1 is selected is the maximum 9. The image processing apparatus according to claim 7, wherein a value is selected and a maximum value among the outputs is selected and output. The vertical difference detection means includes a low-pass filter that applies low-pass filter processing to the image signal of the first field and the image signal of the second field, respectively, and uses the output signal of the low-pass filter to The image processing apparatus according to claim 1, wherein a difference between adjacent lines in one field and a difference between adjacent lines in the second field are calculated. The field difference detection means includes a low-pass filter that applies low-pass filter processing to the image signal of the first field and the image signal of the second field, and uses the output signal of the low-pass filter. 3. The image processing apparatus according to claim 2, wherein a difference between the image signal of one field and the image signal of the second field is calculated.

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