JP2005039134A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device of a COC (chip-on-chip)configuration, wherein the flexibility of a circuit layout design in an IC chip is raised and the area ratio of a power source wiring is decreased to materialize high integration. <P>SOLUTION: The semiconductor integrated circuit device of the COC configuration is constituted of a first IC chip LSI 1 to be operated at a first power source voltage, and a second IC chip LSI 2 which is mounted on the first IC chip and is operated at a second power source voltage different from the first power source voltage. First and second power source voltages VDD1, VDD2 are fed from the exterior to the first IC chip, and the second power source voltage is fed to the second IC chip through the first IC chip. The first IC chip is formed with a circuit 105 requiring the second power source voltage, and the second IC chip comprises a power source wiring XXVDD2 for feeding the second power voltage to the circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device having a COC (chip on chip) configuration in which one or a plurality of IC chips operating at different power supply voltages are mounted on one semiconductor chip (IC chip).

As shown in FIG. 1, a semiconductor integrated circuit device having a COC configuration has one or a plurality of IC chips (on-chip) LSI2 mounted on a single IC chip (base chip) LSI1 as a base by means of flip mounting. And the signal lines and power lines of both chips are connected to each other, and the signal and power supply are connected to the base chip and on-chip via the signal pads and power pads provided on the base chip. It has been. An example of this type of COC semiconductor integrated circuit device is disclosed in Patent Document 1. In this COC, when the base chip and the on-chip are configured as IC chips that operate with different power supply voltages, a circuit that operates with a voltage used in the other IC chip as part of one of the IC chips Part may be formed. For example, when a voltage signal output from an on-chip operating at 5V is output from a signal pad of the base chip as a voltage signal of an operating voltage of a base chip operating at 3V, a 5V signal is applied to a part of the base chip at 3V. It is necessary to configure a level shift circuit for converting to a signal. In this level shift circuit, it is necessary to supply a base chip voltage of 3 V and an on-chip voltage of 5 V, and it is necessary to arrange these 3 V and 5 V power supply wirings in the base chip.
JP 2000-114386 A

  For example, the example shown in FIG. 11 shows a configuration example in which level shift circuits 105 are arranged at three island-like locations in the substantially central region of the base chip LSI 1A. In the base chip LSI 1A, external connection pads 101 such as signal pads and power pads are arranged in the periphery, IO cells (input / output cells) 102 and power cells 103 are arranged inside, and further, VDD1 (3V), VDD2 inside. (5V), GND (0V) circuit wirings SVDD1, SVDD2, and SGND are provided. For each of the three level shift circuits 105, VDD1, VDD2, and GND power supply rings RVDD1, RVDD2, and RGND that circulate around each level shift circuit 105 are provided. Of the power supply rings RVDD1, RVDD2, and RGND surrounding the level shift circuit 105, the power supply rings RVDD1 and RGND are electrically connected by power supply wirings YVDD1 and YGND respectively connected to the peripheral wirings SVDD1 and SGND. On the other hand, the power supply ring RVDD2 which is not the original power supply voltage of the base chip LSI 1A is electrically connected to the peripheral wiring SVDD2 by the thick connection wirings XVVD2 and YVDD2.

  Each part in the plurality of level shift circuits 105 arranged in an island shape in the base chip LSI 1A is electrically connected to each power supply ring RVDD1, RVDD2, RGND so that each voltage is supplied to perform a predetermined operation. It has become. Further, the level shift circuit 105 is electrically connected to an on-chip (LSI 2 in FIG. 1) mounted immediately above via a signal COC pad PS. A VDD2 COC pad P2 and a GND COC pad PG are disposed on the power supply wirings YDD2 and YGND, and the on-chip LSI 2 mounted on the base chip LSI 1A is provided via these COC pads P2 and PG. The power supply voltage is supplied to the on-chip LSI 2 by electrical connection.

  Here, as a different example of the level shift circuit 105, there is a configuration shown in FIG. In this case, the level shift circuit 105 is composed of a plurality of level shift circuit cells CELL, and of the power supply rings RVDD1, RVDD2, and RGND surrounding the level shift circuit 105, the power supply rings RVDD1 and RGND are the above-described peripheral wirings SVDD1, They are electrically connected by power lines YVDD1, YGND and XVDD1, XGND individually connected to SGND. On the other hand, the power supply ring RVDD2 which is not the original power supply voltage of the base chip LSI 1A is electrically connected to the peripheral wiring SVDD2 by the thick connection wiring XVDD2. In this example, the signal COC pad PS is disposed between the power wiring lines YVDD1, YGND and XVDD1, XGND, and is electrically connected to an on-chip mounted immediately above.

  Thus, in order to supply VDD2 which is not the original power supply voltage of the base chip LSI 1A to the level shift circuit 105 provided in the base chip LSI 1A, each of the power supply voltages VDD1, VDD2, GND is conventionally provided around the level shift circuit 105. The power supply rings RVDD1, RVDD2, and RGND must be provided, and the wiring widths of the connection wirings YVVD2 and XVDD2 connected to the power supply ring RVDD2 are formed to be thick corresponding to the electric capacity required for the level shift circuit 105. Must. Therefore, the ratio of the area occupied by the power supply wiring including the power supply ring and the connection wiring to the base chip LSI 1A is so large that it cannot be ignored, which is an obstacle to high integration of various circuit elements in the semiconductor integrated circuit device. In particular, when the level shift circuit is disposed at a plurality of locations on the base chip and at positions separated from each other, a power ring or connection wiring is required for each level shift circuit, and the area occupied by the power supply wiring Is extremely large.

  In this case, it is conceivable to reduce the area ratio of the power supply ring and the connection wiring by combining a plurality of level shift circuits in one place, but this suppresses the degree of freedom in circuit layout design in the base chip, and level The degree of freedom in designing the circuit layout in the on-chip connected to the shift circuit is also suppressed, resulting in a problem that it becomes difficult to design the IC chip. In addition, such a problem is not limited to the level shift circuit in the base chip, but when a circuit unit that operates at a voltage different from the original voltage used in the IC chip is provided in a part of the IC chip. Is similarly generated. Therefore, in the example of FIG. 11, even when a circuit portion that operates at 3 V is disposed on an on-chip that operates at 5 V, the area ratio of the power supply wiring in the on-chip increases, and the semiconductor integrated circuit device is highly integrated. It is the same that it becomes an obstacle of the conversion.

  An object of the present invention is to increase the degree of freedom of circuit layout design and reduce the area ratio of power supply wiring even when a circuit unit that operates at different voltages is disposed on an IC chip in a semiconductor integrated circuit device having a COC configuration. Thus, a semiconductor integrated circuit device that can easily achieve high integration is provided.

  The present invention provides a first IC chip that is operated with a first power supply voltage, and a second IC that is mounted on the first IC chip and is operated with a second power supply voltage different from the first power supply voltage. A chip in which the first and second power supply voltages are supplied from the outside to the first IC chip, and the second power supply voltage is supplied to the second IC chip via the first IC chip. In the on-chip semiconductor integrated circuit device, one of the first or second IC chips has a circuit portion that requires a power supply voltage for operating the other IC chip, The other IC chip is provided with a power supply wiring for supplying a power supply voltage for operating the other IC chip to the circuit portion.

  According to the present invention, the second power supply voltage input from the outside to the first IC chip is supplied from the first IC chip from a partial region of the second IC chip. After the power supply voltage is transmitted to the other area of the second IC chip through the power supply wiring provided in the second IC chip, it is supplied to the circuit portion provided in the first IC chip in this area. The first IC chip does not require a power supply wiring for supplying the second power supply voltage from the input region of the second power supply voltage to the circuit portion, and the area ratio occupied by the power supply wiring in the first IC chip Can be reduced, and high integration in the first IC chip can be realized. Alternatively, the power supply wiring for supplying the first power supply voltage to the circuit provided in the second IC chip becomes unnecessary, and high integration in the second IC chip can be realized. Thus, according to the present invention, it is possible to highly integrate a semiconductor integrated circuit device having a COC configuration.

In the present invention, it is preferable to take the following form.
(1) A circuit portion that requires a second power supply voltage is formed in the first IC chip, and a power supply wiring for supplying the second power supply voltage to the circuit portion is formed in the second IC chip. Prepare.
(2) A circuit portion that requires the first power supply voltage is formed on the second IC chip, and power supply wiring for supplying the first power supply voltage to the circuit portion is formed on the first IC chip. Prepare.
(3) The first IC chip is provided with a circuit portion that requires the first power supply voltage and the second power supply voltage, and the second IC chip supplies the second power supply voltage to the circuit portion. Power supply wiring is provided.
(4) The second IC chip has a circuit portion that requires the first power supply voltage and the second power supply voltage. The first IC chip supplies the first power supply voltage to the circuit portion. Power supply wiring is provided.

  Here, in the present invention, the first IC chip and the second IC chip are each provided with a power supply pad in an area where the circuit portion is disposed, and the second IC chip is placed on the first IC chip. The power supply pads of both IC chips are electrically connected to each other when mounted on.

  In the present invention, the second IC chip is composed of one or a plurality of IC chips, and each of the plurality of second IC chips operates with the same power supply voltage. Alternatively, the second IC chip is configured by one or a plurality of IC chips, and the plurality of second IC chips are operated by different power supply voltages.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is an external perspective view of Embodiment 1 of the present invention, and FIG. 2 is a longitudinal sectional view thereof. A rectangular base chip LSI 1 and an on-chip LSI 2 mounted on the base chip LSI 1 constitute a semiconductor integrated circuit device having a COC configuration. Here, the base chip LSI1 is mainly composed of circuit elements that operate at a power supply voltage VDD1 (here 3V), and the on-chip LSI2 is mainly composed of circuit elements that operate at a power supply voltage VDD2 (here 5V) different from this. It is configured. FIG. 3 is a plan view of the surface of the base chip LSI 1. The base chip LSI 1 has a large number of external connection pads 101 arranged in the peripheral portion, and the IO cells 102 are arranged in the circumferential direction along the inside of the external connection pads 101. It is arranged. A power supply cell 103 is disposed in a part of the IO cell 102. Further, an internal circuit 104 having a required circuit configuration is formed in the central region of the base chip LSI 1 surrounded by the IO cells 102. Here, in a partial region of the internal circuit 104, particularly in a region where the on-chip LSI 2 indicated by a two-dot chain line in the figure is mounted, the base chip is operated at seven locations indicated by the chain line in the figure. Is provided with a circuit section that requires both the power supply voltage VDD1 and the power supply voltage VDD2 for operating the on-chip LSI 2 mounted on the base chip LSI1, in this case, a level shift circuit 105 is provided.

  In the area of the internal circuit 104 in which the on-chip LSI 2 is mounted, the level shift circuit 105 and the power supply connection area 106 divided into areas different from the level shift circuit 105 are provided. A large number of COC pads 107 for electrical connection between the base chip LSI 1 and the on-chip LSI 2 are arranged. Here, the COC pad 107 includes a signal COC pad PS for making a signal connection between the base chip LSI 1 and the on-chip LSI 2 and a VDD2 COC pad P2 for making a connection of the voltage VDD2. It is installed. In the power supply connection area 105, a signal COC pad PS, a VDD2 COC pad P2, and a GND pad PG for connecting GND are disposed.

  A signal wiring that does not appear in the figure connecting the IO cell 102 and the internal circuit 104 is provided, and the internal circuit 104, the power supply cell 103, the power supply, as shown in FIG. A power supply wiring 108 for connecting the external connection pads 101 used as pads to each other is provided. The power supply pads are composed of a VDD1 power supply pad PVDD1, a VDD2 power supply pad PVDD2, and a GND power supply pad PGND. The power supply wiring 108 is connected to each of the power supply wirings SVDD1, SVDD2, and SGND for VDD1, VDD2, and GND that are circulated along the inside of the IO cell, and the internal power supply wiring 104. In this region, a plurality of VDD1 internal power supply wirings YVDD1, VDD2 internal power supply wirings YVDD2 and GND internal power supply wirings YGND are arranged in a stripe shape extending in the Y direction. The VDD1 power supply pad PVDD1 is connected to the VDD1 peripheral power supply line SVDD1 via the corresponding power supply cell, and the VDD2 power supply pad PVDD2 is connected to the VDD2 peripheral power supply wiring SVDD2 via the corresponding power supply cell, and the GND power supply pad. PGND is connected to the GND peripheral power supply wiring SGND via the corresponding power supply cell.

  Among the internal power supply lines, the VDD1 internal power supply line YVDD1 and the GND internal power supply line YGND are arranged over the entire area of the internal circuit 104, and each element in the internal circuit 104 formed in the base chip LSI1. It is formed so that electrical connection can be made. On the other hand, the VDD2 internal power supply wiring YVDD2 is arranged in parallel to the pitch between the VDD1 internal power supply wiring YVDD1 and the GND internal power supply wiring YGND only in the power supply connection region 106 of the internal circuit 104. In the power connection region 106, as described above, a plurality of VDD2 COC pads P2 are arranged on the VDD2 internal power supply wiring YVDD2, and a plurality of GND COC pads PG are arranged on the GND internal power supply wiring YGND. It is arranged. In the level shift circuit 105 of the internal circuit 104, the signal COC pad PS and the VDD2 COC pad P2 are electrically insulated from the VDD1 internal power supply wiring YVDD1 and the GND internal power supply wiring YGND, respectively. They are arranged in the gaps between these internal power supply wirings.

  FIG. 4 is an enlarged detailed view of the level shift circuit surrounded by a solid line among the seven level shift circuits 105 shown in FIG. The plurality of level shift circuit cells CELL constituting the level shift circuit 105 are each configured by transistor elements, and are configured in a desired arrangement. Each level shift circuit cell CELL is connected to the signal COC pad PS via a via hole VIA and a signal wiring HS. On the other hand, the VDD1 lower layer wiring XVDD1, the VDD2 lower layer wiring XVDD2, and the GND lower layer wiring XGND extending in the X direction over each level shift circuit 105 are arranged in parallel in the Y direction. Electrically connected to the circuit cell. The VDD1 lower layer wiring XVDD1 is connected to the VDD1 internal power supply wiring YVDD1 through a via hole VIA, and the GND lower layer wiring XGND is connected to the GND internal power supply wiring YGND through a via hole VIA. On the other hand, the VDD2 lower layer wiring XVDD2 is electrically connected to the VDD2 COC pad P2 through a via hole VIA.

  FIG. 5 is a plan view of the surface of the on-chip LSI 2 facing downward, and shows the surface on which electrical connection is made opposite to the surface of the base chip LSI 1. The on-chip LSI 2 is formed with various internal circuits not shown in the figure, and on its surface, a signal COC pad PSS, a VDD2 COC pad P22, and a GND COC pad electrically connected to these internal circuits. Each PGG is arranged in a region corresponding to each COC pad PS, P2, PG of the base chip LSI1. In addition, a plurality of power supply wires are formed which are arranged in the Y direction at a pitch equal to the arrangement pitch of the COC pads in the Y direction and extend in the X direction. These power supply wirings are configured, for example, as GND power supply wiring XXGND and VDD2 power supply wiring XXVDD2 alternately in the Y direction. The GND COC pads are separated in the X direction on the same Y coordinate by the GND power supply wiring XXGND. PGG are electrically connected to each other, and similarly, a VDD2 COC pad P22 separated in the X direction on the Y coordinate by the VDD2 power supply wiring XXVDD2 is electrically connected to each other. The signal COC pad PSS is disposed between the power supply lines PXGND and XXVDD2 so as to be insulated from each other.

  As shown in FIG. 2, the on-chip LSI 2 is placed on the surface of the base chip LSI 1 with the surface turned upside down and the COC pads PSS, A semiconductor integrated circuit having a COC structure is connected to the corresponding COC pads PS, PG, P2 of the base chip LSI1 by metal balls 109 formed on PGG, P22, and a sealing resin 110 is filled between the two chips. The device is configured. Although not shown, the semiconductor integrated circuit device configured in this way is mounted on a lead frame on the back surface of the base chip LSI 1 and is used for external connection such as signal pads and power pads around the base chip LSI 1. Wire bonding is performed to connect the pad 101 to the internal lead of the lead frame. Further, the package is formed by sealing the whole with a sealing resin or ceramic, but the description thereof is omitted here.

  The operation of this semiconductor integrated circuit device will be described with reference to FIG. 6 showing a schematic circuit configuration. In FIG. 6, the alternate long and short dash line indicates a signal line, and the solid line indicates a power supply line. The power of VDD1, VDD2, and GND is supplied from the outside to the power pads of the base chip LSI1, that is, the power pads PVDD1, VDD2 and PGND2, and the GND power pad PGND for VDD1, respectively, via bonding wires. Various signals are supplied to the external connection pad 101 as the signal pad of the base chip LSI 1. The VDD1 and the GND supplied to the VDD1 power supply pad PVDD1 and the GND power supply pad PGND are supplied via the VDD1 peripheral power supply wiring SVDD1, the GND peripheral power supply wiring SGND, the VDD1 internal power supply wiring YVDD1, and the GND internal power supply wiring YGND. Are supplied to the region of the internal circuit 104, and further supplied from these power supply wirings to the lower layer wiring XVDD1 for VDD1 and the lower layer wiring XGND for GND, and supplied to each element circuit 111 of the internal circuit 104. This is the same in that power is supplied to the level shift circuit cell CELL constituting the level shift circuit 105.

  On the other hand, VDD2 supplied to the VDD2 power supply pad PVDD2 of the base chip LSI2 is transmitted from the VDD2 peripheral power supply wiring SVDD2 to the VDD2 internal power supply wiring YVDD2 in the power supply connection region 106. In this power connection region 106, the on-chip LSI 2 in which the VDD2 COC pad P2 on the VDD2 internal power supply wiring YVDD2 and the GND COC pad PG on the GND internal power supply wiring YGND are mounted on the base chip LSI1, respectively. The VDD2 COC pad P22 and the GND COC pad PGG are electrically connected to each other through the metal balls 109, so that the VDD2 and GND are respectively connected to the respective elements of the on-chip LSI 2 by the VDD2 power supply wiring XXVDD2 and GND power supply wiring XXGND. Each element circuit 112 formed in the on-chip LSI 2 is operated by the supplied VDD 2 and GND.

  Further, of VDD2 and GND supplied to each part of these on-chip LSIs 2, VDD2 is supplied to the VDD2 COC pad P22 by the VDD2 power supply wiring XXVDD2. Since the VDD2 COC pad P22 is electrically connected to the VDD2 COC pad P2 provided in the level shift circuit 105 of the base chip LSI 1 via the metal ball 108, VDD2 is connected to these pads P22 and P2. Is supplied to the lower layer wiring XVDD2 of the level shift circuit 105, and further supplied to the level shift circuit CELL cell. As a result, the level shift circuit 105 can perform a predetermined operation with two power supplies of VDD1 and VDD2 by adding VDD2 supplied via the on-chip LSI2 together with VDD1 supplied from the base chip LSI1.

  At the same time, since the signal COC pad PSS of the on-chip LSI 2 and the signal COC pad PS of the level shift circuit 105 of the base chip LSI 1 are connected, the VDD2 level output from the predetermined element circuit 112 of the on-chip LSI 2 Is input to the level shift circuit 105 through these signal COC pads PS and PSS, and is level-shifted to a VDD1 level signal from the signal pad PSIG of the external connection pads 101 of the base chip LSI1. It will be output to the outside. On the other hand, the VDD1 level signal input to the element circuit 111 of the base chip LSI 1 from the signal pad PSIG of the base chip LSI 1 and subjected to predetermined processing is level-shifted to a VDD2 level signal by the level shift circuit 105, It is also possible to configure so as to be output to the element circuit 112 of the on-chip LSI 2 via the COC pad PS for use.

  As described above, in the semiconductor integrated circuit device according to the first embodiment, VDD2 input from the outside to the power supply pad PVDD2 of the base chip LSI1 is once supplied from the base chip LSI1 to the onchip LSI2 and is turned on through the power supply wiring of the onchip LSI2. After being transmitted to the other area of the chip LSI 2, it is supplied from the on-chip LSI 2 to the level shift circuit 105 of the base chip LSI 1 via the COC pads P2 and P22 in that area. Therefore, it is not necessary to provide power supply wiring for supplying VDD2 to the level shift circuit 105 provided in the base chip LSI1, for example, a power supply ring as shown in FIG. 11, in the base chip. The area ratio occupied by can be reduced. In particular, when the level shift circuit 105 is configured separately at a plurality of locations of the base chip LSI 1 as in the present embodiment, the power supply is compared with the conventional configuration in which each level shift circuit 105 is provided with a power supply ring. The area ratio of the wiring can be greatly reduced. Thereby, high integration of the base chip or high integration of the semiconductor integrated circuit device having the COC configuration can be realized.

  Further, in this semiconductor integrated circuit device, even when the level shift circuit 105 is arranged at an arbitrary position of the base chip LSI1, VDD2 can be easily supplied to the level shift circuit 105 via the on-chip LSI2. Therefore, the degree of freedom in circuit layout design in the base chip LSI 1 is increased, and it becomes easy to minimize the length of the power supply wiring such as VDD1, GND, etc. in the base chip LSI 1, thereby achieving further higher integration and semiconductor integration. This is also advantageous for speeding up the operation of the circuit device.

  In the first embodiment, an example of a semiconductor integrated circuit device having a COC configuration in which the level shift circuit 105 that requires VDD2 is formed as a part of the base chip LSI1 that operates at VDD1 is shown. On the contrary, the on-chip LSI2 that operates at VDD2 It is also possible to apply the present invention to a COC-structured semiconductor integrated circuit device that constitutes a level shift circuit that requires the same VDD1 as the element circuit of the base chip LSI1 as a part thereof. FIG. 7 is a schematic configuration diagram of the second embodiment in such a case. Similarly to the first embodiment, VDD1, VDD2, and GND are supplied to the base chip LSI1 from the outside through power supply pads PVDD1, PVDD2. . In addition, the base chip LSI1 is formed with an element circuit 111 that operates at VDD1. On the other hand, an on-chip LSI 2 mounted on the base chip LSI 1 is provided with a level shift circuit 105 that requires VDD 1 as well as an element circuit 112 operated by VDD 2.

  In such a configuration, the VDD1 internal power supply wiring XVDD1 connected to the VDD1 power supply pad PVDD1 is extended to the region corresponding to the level shift circuit 105 of the on-chip LSI2 in the base chip LSI1, and the VDD1 internal power supply wiring XVDD1 is formed on the base chip LSI1. A COC pad P1 for VDD1 is formed. Further, the VDD1 COC pad P11 facing the VDD1 COC pad P1 is formed in the area of the level shift circuit 105 in the on-chip LSI2, and when the on-chip LSI2 is mounted on the base chip LSI1, both the VDD1 COCs are mounted. The pads P1 and P11 are configured to be electrically connected to each other via the metal ball 109. Note that the VDD 2 supplied to the base chip LSI 1 is supplied to the element circuit 112 of the on-chip LSI 2 through the VDD 2 power supply pad PVDD 2 as in the first embodiment, and a part of the on-chip LSI 2 is a level shift circuit. Needless to say, it is also supplied to 105.

  According to the second embodiment, the level shift circuit 105 of the on-chip LSI 2 is supplied with VDD2 and GND, which are the operating voltages of the on-chip LSI 2, and directly from the base chip LSI 1 via the VDD1 COC pad P1. Thus, VDD1 is supplied, and the level shift circuit 105 is operated. Therefore, it is not necessary to provide power supply wiring for supplying VDD1 to the level shift circuit 105 of the on-chip LSI 2 in the on-chip LSI 2, and the area ratio occupied by the power supply wiring in the on-chip LSI 2 can be reduced. As a result, high integration of the on-chip LSI 2 or high integration of the semiconductor integrated circuit device having the COC configuration can be realized.

  The present invention also includes a case in which an element circuit that operates only with VDD2 is provided in a part of a base chip that is configured with an element circuit that operates with VDD1, or conversely, an element circuit that operates with VDD2 The present invention can also be applied to a COC-structured semiconductor integrated circuit device in which an element circuit that operates only with VDD1 is provided in a part of the on-chip. For example, FIG. 8 is a schematic diagram as Example 3 showing the former configuration example. As in the first embodiment, a shift register circuit 105 is formed in the base chip LSI1 as an element circuit that operates at VDD1 and VDD2, and operates at a different VDD2 from the element circuit 111 that operates at VDD1 of the base chip LSI1. An element circuit 113 for VDD2 is formed. The base chip LSI 1 and the on-chip LSI 2 in the region where the VDD 2 element circuit 112 is formed have the VDD 2 COC pad P 2 formed in the same manner as the shift register circuit 105. When the chip LSI 2 is mounted, both the CO2 pads P2 and P22 for VDD2 are electrically connected to each other.

  In the semiconductor integrated circuit device according to the third embodiment, when VDD1 and VDD2 are supplied from the outside to the base chip LSI1, VDD1 is supplied to the level shift circuit 105 as in the first embodiment, and the VDD2 COC pad P2,. VDD2 is supplied from the on-chip LSI 2 via P22 and is operated by both voltages VDD1 and VDD2. Similarly, the VDD2 element circuit 113 is operated only by VDD2 supplied from the on-chip LSI 2. Thus, it is not necessary to provide power supply wiring for supplying VDD2 to the level shift circuit 105 and the VDD2 element circuit 113 in the base chip LSI1, and the area ratio of the power supply wiring in the base chip LSI1 is reduced. Therefore, it is possible to realize high integration of the base chip LSI 1 or high integration of a semiconductor integrated circuit device having a COC configuration.

  Further, each of the above embodiments shows an example in which one on-chip is mounted on the base chip, but it goes without saying that the present invention can be applied even when two or more on-chips are mounted. For example, FIG. 9 is a schematic diagram of a semiconductor integrated circuit device according to the fourth embodiment having a COC configuration in which two on-chip LSIs 21 and 22 are mounted on the base chip LSI 1. Areas corresponding to the two on-chip LSIs 21 and 22, respectively. The level shift circuits 105a and 105b are disposed in the base chip LSI1, and the two on-chip LSIs 21 and 22 are configured similarly to the on-chip of the first embodiment for the level shift circuits 105a and 105b. Thus, VDD2 can be supplied to the level shift circuits 105a and 105b via separate on-chip LSIs 21 and 22, respectively. Even in the case of such a configuration, it is needless to say that the high integration of the semiconductor integrated circuit device can be realized by reducing the area ratio of the power supply wiring in the base chip LSI 1.

  The above description is an example in which the present invention is applied to a semiconductor integrated circuit device that is operated with two different power supply voltages of VDD1 and VDD2, but the present invention is applied to a semiconductor integrated circuit device that is operated with three or more different power supply voltages. It is also possible to apply. FIG. 10 is a schematic plan view showing a configuration example of the semiconductor integrated circuit device according to the fifth embodiment that is operated with three different power supply voltages VDD1, VDD2, and VDD3. Here, the base chip LSI1 is operated with the power supply voltage VDD1, and a VDD2 on-chip LSI2 operating with a different power supply voltage VDD2 and a VDD3 on-chip LSI3 operating with a different power supply voltage VDD3 are mounted on the base chip LSI1, respectively. 2 shows an example in which a semiconductor integrated circuit device having a COC configuration is configured. Here, the first element circuit 114 that requires VDD2 is disposed in the base chip LSI1 in the region immediately below the VDD2 on-chip LSI 21, and VDD3 is required in the base chip in the region immediately below the VDD3 on-chip LSI3. When the second element circuit 115 is provided, VDD2 is supplied to the first element circuit 114 via the VDD2 on-chip LSI2, and VDD3 is supplied to the second element circuit 115 via the VDD3 on-chip LSI3. To supply. In the VDD2 on-chip LSI 2 and the VDD3 on-chip LSI 3, the configuration for supplying VDD2 and VDD3 to the first and second element circuits 114 and 115 uses the COC pad provided on each chip as in the above embodiments. Needless to say.

  According to this embodiment, by supplying three different power supply voltages to the base chip LSI 1, the respective on-chip LSIs 2, LSI 3 that operate at different power supply voltages VDD 2, VDD 3 can be operated and provided in the base chip LSI 1. The element circuits 114 and 115 that require VDD2 and VDD3 can be operated. Even in this case, the base chip LSI1 is supplied with VDD2 and VDD3 to the first and second element circuits 114 and 115, respectively. There is no need to form a power supply wiring, and the area ratio of the power supply wiring can be reduced and high integration can be realized.

  In the above description of the embodiment, an example of a shift register circuit is shown as an internal circuit that operates with two different power supply voltages VDD1 and VDD2, or an internal circuit that operates with two different power supply voltages VDD1 and VDD3. However, the present invention can be similarly applied to any circuit that operates with two different power supply voltages.

  In addition, as described in the third embodiment, the present invention provides a semiconductor having a COC configuration of a first IC chip that is operated with a predetermined power supply voltage and a second IC chip that is operated with a power supply voltage different from the first IC chip. When configuring an integrated circuit device, the present invention can be similarly applied as long as a part of the circuit of one of the IC chips includes a circuit that operates at the operating voltage of the other IC chip. .

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an external perspective view in which a part of a first embodiment of a semiconductor integrated circuit device of the present invention is broken. FIG. 2 is a longitudinal sectional view of a schematic configuration of the semiconductor integrated circuit device of FIG. 1. It is a surface view of a base chip. It is an enlarged view which shows the element structure of the principal part of FIG. It is an on-chip surface view. 2 is a wiring configuration diagram illustrating a schematic configuration of Example 1. FIG. 6 is a wiring configuration diagram showing a schematic configuration of an embodiment of Example 2. FIG. 6 is a wiring configuration diagram showing a schematic configuration of an embodiment of Example 3. FIG. 10 is a plan view showing a schematic configuration of Example 4. FIG. 10 is a wiring configuration diagram showing a schematic configuration of Example 5. FIG. It is a surface view of the base chip of the conventional COC semiconductor integrated circuit device. It is an enlarged view of a part of surface of a different conventional COC semiconductor integrated circuit device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 External connection pad 102 IO cell 103 Power supply pad 104 Internal circuit 105 Level shift circuit 106 Power supply connection area 107 COC pad 108 Power supply wiring 109 Metal ball 110 Sealing resin 111-115 Element circuit PVDD1 VDD1 power supply pad PVDD2 VDD2 power supply pad PGND GND power supply pad PSIG Signal pad P1, P11 VDD1 COC pad P2, P22 VDD2 COC pad PG, PGG GND COC pad PS, PSS signal COC pad SVDD1 VDD1 peripheral power supply wiring SVDD2 VDD2 peripheral power supply wiring SGND GND power supply wiring YVDD1 VDD1 internal power supply wiring YVDD2 VDD2 internal power supply wiring YGND GND internal power supply wiring XVDD1 VDD1 lower layer wiring XVDD2 VDD2 lower layer wiring XGND GND lower layer wiring XXGND GND power supply wiring XXVDD2 VD Power supply wiring for D2

Claims (8)

  A first IC chip operated with a first power supply voltage, and a second IC chip mounted on the first IC chip and operated with a second power supply voltage different from the first power supply voltage; The first and second power supply voltages are supplied to the first IC chip from the outside, and the second power supply voltage is supplied to the second IC chip via the first IC chip. In a semiconductor integrated circuit device having a chip-on-chip configuration, a circuit portion that requires a power supply voltage for operating the other IC chip is formed on one of the first or second IC chips. A semiconductor integrated circuit device, wherein the other IC chip is provided with power supply wiring for supplying a power supply voltage for operating the other IC chip to the circuit portion.   The first IC chip is formed with a circuit portion that requires a second power supply voltage, and the second IC chip has a power supply wiring for supplying the second power supply voltage to the circuit portion. The semiconductor integrated circuit device according to claim 1, further comprising:   The second IC chip has a circuit portion that requires a first power supply voltage, and the first IC chip has a power supply wiring for supplying the first power supply voltage to the circuit portion. The semiconductor integrated circuit device according to claim 1, further comprising:   The first IC chip is provided with a circuit portion that requires a first power supply voltage and a second power supply voltage, and the second IC chip supplies a second power supply voltage to the circuit portion. The semiconductor integrated circuit device according to claim 2, further comprising a power supply wiring for performing the operation.   The second IC chip is formed with a circuit portion that requires a first power supply voltage and a second power supply voltage, and the first IC chip supplies the first power supply voltage to the circuit portion. The semiconductor integrated circuit device according to claim 3, further comprising a power supply wiring for performing the operation.   When the first IC chip and the second IC chip are each provided with a power supply pad in an area where the circuit portion is disposed, and the second IC chip is mounted on the first IC chip. 6. The semiconductor integrated circuit device according to claim 1, wherein the power supply pads of both IC chips are electrically connected to each other.   7. The device according to claim 1, wherein the second IC chip is composed of one or a plurality of IC chips, and each of the plurality of second IC chips operates with the same power supply voltage. 8. Semiconductor integrated circuit device.   The said 2nd IC chip is comprised by 1 or several IC chip, and these 2nd IC chips operate | move with a different power supply voltage, respectively. Semiconductor integrated circuit device.

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