JP2005037126A - Charge dispersion test vector generation method and system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a generation method for a charge sharing test vector, allowing a test in a circuit including an additional electronic circuit for suppressing influence of charge sharing. <P>SOLUTION: This charge sharing test vector generation method includes a logic cell, a discharge AND gate 102 and a charge sharing AND gate 104. A test model 98 comprising an auxiliary test circuit 100 is prepared. An automatic test pattern generator 124 generates a first test vector 120 to the test model 98 to supply an input pattern for discharging charges of a discharge node to the discharge node of the logic cell, makes the discharge AND gate 102 output a logic level 1, generates a second test vector 122 to supply an input pattern for calling behavior of worst charge dispersion to the logic cell, and makes the charge sharing AND gate 104 output a logic level 1. The logic cell supplies an output 130 for verifying results of both the vectors. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates generally to the field of integrated circuits, and more particularly to a method and system for generating a charge sharing test vector.
[0002]
[Prior art]
Integrated circuits designed using domino logic and / or dynamic logic are generally designed to minimize the effects of charge sharing. Charge distribution refers to a redistribution of charge between two nodes when they are connected to each other at different initial voltages in the circuit. For example, consider that the first node is at a high voltage and the second node is at a low voltage. When these two nodes are connected together, the charge from the first node is partially redistributed to the second node. This redistribution can cause inaccurate circuit operation. This is because nodes that should be at high voltage levels can be lowered in their voltage levels to the extent that the values of the nodes are misinterpreted.
[0003]
A conventional solution to the charge distribution problem involves precharging one or more intermediate nodes by adding a p-channel precharge transistor. Another conventional solution involves implementing dual logic and using p-channel cross-connected transistors to cross connect the dual logic initial storage nodes. Another conventional solution to the charge distribution problem is to provide a feedback transistor to hold the initial storage node at a constant voltage level at the end of precharge.
[0004]
[Problems to be solved by the invention]
All conventional solutions to the charge distribution problem include adding additional electronic circuitry to the integrated circuit. However, such additional electronic circuits generally cannot be tested by integrated circuit testing techniques and automatic test pattern generators. As a result, the state of the electronic circuit under the influence of a set of manufacturing defects remains unknown.
[0005]
[Means for Solving the Problems]
In accordance with the present invention, charge distribution test vector generation methods and systems are provided that substantially eliminate or reduce the disadvantages and problems associated with conventional test vector generation. In particular, charge dispersion test vectors are generated and used to test the accuracy of circuit behavior under the influence of charge dispersion.
[0006]
In accordance with an embodiment of the present invention, a method for generating a charge distribution test vector for a circuit is provided, the method comprising providing an automatic test pattern generator operable to generate a first test vector and a second test vector. . The method further includes providing a test model including a logic cell of the circuit and an auxiliary test circuit, wherein the auxiliary test circuit includes a discharge AND gate and a charge distribution AND gate. The method then includes the step of selecting the output of the discharge AND gate as the target for generating a falling transition fault vector by an automatic test pattern generator. The method then includes generating a first test vector for the test model using an automatic test pattern generator, where the first test vector provides an input pattern to the discharge node of the logic cell. In addition, the discharge AND gate evaluates to logic level 1 for the first test vector. The method then includes generating a second test vector for the test model using an automatic test pattern generator, where the second test vector invokes the worst charge distribution behavior for the logic cell. Supply the input pattern. In addition, the charge sharing AND gate evaluates to logic level 1 for the second test vector.
[0007]
The present invention provides various technical advantages. One technical advantage is that the test vectors are designed to automatically test additional electronic circuitry added to the integrated circuit to minimize charge distribution errors. As a result, the state of the charge dispersion correction circuit can be known, and the operation of the integrated circuit is verified. Another technical advantage is that it allows the sequential generation of test vectors without changing the function of the integrated circuit, and thus without recompiling the integrated circuit.
[0008]
Other technical advantages will be readily apparent to one skilled in the art from the accompanying figures, following description, and claims.
[0009]
For a more complete understanding of the present invention and the advantages thereof, reference is made to the following description taken in conjunction with the accompanying drawings. In these drawings, like reference numerals refer to like parts.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 generally shows a logic cell 10. Certain circuits of an integrated circuit may contain many logic cells, which represent a block of electronic circuitry that can be independently tested and verified. The present invention applies to any circuit that exhibits charge distribution behavior, such as domino circuits and other dynamic logic circuits. Logic cell 10 may be any suitable logic circuit including dynamic logic circuits or domino logic circuits.
[0011]
The logic cell 10 includes a power supply 12, a precharge transistor 14, a transistor network 16, an inverter 18, a logic cell output 20, and a charge distribution correction circuit 21. Transistor network 16 includes transistor A22, transistor B24, transistor C26, transistor D28, transistor E30, transistor F32, and ground 34. Transistor network 16 receives input signals 40, which include input A42, input B44, input C46, input D48, input E50, and input F52. The logic cell 10 also includes several points of capacitance called nodes. These nodes hold charge and the logic cell 10 that exists between the pair of transistors includes an O node 60, an X node 62, a Y node 64, and a Z node 66. The O node 60 is an initial storage node and exists between the precharge transistor 14 and the transistors A22 and B24. The X node 62 exists between the transistor B24 and the transistors C26 and D28. The Y node 64 exists between the transistor D28 and the transistor F32. Z node 66 exists between transistor E30 and transistor F32. In the exemplary embodiment of FIG. 1, the logic function is A + B (C + DEF).
[0012]
The charge dispersion correction circuit 21 is an additional electronic circuit added to the logic cell 10 to cope with the behavior of charge dispersion that may appear in the logic cell 10. In one embodiment, the charge distribution correction circuit 21 is a feedback p-channel transistor designed to maintain a precharge level at the O node 60 even if charge distribution behavior appears in the transistor network 16. The charge dispersion correction circuit 21 may be any appropriate charge dispersion correction circuit. Another type of charge dispersion correction circuit is to add a p-channel precharge transistor to each intermediate node, implement dual logic, cross connect the initial storage nodes of the dual logic, and dual rail cross connect Implementing the circuit includes precharging one or more intermediate nodes.
[0013]
As applied to the exemplary embodiment of FIG. 1, charge distribution may exist between the 0 node 60 and any other node connected to the O node 60 through an intervening transistor. For example, O node 60 is initially set to logic level 1 and X node 62 is initially set to logic level 0. If input B is a logic level 1, it connects O node 60 with X node 62, and the initial charge on O node 60 is redistributed to X node 62 even if there is no path to ground 34. Is done. If the voltage level at O-node 60 falls below a threshold that is a logic level 1, then O-node 60 is misinterpreted as a logic level 0. In the exemplary embodiment, a charge distribution correction circuit 21 is added to the logic cell 10 to minimize charge distribution errors. However, if this additional electronic circuit has a defect, such as a stuck open transistor, it will cause inaccurate operation. Conventional test techniques may not evoke the worst case charge distribution behavior and the stack open condition may proceed undetected.
[0014]
FIG. 2 shows a test model 98 that includes the logic cell 10 of FIG. The test model 98 is used by an automatic test pattern generator (ATPG) 124 that generates a first test vector 120 and a second test vector 122. As described in more detail below, the first test vector 120 is configured to cause an optimal discharge of all nodes within the logic cell 10. The second test vector 122 is configured to provide the optimal charge distribution state for the logic cell 10. Preferably, the optimal discharge state and the optimal charge state are a maximum discharge state and a maximum charge state, respectively. However, due to the design of the integrated circuit, these maximum states are not feasible and therefore these optimal states are the maximum obtainable state or the substantially maximum obtainable state.
[0015]
The auxiliary test circuit 100 includes a first AND gate 102, a second AND gate 104, a third AND gate 106, an OR gate 108, and a boundary output 130. The automatic test pattern generator 124 may be any suitable test pattern generator that generates integrated circuit test test vectors, including integrated automatic test pattern generators available on the market. The test model 98 may be data or software stored on a computer readable medium and used as an input to the automatic test pattern generator 124.
[0016]
Test model 98 is provided to an automatic test pattern generator 124 that generates appropriate test vectors to verify the operational integrity of logic cell 10. If the logic cell 10 is part of a large integrated circuit, a modified version of the circuit comprised of the logic cell test model is provided to the automatic test pattern generator 124. The output test vector is input to the integrated circuit input and is configured to provide an appropriate input to the logic cell 10. Therefore, the integrated circuit input is processed by the integrated circuit and configured to generate the appropriate input of logic cell 10.
[0017]
For ease of explanation, the input signal 40 is illustrated separately to provide an input signal to the transistor network 16, an input signal to the first AND gate 102, and an input signal to the second AND gate 104. . However, the input signal 40 is supplied by a common input signal source. An input signal 40 for supplying an input signal to the transistor network 16 is supplied to the first AND gate 102 as it is. The input signal 40 to the source-grounded transistor in the transistor network 16 is inverted and supplied to the second AND gate 104. The input to the remaining transistors in the transistor network 16 is supplied to the second AND gate 104 as it is. In the exemplary embodiment, input A 42, input C 46, and input F 52 are inverted and provided to second AND gate 104. This is because transistor A22, transistor C26, and transistor F32 are all connected to ground 34. The input B44, the input D48, and the input E50 are supplied to the second AND gate 104 as they are. Test model 98 is used to generate first test vector 120 and second test vector 122. This configuration takes care to test using the maximum discharge input and the maximum charge distribution input, respectively. Those inputs can be said to be appropriately modified to handle the maximum obtainable state of the vector.
[0018]
To generate charge distribution test vectors 120 and 122, test model 98 is input to automatic test pattern generator 124, and the falling transition fault at the output of first AND gate 102 is the target for test vector generation. The occurrence of a test for a falling transition fault causes a logic level 1 at the output of the first AND gate 102 during the first test vector 120. In order to obtain a logic level 1 at the output of the first AND gate 102, all input signals 40 are at a logic level 1. Providing a logic level 1 for all input signals 40 leads to all intermediate nodes in logic cell 10 to discharge. This is because all paths to ground 34 are connected. In the exemplary embodiment, O node 60, X node 62, Y node 64, and Z node 66 are all discharged. The second test vector 122 generated by the automatic test pattern generator 124 seeks to produce a logic level 1 at the output of the second AND gate 104. To accomplish this, the input signal 40 for the source-grounded transistor is set to logic level 0 and the remaining input signal 40 is set to logic level 1. The second test vector 122 ensures that a direct path to ground is not available and therefore evokes a worst case charge distribution situation for the logic cell 10. Since the logic cell 10 does not provide a direct path to ground for any signal path, the second test vector 122 ensures observability of all charge distribution and the worst charge distribution for the logic cell 10. Evokes the behavior of. If any element in the additional electronic circuit added to minimize charge distribution fails, the second test vector 122 ensures observability of the failure, thereby testing for the additional electronic circuit. I do.
[0019]
Since the first AND gate 102 and the second AND gate 104 are complementary, the output of the third AND gate 106 should always be at logic level zero. Since the output of the third AND gate 106 is at logic level 0, the output of the OR gate 108 is equal to the logic cell output 20 and provides a boundary output 130 that verifies the results of the first test vector 120 and the second test vector 122. .
[0020]
The generation of the first test vector 120 and the second test vector 122 for the falling transition fault of the output of the first AND gate 102 is based on the second test vector 122 and is one stuck-at fault for the output of the first AND gate 102 at the boundary output 130 ( stack-at-1 fault) test. A stuck-at-0 fault test for the O node 60 can be observed based on the second test vector 122. In preparation for the falling transition fault test by the second test vector 122, the first test vector 120 initializes the logic cell 10.
[0021]
The generated test vector automatically evokes the worst charge distribution behavior, and if charge distribution causes the O-node 60 voltage to change to logic level 0 in response to the second test vector, the effect of charge distribution is the boundary output 130. Observed at The auxiliary test circuit 100 is only added to the test model 98. The auxiliary test circuit 100 is not added to an actual integrated circuit. The auxiliary test circuit is only added to the test model 98 that is provided to the automatic test pattern generator 124 so that the appropriate test vectors 120 and 122 can be generated.
[0022]
FIG. 3 is a flow diagram illustrating a method for generating test vectors according to one embodiment of the invention. The method begins at step 200 where the transistor inputs of all logic cells 10 are ANDed together to produce a first intermediate output. In this exemplary embodiment, input signal 40 is provided to first AND gate 102 to generate a first intermediate output at the output of first AND gate 102.
[0023]
The method proceeds to step 202 where the inverted signal of the input to the transistor whose source is grounded is ANDed with the inputs of the remaining logic cell transistors to produce a second intermediate output. In this exemplary embodiment, transistor A 22, transistor C 26, and transistor F 32 are all connected to ground 34 and are therefore inverted and provided to the second AND gate 104. Further, the transistor B24, the transistor D28, and the transistor E30 are supplied to the second AND gate 104 as they are. The second AND gate 104 generates a second intermediate output at its output.
[0024]
The method proceeds to step 204 where the first intermediate output and the second intermediate output are ANDed together to generate a third intermediate output. In this exemplary embodiment, the output of the first AND gate 102 and the output of the second AND gate 104 are provided to a third AND gate 106 to generate a third intermediate output at the output of the third AND gate 106.
[0025]
The method proceeds to step 206 where the third intermediate output is ORed with the output of the logic cell to generate the main output. In this exemplary embodiment, the output of the third AND gate 106 is provided to an OR gate 108 and the logic cell output 20 is provided to the OR gate 108 to generate a boundary output 130. Steps 200 to 206 represent the auxiliary test circuit 100 of FIG.
[0026]
The method proceeds to step 208 where the test model 98 is transferred to the automatic test pattern generator 124, which generates a first to logic cell transistor input 40 that causes the first intermediate output to be a logic level one. A test vector 120 is determined. In this exemplary embodiment, the first intermediate output is the output of the first AND gate 102.
[0027]
The method proceeds to step 210 where the automatic test pattern generator 124 determines a second test vector 122 for the logic cell transistor input 40 that causes a transition to logic level 0 of the first intermediate output.
[0028]
It is therefore clear that a method of generating a charge distribution test vector that satisfies the above-mentioned advantages such as automatically generating a test vector that tests for charge distribution errors in an integrated circuit is provided according to the present invention. . Having described the invention and its advantages in detail, it will be appreciated that various alternative embodiments, replacement embodiments, and alternative embodiments will be readily apparent to those skilled in the art and the appended claims. Can be made without departing from the spirit and scope of the invention as defined in.
[0029]
The following items are further disclosed with respect to the above description.
[0030]
(1) A method for generating a charge dispersion test vector for a circuit,
Providing an automatic test pattern generator operable to generate a first test vector and a second test vector;
Providing a test model including a logic cell of the circuit and an auxiliary test circuit, wherein the auxiliary test circuit includes a discharge AND gate and a charge distribution AND gate;
Selecting the output of the discharge AND gate as a target for falling transition fault test vector generation by the automatic test pattern generator;
Generating a first test vector for the test model using the automatic test pattern generator, wherein the first test vector provides an input pattern to a discharge node of the logic cell and the discharge AND; Generating a first test vector that evaluates to a logic level 1 with respect to the first test vector;
Generating a second test vector for the test model using the automatic test pattern generator, the second test vector providing an input pattern that evokes a worst-case charge distribution behavior for the circuit; And generating the second test vector, wherein the charge distribution AND gate evaluates to a logic level 1 with respect to the second test pattern.
[0031]
(2) A method for generating a charge dispersion test vector for a circuit,
Providing an automatic test pattern generator operable to generate a first test vector and a second test vector;
Providing a test model including a logic cell of the circuit and an auxiliary test circuit;
Setting the inputs for all sources of the logic cell to logic level 1, wherein the input value provides an input pattern for the automatic test pattern generator; and
Generating a first test vector for the test model using the automatic test pattern generator, the first test vector supplying an input pattern to a discharge node of the logic cell; Said generating step;
Setting the input to the grounded source of the circuit to logic level 0;
Setting the input to the ungrounded source of the circuit to logic level 1;
Generating a second test vector for the test model using the automatic test pattern generator, the second test vector providing an input pattern that evokes a worst-case charge distribution behavior for the circuit; Generating the second test level. The method of generating a charge distribution test vector.
[0032]
(3) The method according to item 2, wherein the logic cell is a domino circuit.
[0033]
(4) The method according to item 2, wherein the logic cell is a dynamic circuit.
[0034]
(5) The method according to item 2, wherein the auxiliary test circuit includes a first AND gate, a second AND gate, a third AND gate, and an OR gate.
[0035]
(6) The method of claim 5, further comprising targeting the output of the first AND gate for falling transition fault test vector generation by the automatic test pattern generator.
[0036]
(7) A circuit charge dispersion test method,
Precharging the output node to logic level 1;
Setting the source input to a value such that a path to ground is provided for the source component associated with the source input;
Discharging the source component of the circuit;
Precharging the output node to logic level 1;
Setting the source input to a value such that the grounded source is at logic level 0 and the other source is at logic level 1;
Evaluating the output node value;
Generating an error condition in response to the output node value evaluation to logic level 0 indicating a charge distribution error.
[0037]
(8) A test vector generation method for a charge dispersion correction circuit of a logic cell,
ANDing all logic cell transistor inputs together to generate a first intermediate output;
ANDing the inverted ground logic cell transistor input with the remaining logic cell transistor input to generate a second intermediate output;
ANDing the first intermediate output and the second intermediate output together to generate a third intermediate output;
ORing the third intermediate output and the output of the logic cell to generate a main output;
Determining a first test vector for the logic cell transistor input that causes the first intermediate output to be at logic level 1;
Determining a second test vector for the logic cell transistor input that causes a transition of the first intermediate output to logic level zero.
[0038]
(9) A logic cell test method,
Applying a first test vector to a logic cell, wherein the first test vector applies the first test vector that operates to optimize a discharge of a node in the logic cell;
Applying a second test vector to the logic cell, wherein the second test vector applies the second test vector that operates to optimize charge distribution between nodes in the logic cell. When,
Measuring a main output from the logic cell to determine a failure state of a charge distribution correction circuit for the logic cell.
[0039]
(10) The method according to item 9, wherein the first test vector operates so as to minimize discharge of a node in the logic cell.
[0040]
(11) The method according to item 9, wherein the second test vector operates to maximize charge distribution between nodes in the logic cell.
[0041]
(12) The method according to item 9,
Generating a first integrated circuit vector;
Applying the first integrated circuit vector to an integrated circuit including the logic cell;
The integrated circuit processes the first integrated circuit vector to generate the first test vector in the logic cell.
Method.
[0042]
(13) The method according to item 12,
Generating a second integrated circuit vector;
Applying the second integrated circuit vector to the integrated circuit including the logic cell;
The integrated circuit processes the second integrated circuit vector to generate the second test vector in the logic cell;
Said method comprising:
A method further comprising measuring a main output from the integrated circuit to determine a fault condition of a charge distribution correction circuit for the cell.
[0043]
(14) A method of generating a charge distribution test vector for a circuit is provided, the method comprising providing an automatic test pattern generator operable to generate a first test vector 120 and a second test vector 122. The method further includes providing a test model 98 including a logic cell of the circuit and an auxiliary test circuit 100, where the auxiliary test circuit 100 includes a discharge AND gate 102 and a charge distribution AND gate 104. The method then includes selecting the output of the discharge AND gate 102 as a target for falling transition fault test vector generation by the automatic test pattern generator 124. The method then includes generating a first test vector 120 for the test model 98 using an automatic test pattern generator 124, where the first test vector 120 is input pattern to the discharge node of the logic cell. Supply. In addition, the discharge AND gate 102 evaluates to a logic level 1 for the first test vector 120. The method then includes generating a second test vector 122 for the test model 98 using an automatic test pattern generator 124, where the second test vector 122 is the worst charge distribution for the logic cell. Supply an input pattern that invokes the behavior of. Further, the charge sharing AND gate 104 evaluates to a logic level 1 for the second test vector 122.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a logic cell with a charge distribution correction circuit that can be tested according to one embodiment of the present invention.
2 is a circuit diagram of a test model for the logic cell of FIG. 1 with an auxiliary test circuit according to one embodiment of the present invention.
FIG. 3 is a flowchart of a test vector generation method according to an embodiment of the present invention.
[Explanation of symbols]
10 logic cells
12 Power supply
14 Precharge transistor
16 transistor network
20 Main output
21 Charge dispersion correction circuit
40 Input signal
60 Initial storage node
62 nodes
64 nodes
66 nodes
98 test model
100 Auxiliary test circuit
102 1st AND gate
104 2nd AND gate
108 Boundary output
120 First test vector
122 Second test vector
124 Automatic test pattern generator
130 Boundary output

Claims (1)

A method for generating a charge dispersion test vector for a circuit, comprising:
Providing an automatic test pattern generator operable to generate a first test vector and a second test vector;
Providing a test model including a logic cell of the circuit and an auxiliary test circuit, wherein the auxiliary test circuit includes a discharge AND gate and a charge distribution AND gate;
Selecting the output of the discharge AND gate as a target for falling transition fault test vector generation by the automatic test pattern generator;
Generating a first test vector for the test model using the automatic test pattern generator, wherein the first test vector provides an input pattern to a discharge node of the logic cell and the discharge AND; Generating a first test vector that evaluates to a logic level 1 with respect to the first test vector;
Generating a second test vector for the test model using the automatic test pattern generator, the second test vector providing an input pattern that evokes a worst-case charge distribution behavior for the circuit; And generating the second test vector, wherein the charge distribution AND gate evaluates to a logic level 1 with respect to the second test pattern.

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