JP2005032404A - Semiconductor memory device, semiconductor integrated circuit device, and portable device - Google Patents

Abstract

To reduce current consumption during standby.
In a standby mode, word drivers 8 and 9 supply a negative voltage Vng to word lines WL0 and WL1. Precharge circuits 6 and 7 turn off P channel MOS transistors PT61-PT63, PT71-PT73, and connect bit line pairs (BL0, / BL0), (BL1, / BL1) from a power supply node receiving power supply voltage VDD. Disconnect electrically. Thereby, the voltage between the source and drain of the access transistor connected to the data holding node at the L level and the access transistor connected to the data holding node at the H level can be lowered to a level at which the problem of the GIDL current does not occur. As a result, current consumption in the standby mode can be reduced without causing a problem of GIDL current.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor memory device, a semiconductor integrated circuit device, and a portable device, and more particularly to a semiconductor memory device, a semiconductor integrated circuit device, and a portable device having a normal mode and a standby mode.

  A semiconductor memory device called an SRAM (Static Random Access Memory) has a feature that it has a flip-flop circuit as a basic structure, and therefore requires no refreshing and is easy to use. In addition, there is a feature that a high-speed operation is possible and an operation margin is large. For this reason, it is often used in memory for portable devices. In recent years, portable devices have also been downsized with the miniaturization of transistors.

  The transistor has a feature that the withstand voltage decreases as the size is reduced. For this reason, when a fine transistor is used, it is necessary to lower the operating voltage of the transistor. Further, in order to operate at a low voltage without impairing the operation speed, the threshold value of the transistor must be lowered. Therefore, a low threshold transistor is used in a small portable device on the premise of battery driving. However, if the threshold value is lowered too much, the transistor cannot be cut off sufficiently and a leakage current flows. This leakage current increases current consumption during standby.

  Small portable devices based on battery drive are required to operate at low voltage and low power. In particular, with mobile phones, one of the decisive factors is how long the standby time can be increased. In order to lengthen the standby time, it is necessary to reduce current consumption during standby, that is, during standby.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device capable of reducing current consumption during standby.

  According to one aspect of the present invention, a semiconductor memory device has a normal mode and a standby mode, and includes a plurality of memory cells, a plurality of word lines, a plurality of bit lines, a plurality of access transistors, and a potential difference supplying unit. With. The plurality of memory cells are arranged in a matrix in rows and columns. The plurality of word lines are arranged corresponding to each row of the plurality of memory cells. The plurality of bit lines are arranged corresponding to each column of the plurality of memory cells. The plurality of access transistors are provided corresponding to each of the plurality of memory cells, connected between a data holding node of the corresponding memory cell and a bit line corresponding to the memory cell, and a word corresponding to the memory cell Receives the voltage of the line at the gate. In the standby mode, the potential difference supply means is an access transistor connected to a data holding node holding data at a logic high level among a plurality of access transistors or an access connected to a data holding node holding data at a logic low level. A negative potential difference is applied between the gate and the source of the transistor.

  Preferably, in the plurality of access transistors, a current of 100 pA / μm or more flows between the drain and the source when the potential difference between the gate and the source is 0V.

  In the semiconductor memory device, in the standby mode, the access transistor connected to the data holding node holding the logic high level data among the plurality of access transistors or connected to the data holding node holding the data of the logic low level. A negative potential difference is applied between the gate and source of the access transistor. As a result, a leakage current that flows from the data holding node that holds the logic high level data to the bit line via the access transistor or a leakage current that flows from the bit line to the data holding node that holds the logic low level data via the access transistor Can be reduced.

  Preferably, the potential difference supplying unit includes a potential holding unit. The potential holding means holds the potentials of the plurality of bit lines at a predetermined positive level in the standby mode.

  In the semiconductor memory device, in the standby mode, the potentials of the plurality of bit lines are higher than the potentials of the plurality of word lines. Therefore, a negative potential difference is applied between the gate and source of the access transistor connected to the data holding node that holds the logic high level data among the plurality of access transistors. As a result, it is possible to reduce the leakage current flowing from the data holding node holding the logic high level data to the bit line via the access transistor. In addition, the problem of the GIDL current can be avoided by holding the potentials of the plurality of bit lines at a level that does not cause the problem of the GIDL current (Gate Induced Drain Leakage current).

  Preferably, the potential holding means includes means for floating a plurality of bit lines in the standby mode.

  In the semiconductor memory device, in the standby mode, the bit line is precharged by a leak current that flows from the data holding node that holds the logic high level data to the bit line via the access transistor. As a result, the potentials of the plurality of bit lines are held at a positive level.

  Preferably, the potential difference supplying unit includes a word line driving unit. The word line driving means supplies a negative voltage to the plurality of word lines in the standby mode.

  In the semiconductor memory device, in the standby mode, the potentials of the plurality of word lines are lower than the potential of the data holding node that holds the logic low level data. Therefore, a negative potential difference is applied between the gate and source of the access transistor connected to the data holding node that holds the logic low level data among the plurality of access transistors. As a result, the leakage current flowing from the bit line to the data holding node holding the logic low level data via the access transistor can be reduced.

  According to another aspect of the present invention, a semiconductor memory device has a normal mode and a standby mode, and includes a plurality of memory cells, a plurality of word lines, a plurality of bit lines, a plurality of access transistors, and a word line. Drive means and precharge means are provided. The plurality of memory cells are arranged in a matrix in rows and columns. The plurality of word lines are arranged corresponding to each row of the plurality of memory cells. The plurality of bit lines are arranged corresponding to each column of the plurality of memory cells. The plurality of access transistors are provided corresponding to each of the plurality of memory cells, connected between a data holding node of the corresponding memory cell and a bit line corresponding to the memory cell, and a word corresponding to the memory cell Receives the voltage of the line at the gate. The word line driving means activates a word line corresponding to a memory cell to be accessed among the plurality of word lines. The precharge means precharges the potentials of the plurality of bit lines to the power supply voltage level for a predetermined period before accessing the memory cell. In the standby mode, the word line driving means supplies a negative voltage to the plurality of word lines, and the precharge means electrically disconnects the plurality of bit lines from the power supply node receiving the power supply voltage.

  In the semiconductor memory device, in the standby mode, the potentials of the plurality of bit lines electrically disconnected from the power supply node are lower than the power supply voltage level because they are not supplied from the power supply node. Usually, it stabilizes at a level in the vicinity of the intermediate potential, which is half the power supply voltage level. As a result, the source-drain voltage of the access transistor connected to the data holding node can be lowered to a level that does not cause a problem of the GIDL current.

  As described above, according to the semiconductor memory device, in the standby mode, a negative voltage is supplied to the plurality of word lines and the plurality of bit lines are electrically disconnected from the power supply node, which causes a problem of the GIDL current. In addition, current consumption in the standby mode can be reduced.

  Preferably, the semiconductor memory device further includes level holding means. The level holding unit holds the potentials of the plurality of bit lines at a predetermined level in the standby mode.

  Preferably, the predetermined level is a level equal to or lower than the intermediate potential.

  In the semiconductor memory device, since the potentials of the plurality of bit lines are held at a predetermined level in the standby mode, the precharge period when returning from the standby mode to the normal mode can be set to a certain period.

  Preferably, the word line driving unit includes a ground voltage supply unit and a negative voltage supply unit. The ground voltage supply means supplies the ground voltage to the plurality of word lines in the standby mode. The negative voltage supply means supplies a negative voltage to the plurality of word lines after the ground voltage is supplied.

  In the semiconductor memory device, since the plurality of word lines are once pulled to the ground voltage level at high speed by the ground voltage supply means, the power consumption of the negative voltage supply means can be reduced.

  According to yet another aspect of the present invention, a semiconductor integrated circuit device includes the semiconductor memory device.

  Preferably, the semiconductor integrated circuit device further includes a logic circuit unit and supply switching means. The supply switching unit supplies the power supply voltage to the logic circuit unit in the normal mode, but does not supply the power supply voltage to the logic circuit unit in the standby mode. The precharge means in the semiconductor memory device further precharges the potentials of the plurality of bit lines to the power supply voltage level in response to switching from the standby mode to the normal mode.

  According to yet another aspect of the present invention, a portable device includes the semiconductor integrated circuit device.

  Preferably, the portable device further includes mode switching signal supply means. The mode signal switching means supplies a mode switching signal for instructing switching between the normal mode / standby mode to the semiconductor integrated circuit.

  In the semiconductor memory device according to one aspect of the present invention, since the potential difference supplying means is provided, the current consumption in the standby mode can be reduced.

  Further, since the potential difference supplying means includes the potential holding means, the leakage current flowing from the data holding node holding the logic high level data to the bit line through the access transistor can be reduced, and further, the problem of the GIDL current can be reduced. It can be avoided.

  In addition, since the potential difference supply unit includes the word line driving unit, it is possible to reduce the leakage current flowing from the bit line to the data holding node that holds the logic low level data via the access transistor.

  In the semiconductor memory device according to another aspect of the present invention, in the standby mode, the word line driving means supplies a negative voltage to the plurality of word lines, and the precharging means electrically connects the plurality of bit lines from the power supply node. Therefore, current consumption in the standby mode can be reduced without causing a problem of GIDL current.

  Further, since the level holding means is provided, the precharge period when returning from the standby mode to the normal mode can be set to a certain period.

  Further, since the word line driving means includes the ground voltage supply means and the negative voltage supply means, the power consumption of the negative voltage supply means can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(First embodiment)
[Configuration of SRAM]
FIG. 1 is a block diagram showing the overall configuration of an SRAM (Static Random Access Memory) according to the first embodiment of the present invention. The SRAM shown in FIG. 1 includes a memory cell array 1, a row decoder 2, a column decoder 3, a column selection circuit 4, an input / output circuit 5, precharge circuits 6 and 7, word drivers 8 and 9, A voltage generation circuit 10 and a NAND circuit 11 are provided.

  Memory cell array 1 includes memory cells MC1-4, word lines WL0, WL1, bit line pairs (BL0, / BL0), (BL1, / BL1), and access transistors NT1a-NT4a, NT1b-NT4b. Memory cells MC1-MC4 are arranged in rows and columns in a matrix. Word line WL0 is arranged corresponding to memory cells MC1 and MC3. Word line WL1 is arranged corresponding to memory cells MC2 and MC4. Bit line pair BL0, / BL0 is arranged corresponding to memory cells MC1, MC2. Bit line pair BL1, / BL1 is arranged corresponding to memory cells MC3, MC4. Access transistors NT1a-NT4a and NT1b-NT4b are low threshold transistors. Specifically, when the potential difference between the gate and the source of the access transistors NT1a-NT4a and NT1b-NT4b is 0V, a current of 100 pA / μm or more flows between the drain and the source. Access transistor NT1a is connected between a data holding node (not shown) of memory cell MC1 and bit line BL0, and receives the voltage of word line WL0 at its gate. Access transistor NT1b is connected between a data holding node (not shown) of memory cell MC1 and bit line / BL0, and receives the voltage of word line WL0 at its gate. Access transistor NT2a is connected between a data holding node (not shown) of memory cell MC2 and bit line BL0, and receives the voltage of word line WL1 at its gate. Access transistor NT2b is connected between a data holding node (not shown) of memory cell MC2 and bit line / BL0, and receives the voltage of word line WL1 at its gate. Access transistor NT3a is connected between a data holding node (not shown) of memory cell MC3 and bit line BL1, and receives the voltage of word line WL0 at its gate. Access transistor NT3b is connected between a data holding node (not shown) of memory cell MC3 and bit line / BL1, and receives the voltage of word line WL0 at its gate. Access transistor NT4a is connected between a data holding node (not shown) of memory cell MC4 and bit line BL1, and receives the voltage of word line WL1 at its gate. Access transistor NT4b is connected between a data holding node (not shown) of memory cell MC4 and bit line / BL1, and receives the voltage of word line WL1 at its gate.

  The NAND circuit 11 outputs a NAND of the mode signal MD and the precharge control signal PR0. The output of the NAND circuit 11 is a precharge signal PR1.

  Row decoder 2 includes an inverter IV21 and NAND circuits ND21 and ND22. Inverter IV21 inverts address signal A1. The NAND circuit ND21 outputs a NAND of the precharge signal PR1 and the address signal A1. The output of the NAND circuit ND21 is the word line selection signal SW0. NAND circuit ND22 outputs a NAND of precharge signal PR1 and the output of inverter IV21. The output of the NAND circuit ND22 is the word line selection signal SW1.

  The negative voltage generation circuit 10 generates a negative voltage Vng.

  The word drivers 8 and 9 constitute word line driving means. The word drivers 8 and 9 supply the power supply voltage VDD, the ground voltage Vss, or the negative voltage Vng to the word lines WL0 and WL1 in response to the word line selection signals SW0 and SW1.

  Column decoder 3 includes an inverter IV31 and AND circuits AD31 and AD32. Inverter IV31 inverts address signal A0. The AND circuit AD31 outputs an AND of the address signal A0 and the access signal R / W. AND circuit AD32 outputs an AND of the output of inverter IV31 and access signal R / W.

  Column selection circuit 4 includes inverters IV41 and IV42 and transfer gates TG41 to TG44. Inverters IV41 and IV42 invert the outputs of AND circuits AD31 and AD32. Transfer gates TG41 and TG42 are connected between bit lines BL0 and / BL and input / output lines IO and / IO. Transfer gates TG41 and TG42 connect / disconnect bit line pair BL0, / BL0 and input / output line pair IO, / IO in response to the output of AND circuit AD31. Transfer gates TG43 and TG44 connect / disconnect bit line pair BL1, / BL1 and input / output line pair IO, / IO in response to the output of AND circuit AD32.

  In response to the access signal R / W, the input / output circuit 5 transmits data read to the input / output line pair IO, / IO to the input / output terminal D or is input to the input / output terminal D from the outside. Data is transmitted to the input / output line pair IO, / IO.

  Precharge circuit 6 includes P channel MOS transistors PT61 to PT63. P channel MOS transistors PT61 and PT62 are connected between a power supply node receiving power supply voltage VDD and bit lines BL0 and / BL0, and turned on / off in response to precharge signal PR1. P channel MOS transistor PT63 is connected between bit line BL0 and bit line / BL0, and is turned on / off in response to precharge signal PR1.

  Precharge circuit 7 includes P channel MOS transistors PT71 to PT73. P channel MOS transistors PT71 and PT72 are connected between a power supply node receiving power supply voltage VDD and bit lines BL1 and / BL1, and turned on / off in response to precharge signal PR1. P-channel MOS transistor PT73 is connected between bit line BL1 and bit line / BL1, and is turned on / off in response to precharge signal PR1.

  FIG. 2 is a diagram showing a specific configuration of memory cells MC1-MC4 shown in FIG. The memory cell MCi shown in FIG. 2 includes P-channel MOS transistors MPia and MPib and N-channel MOS transistors MNia and MNib (i = 1-4).

  P-channel MOS transistor MPia is connected between a power supply node receiving power supply voltage VDD and data holding node Nia. N channel MOS transistor MNia is connected between data holding node Nia and a ground node receiving ground voltage Vss. The gates of P channel MOS transistor MPia and N channel MOS transistor MNia are connected to data holding node Nib. P channel MOS transistor MPib is connected between a power supply node and data holding node Nib. N channel MOS transistor MNib is connected between data holding node Nib and the ground node. The gates of P channel MOS transistor MPib and N channel MOS transistor MNib are connected to data holding node Nia.

  In memory cell MCi configured as described above, a 1-bit complementary data signal is held in data holding nodes Nia and Nib.

  The access transistor NTia (i = 1-4) shown in FIG. 1 is connected between the bit lines BL0 and BL1 and the data holding node Nia, and the access transistor NTib is connected to the bit lines / BL0 and / BL1 and the data Connected to holding node Nib.

  FIG. 3 is a diagram showing a specific configuration of negative voltage generating circuit 10 shown in FIG. The negative voltage generating circuit shown in FIG. 3 includes ring oscillator 101, inverter 102, capacitors C101-C104, and P-channel MOS transistors PT101-PT106.

  Ring oscillator 101 includes an odd number of inverters (not shown) connected in a ring shape, and outputs a signal having a predetermined oscillation frequency. Inverter 102 inverts the signal from ring oscillator 101. Capacitor C101 is connected between the output node of inverter IV102 and node N102. Capacitor C102 is connected between the output node of inverter IV102 and node N104. Capacitor C 103 is connected between the output node of ring oscillator 101 and node 103. Capacitor C104 is connected between the output node of ring oscillator 101 and node N105.

  P-channel MOS transistor PT101 is connected between nodes N101 and N102. P-channel MOS transistor PT102 is connected between node N102 and a ground node receiving ground voltage Vss. P-channel MOS transistor PT103 is connected between nodes N101 and N103. P-channel MOS transistor PT104 is connected between node N103 and the ground node. P-channel MOS transistor PT105 is connected between node N104 and the ground node. P-channel MOS transistor PT106 is connected between node N105 and the ground node. The gates of P-channel MOS transistors PT101 and PT104 are connected to each other and to node N104. The gates of P-channel MOS transistors PT102 and PT103 are connected to each other and to node N105. P channel MOS transistor PT105 has its gate connected to node N105. P channel MOS transistor PT106 has its gate connected to node N104.

  In the negative voltage generating circuit configured as described above, charge pumping is performed in response to the rise / fall of the signal from the ring oscillator 101, and a negative voltage Vng is generated at the node N101.

  The charge supplied to the node N101 when generating the negative voltage Vng is accumulated in the capacitor 104 shown in FIG. Components of the capacitor 104 include a capacitor using a gate oxide film, a capacitance between wirings, a coupling capacitance with a word line, and the like.

  The level (potential) of the negative voltage Vng is clamped to an intermediate level between the built-in voltage level and the ground voltage Vss level by the PN junction diode 103 shown in FIG. This potential can be controlled to a desired level using an existing analog technique such as a combination of a monitor circuit and a reference circuit. It is expected that it is often set in the range of -0.3V to -0.5V depending on the characteristics of GIDL current described later.

  FIG. 5 is a diagram showing a specific configuration of the word drivers 8 and 9 shown in FIG. Since the word drivers 8 and 9 have the same configuration, FIG. 5 shows the configuration of the word driver 8. The word driver shown in FIG. 5 includes inverters IV81-IV92, NAND circuit ND81, level shift circuits LS1, LS2, P channel MOS transistor PT81, and N channel MOS transistors NT81, NT82.

  Inverters IV81-IV85 are connected in series. The word line selection signal SW0 is supplied to the input of the inverter IV81. The output of inverter IV85 is connected to one input of NAND circuit ND81. Inverters IV81-IV85 delay word line select signal SW0 for a predetermined time and supply the delayed signal to one input of NAND circuit ND81. NAND circuit ND81 outputs NAND of the output of inverter IV85 and word line selection signal SW0. Inverter IV86 inverts the output of NAND circuit ND81. Inverter IV87 inverts word line selection signal SW0. Inverter IV88 inverts the output of inverter IV87. Inverters IV89-IV92 are connected in series. A word line selection signal SW0 is supplied to the input of the inverter IV89. Inverters IV89-IV92 output word line select signal SW0 with a predetermined delay.

  Level shift circuit LS1 includes P-channel MOS transistors PT91 and PT92, N-channel MOS transistors NT91 and NT92, and an inverter IV93.

  P-channel MOS transistor PT91 is connected between nodes N80 and N82 receiving power supply voltage VDD, and receives the output of inverter IV86 at its gate. N channel MOS transistor NT91 is connected between node N82 and a node N81 receiving negative voltage Vng. N channel MOS transistor NT91 has its gate connected to node N83. Inverter IV93 inverts the output of inverter IV86. P-channel MOS transistor PT92 is connected between nodes N80 and N83, and receives the output of inverter IV93 at its gate. N channel MOS transistor NT92 is connected between nodes N83 and N81. N channel MOS transistor NT92 has its gate connected to node N82.

  Level shift circuit LS2 includes P channel MOS transistors PT93 and PT94, N channel MOS transistors NT93 and NT94, and an inverter IV94.

  P-channel MOS transistor PT93 is connected between nodes N90 and N92 receiving power supply voltage VDD, and receives the output of inverter IV92 at its gate. N channel MOS transistor NT93 is connected between node N92 and a node N91 receiving negative voltage Vng. N channel MOS transistor NT93 has its gate connected to node N93. Inverter IV94 inverts the output of inverter IV92. P channel MOS transistor PT94 is connected between nodes N90 and N93, and receives the output of inverter IV94 at its gate. N channel MOS transistor NT94 is connected between nodes N93 and N91. N channel MOS transistor NT94 has its gate connected to node N92.

  P-channel MOS transistor PT81 and N-channel MOS transistor NT81 are connected in series between a power supply node receiving power supply voltage VDD and a ground node receiving ground voltage Vss. The gate of P channel MOS transistor PT81 receives the output of inverter IV88. N channel MOS transistor NT81 has its gate receiving voltage Va at node N83. The voltage at interconnection node N84 between P channel MOS transistor PT81 and N channel MOS transistor NT81 is supplied to word line WL0.

  N channel MOS transistor NT82 is connected between interconnection node N84 and a node receiving negative voltage Vng. N channel MOS transistor N82 has its gate receiving a voltage at node N93.

  The operation of the word driver 8 configured as described above will be described with reference to FIG.

  When the word line selection signal SW0 is at the H level (logic high level), the voltage Va at the node N83 is at the negative voltage Vng level, and the voltage Vb at the node N93 is at the power supply voltage VDD level. Therefore, N channel MOS transistor NT81 is off, N channel MOS transistor NT82 is on, and P channel MOS transistor PT81 is off.

  When word line select signal SW0 falls from H level (logic high level) to L level (logic low level), in response to this, P channel MOS transistor PT81 is turned on. Further, the voltage Vb of the node N93 falls to the negative voltage Vng level, and the N-channel MOS transistor NT82 is turned off. Thereby, the voltage of the node N84, that is, the voltage of the word line WL0 changes from the negative voltage Vng level to the power supply voltage VDD level.

  When word line select signal SW0 rises from L level to H level, P channel MOS transistor PT81 is turned off. The voltage Va at the node N83 is a one-shot pulse in response to the rise of the word line selection signal SW0. In response to this one-shot pulse, N-channel MOS transistor NT81 is turned on for a certain period, and node N84 is discharged. That is, the voltage of the word line WL0 changes from the power supply voltage VDD level to the ground voltage Vss level. After voltage Va at node N83 rises, voltage at node N93 becomes power supply voltage VDD level, and N-channel MOS transistor NT82 is turned on. As a result, the voltage of the word line WL0 changes from the ground level Vss to the negative voltage Vng level.

  As described above, in the word driver 8, the N-channel MOS transistor NT81 temporarily pulls out the word line WL0 to the ground voltage Vss level at a high speed, and then turns on the N-channel MOS transistor NT82, whereby the capacitance 104 shown in FIG. The potential is dropped from the ground voltage Vss level to the negative voltage Vng level by charge redistribution using the accumulated charges. As a result, it is possible to achieve unnecessary high-speed pull-down of the word line and not to consume useless charges. That is, the power consumption of the negative voltage generation circuit 10 can be reduced.

[Operation of SRAM]
Next, the operation of the SRAM configured as described above will be described with reference to the overall configuration diagram shown in FIG. 1 and the timing chart shown in FIG. Here, (1) normal mode and (2) standby mode will be described separately.

(1) Normal mode When the mode signal MD is at the H level, the SRAM enters the normal mode. The normal mode refers to a period during which the memory cell MCi is accessed. This SRAM is controlled in the order of access in the first half of one cycle of the precharge signal PR0 and preparation for the next cycle by performing precharge in the second half. The precharge signal PR0 supplied from the outside of the SRAM is a signal synchronized with the external clock signal CLK. The external clock signal CLK is a signal serving as a reference for operation.

  At time t1, the precharge signal PR0 changes from H level to L level. In response to this, the precharge signal PR1 becomes H level. Further, the access signal R / W changes from L level to H level. In order to access memory cell MC1 shown in FIG. 1, both address signals A0 and A1 are at H level. In response to address signal A1 and precharge signal PR1, word line selection signal SW0 attains an L level. In response to this, the word line WL0 is activated by the word driver 8, and the voltage of the word line WL0 becomes the power supply voltage VDD level. Then, N channel MOS transistors NT1a and NT1b are turned on, and data holding nodes N1a and N1b of memory cell MC1 are connected to bit line pair BL0 and / BL0.

  On the other hand, transfer gates TG41 and TG42 are turned on in response to address signal A0 and access signal R / W. Thus, bit line pair BL0, / BL0 and input / output line pair IO, / IO are connected.

  When data is read from the memory cell MC1, complementary data of the data holding nodes Nia and Nib are read to the bit line pair BL0, / BL0 and the data input / output line pair IO, / IO. To D.

  When data is written to the memory cell MC1, the data input / output circuit 5 transmits data supplied to the input / output terminal D to the bit line pair BL, / BL0 via the input / output line pair IO, / IO. As a result, the data signal read from the memory cell MC1 to the bit line pair BL0, / BL0 is rewritten.

  At time t2, precharge signal PR0 becomes H level. In response to this, the precharge signal PR1, the access signal R / W, and the address signals A0 and A1 become L level. Further, the transfer gates TG41 and TG42 are turned off. Further, the word line selection signal SW0 becomes H level, and the voltage of the word line WL0 becomes negative voltage level. In response to this, N channel MOS transistors NT1a and NT1b are turned off.

  In response to precharge signal PR1 becoming L level, P channel MOS transistors PT61-PT63, PT71-PT73 in precharge circuits 6 and 7 are turned on. Thereby, bit lines BL0, / BL0, BL1, / BL1 are connected to the power supply node receiving power supply voltage VDD and precharged to the power supply voltage VDD level. Further, bit line pair BL0, / BL0 is equalized by P channel MOS transistor PT63, and bit line pair BL1, / BL1 is equalized by P channel MOS transistor PT73. Thereby, the preparation for the access at the subsequent time t3-t4 is completed. In the cycle at time t3-t5, access and precharge are performed in the same manner.

(2) Standby mode When the mode signal MD is at L level, the SRAM enters a standby mode. Here, the standby mode refers to a period in which the access frequency to the memory cell is 10% or less of the access frequency in the normal mode.

  At time t5, the mode signal MD changes from the H level to the L level, and the SRAM enters the standby mode.

  When the mode signal MD becomes L level, the precharge signal PR1 becomes H level regardless of the value of the precharge signal PR0. In response to this, the P-channel MOS transistors PT61-PT63, PT71-PT73 in the precharge circuits 6, 7 are turned off. As a result, the bit line pair BL0, / BL0, BL1, / BL1 and the power supply node receiving the power supply voltage VDD are electrically disconnected. That is, the precharge is stopped.

  Further, the word line selection signals SW0 and SW1 are at the H level, and the voltages of the word lines WL0 and WL1 are at the negative voltage Vng level.

  Further, the access signal R / W becomes L level, and the transfer gates TG41 to TG44 are turned off. Thereby, bit line pair BL0, / BL0, BL1, / BL1 and input / output line pair IO, / IO are electrically disconnected.

  Thereafter, the standby mode continues until time t6.

  Normally, in the SRAM, the access operation is performed in the first half of one cycle, and precharge is performed in the second half to prepare for the next cycle. Therefore, when the precharge operation is stopped in the standby mode, it is not possible to directly enter the access operation from that state in the normal mode, that is, in the first half of the cycle. However, in a portable device using an SRAM, there is usually a time of several milliseconds before returning from a standby state (standby mode) to a normal operation state (normal mode) (a power supply stabilization period described later). If a plurality of dummy cycles are inserted between them, there is no problem because the precharge state of all the bit lines can be restored. From such a viewpoint, a dummy cycle is provided between times t6 and t7.

  When such a dummy cycle cannot be provided, the above-described problem can be avoided by converting to memory control in which precharging is performed at the beginning of the cycle and access is performed thereafter. However, since the time until the data is actually output from the access request becomes long, the application range is limited to a low-speed application.

[Reduction effect of current consumption in standby mode]
Next, the effect of reducing current consumption in the standby mode will be described. In order to simplify the description, the memory cells MC1 and MC2 will be described.

  Referring to FIG. 8, in the conventional SRAM, in the standby mode, P channel MOS transistors PT61-PT63 in precharge circuit 6 are turned on to precharge bit line pair BL0, / BL0 to power supply voltage VDD level. ing. Further, an L level (0 V) voltage is supplied to the word lines WL0 and WL1. Therefore, leakage current I1 flows from the power supply node receiving power supply voltage VDD to the ground node in memory cells MC1 and MC2 via access transistors NT1b and NT2a.

  Leakage current I1 flows from the power supply node to the data holding node at the L level of all memory cells. Therefore, in the entire SRAM, a leakage current I1 flows by multiplying the number of memory cells and the leakage current of each access transistor. Although only two memory cells MC1 and MC2 are shown in FIG. 8, for example, if the leakage current of the access transistor is 0.1 μA, a current of 100 mA flows in an SRAM having 1 million memory cells. When used in a small portable device on the premise of battery driving, this value is not an acceptable value as the current consumption value in the standby mode.

  As a method for reducing the leakage current I1, there is a method of applying a negative voltage (for example, −0.3 V) to the gates of the access transistors NT1b and NT2a. According to this method, the leakage current I1 can be reduced because the source (L level data holding nodes N1b, N2a) of the access transistors NT1b, NT2a and the gate are reverse-biased.

  However, with the recent further miniaturization of transistors, new problems have arisen. This is a problem of GIDL current (Gate-Induced-Drain-Leakage-current). As shown in FIG. 9, the GIDL current becomes a problem when the gate voltage Vgs is negative and the drain voltage Vds is near the power supply voltage VDD. In order to avoid this problem, it is effective to reduce the drain voltage Vds.

  When a negative voltage (for example, −0.3 V) is applied to the gates of the access transistors NT1b and NT2a, the negative potential difference between the gate and the drain increases. This is because the bit line pair BL0, / BL0 is precharged to the power supply voltage VDD level. When the power supply voltage VDD is 1.5V, the gate-drain voltage Vgd is Vgd = −0.3−1.5 = −1.8V. Therefore, the GIDL current I2 flows, and the current consumption during standby cannot be reduced.

  In the SRAM according to the first embodiment, in order to solve the problem of the GIDL current, in the standby mode, the P-channel MOS transistors PT61 to PT63 and PT71 to PT73 of the precharge circuits 6 and 7 are turned off, and the bit line The pair BL0, / BL0, BL1, / BL1 is electrically disconnected from the power supply node that receives the power supply voltage VDD.

  The potentials of the bit line pairs BL0, / BL0, BL1, / BL1 electrically isolated from the power supply node are lower than the power supply voltage VDD level because they are not supplied from the power supply node. Normally, it is considered stable at a level near the intermediate potential (1/2 VDD). Hereinafter, a description will be given with reference to FIG. FIG. 10 shows P-channel MOS transistor MP1a, access transistors NT1a and NT2a, and N-channel MOS transistor MN2a shown in FIG. When the precharge is stopped, the voltage VBN of the bit line BL0 is stabilized near the intermediate potential level (about 0.75 V when the power supply voltage VDD is 1.5 V). As a result, the drain voltage Vds2 of the access transistor NT2a is about 0.75V. As a result, current I2b flowing through access transistor NT2a is reduced from I2 to I3 as shown in FIG. Further, the drain voltage Vds1 of the access transistor NT1a connected to the data holding node N1a at the H level is also about 0.75 V, and the current I2b flowing through the access transistor NT1a is also about I3 as shown in FIG.

  Thus, by electrically disconnecting bit line pairs BL0, / BL0, BL1, / BL1 from the power supply node, they are connected to the access transistor connected to the L level data holding node and to the H level data holding node. The source-drain voltage of both of the access transistors can be set to a level that does not cause a problem of GIDL current.

  As described above, according to the first embodiment, in the standby mode, the negative voltage Vng is supplied to the word lines WL0 and WL1, and the bit line pairs BL0, / BL0, BL1, and / BL1 are supplied from the power supply node. Since it is electrically disconnected, current consumption in the standby mode can be reduced without causing a problem of GIDL current.

(Second Embodiment)
The SRAM according to the second embodiment of the present invention further includes a ½ VDD generation circuit 12 and level holding circuits 13 and 14 shown in FIG. 11 in addition to the configuration shown in FIG.

  The 1 / 2VDD generation circuit 12 is a known circuit, and receives the power supply voltage VDD and generates a voltage 1 / 2VDD that is 1/2 level of the power supply voltage VDD.

  Level holding circuit 13 includes P channel MOS transistors PT131 to PT133. P-channel MOS transistor PT131 is connected between a node receiving voltage 1 / 2VDD and node N131, and is turned on / off in response to mode signal MD. P-channel MOS transistor PT132 is connected between a node receiving voltage 1 / 2VDD and node N132, and is turned on / off in response to mode signal MD. Nodes N131 and N132 are connected to bit lines BL0 and / BL0, respectively. P-channel MOS transistor PT133 is connected between nodes N131 and N132, and is turned on / off in response to mode signal MD.

  Level holding circuit 14 includes P-channel MOS transistors PT141 to PT143. P-channel MOS transistor PT141 is connected between a node receiving voltage 1 / 2VDD and node N141, and is turned on / off in response to mode signal MD. P-channel MOS transistor PT142 is connected between a node receiving voltage 1 / 2VDD and node N142, and is turned on / off in response to mode signal MD. Nodes N141 and N142 are connected to bit lines BL1 and / BL1, respectively. P-channel MOS transistor PT143 is connected between nodes N141 and N142, and is turned on / off in response to mode signal MD.

  In this SRAM, in the standby mode, P channel MOS transistors PT131-PT133, PT141-PT143 are turned on, and the voltage levels of bit line pairs BL0, / BL0, BL1, / BL1 are held at 1/2 VDD level. Thereby, in addition to obtaining the same consumption current reduction effect as in the first embodiment, the following effect can be obtained.

  In the first embodiment, the bit line pairs BL0, / BL0, BL1, / BL1 are floating, and their voltage levels are not constant. Therefore, the precharge period (dummy cycle period shown in FIG. 7) when returning from the standby mode to the normal mode cannot be set to a certain period.

  However, according to the second embodiment, the voltage levels of the bit line pairs BL0, / BL0, BL1, / BL1 in the standby mode are held at a constant level (1/2 VDD level). A precharge period (dummy cycle period shown in FIG. 7) when returning to the mode can be set to a certain period.

  Note that although the voltage level of the bit line is held at ½ VDD here, the level held may be lower than the power supply potential VDD. Preferably, it is a level equal to or lower than the intermediate potential 1/2 VDD level.

(Third embodiment)
FIG. 12 is a block diagram showing the configuration of a portable device according to the third embodiment of the present invention. A mobile device 200 shown in FIG. 12 includes a standby microcomputer 210 and a system LSI 220. As an example of such a portable device 200, a mobile phone etc. are mentioned, for example.

  The standby microcomputer 210 is always turned on as a system of the portable device 200. Further, a mode switching signal CTA for instructing switching between the normal mode / standby mode is supplied to the system LSI 220.

  The system LSI 220 includes a control circuit 221, SRAMs 222 and 223, a logic circuit 224, and a switch 225.

  The control circuit 221 supplies the mode signal MD to the SRAM 222 in response to the mode switching signal CTA from the standby microcomputer 210 and supplies the switching signal CTB to the switch 225. The SRAM 222 is the same as the SRAM shown in FIG. 1 and has an effect of reducing current consumption in the standby mode. The power supply voltage VDD is supplied to the SRAM 222 even in the standby mode. The SRAM 223 is not supplied with power in the standby mode in order to cut off the leakage current in the standby mode. Switch 225 is connected between a power supply node receiving power supply voltage VDD and a power supply node of SRAM 223 and logic circuit 224, and is turned on / off in response to switching signal CTB. When the switch 225 is on, the power supply voltage VDD is supplied to the SRAM 223 and the logic circuit 224, and when the switch 225 is off, the power supply voltage VDD is not supplied.

  That is, in the system LSI 220, power is always supplied only to the control circuit 221 and the SRAM 222 that exchange with the standby microcomputer 210.

  Next, the operation of the mobile device configured as described above will be described with reference to FIG.

  When shifting from the normal mode to the standby mode (for example, when waiting for a mobile phone), the standby microcomputer 210 supplies the system LSI 220 with a mode switching signal CTA for switching to the standby mode. This corresponds to the mode switching signal CTA falling from the H level to the L level at time t11.

  In response to mode switching signal CTA, control circuit 221 causes mode signal MD and switching signal CTB to fall to the L level. In response to the L level switching signal CTB, the switch 225 is turned off. As a result, power supply to the SRAM 223 and the logic circuit 224 is cut off. On the other hand, in response to the L level mode signal MD, the SRAM 222 stops the precharge operation.

  When returning from the standby mode to the normal mode, the mode switching signal CTA becomes H level (t12). In response to this, the switching signal CTB becomes H level and the switch 225 is turned on. On the other hand, the mode signal MD becomes H level, and the SRAM 222 starts precharging. Since the bit line of the SRAM 222 is electrically disconnected from the power supply node during the standby mode, the potential is lowered. Therefore, it is expected that a large peak current will flow if all the bit lines are precharged at the same time when precharging is started. For this reason, it is desirable to perform precharge stepwise with a time difference. For example, it is desirable to divide a plurality of bit lines into several groups and perform precharging with a time difference for each group. It is expected that it takes several milliseconds for the voltage Vint to stabilize to the power supply voltage VDD level after the switch 225 is turned on (t12-t13). As described above, there is time until the system LSI 220 stably starts to operate. Therefore, there is sufficient time for the SRAM 222 to return to the precharge state (dummy cycle shown in FIG. 7), and the above-described stepwise precharge is possible.

(Fourth embodiment)
FIG. 14 is a block diagram showing the overall structure of the SRAM according to the fourth embodiment of the present invention. The SRAM shown in FIG. 14 includes a memory cell array 1, a row decoder 2, a column decoder 3, a column selection circuit 4, an input / output circuit 5, precharge circuits 6 and 7, word drivers 1401 and 1402, NAND Circuit 11. The word drivers 1401 and 1402 supply the power supply voltage VDD to the word lines WL0 and WL1 in response to the H level word line selection signals SW0 and SW1, and the ground voltage in response to the L level word line selection signals SW0 and SW1. Vss (= 0V) is supplied to the word lines WL0 and WL1.

  Next, the effect of reducing current consumption in the standby mode of the SRAM shown in FIG. 14 will be described. In order to simplify the description, the memory cells MC1 and MC2 will be described.

  In the standby mode, the ground voltage Vss (= 0V) is applied to the word lines WL0 and WL1, and the access transistors NT1a, NT1b, NT2a and NT2b are turned off. Further, transfer gates TG41-TG44 and P-channel MOS transistors PT61-PT63, PT71-PT73 are turned off, and bit lines BL0, / BL0, BL1, / BL1 are floated. However, as shown in FIG. 15, P channel MOS transistors MP1a and MP2b from the power supply nodes of the memory cells MC1 and MC2-data holding nodes N1a and N2b for holding H level data-access transistors NT1a and NT2b-bit lines BL0, / BL0 − Access transistors NT2a and NT1b − Data holding nodes N2a and N1b for holding L level data − N channel MOS transistors MN2a and MN1b − Leakage current Ix flows through the path to the ground node. This is because the threshold values of the access transistors NT1a, NT1b, NT2a, NT2b are low. The potential of the bit lines BL0 and / BL0 is held at a positive level higher than the ground voltage Vss (= 0V) and lower than the power supply voltage VDD by the leak current Ix. This gives a negative potential difference between the gate and source of access transistors NT1a and NT2b. Therefore, although leakage current Ix flows through access transistors NT1a and NT2b, the amount of current is reduced by the negative potential difference between the gate and the source.

  As described above, the potentials of the bit lines BL0 and / BL0 are held at a positive level by the leakage current Ix. However, the level is not always constant. There is also a possibility that the level is close to the level of the ground voltage Vss (= 0V) (for example, 0.1V). At this time, the gate-source voltage Vgs of the access transistors NT1a and NT2b is negative (−0.1V), and the drain-source voltage Vds is at a level near the power supply voltage VDD (here, VDD = 1.5V). Become. Therefore, a GIDL current (≈I11) flows as shown in FIG. In order to avoid this GIDL current problem, level holding circuits 13 and 14 and a ½ VDD generation circuit 12 as shown in FIG. 12 may be provided. Then, as shown in FIG. 17, the potentials (VNB) of bit lines BL0 and / BL0 in the standby mode become 1 / 2VDD level, and the drain-source voltage Vds of access transistors NT1a and NT2b becomes approximately 1 / 2VDD level. (0.75V). As a result, as shown in FIG. 16, the level of the GIDL current is reduced to a level I12 where there is no problem. The bit lines BL0 and / BL0 may be precharged to the 1 / 2VDD level by the precharge circuits 6 and 7 without providing the level holding circuits 13 and 14 and the 1 / 2VDD generation circuit 12. Further, the level to be held is not limited to the ½ VDD level. What is necessary is just to hold | maintain to the level which does not produce the problem of GIDL current in the range larger than the ground voltage Vss level (0V) and smaller than the power supply voltage VDD level.

1 is a block diagram showing an overall configuration of an SRAM according to a first embodiment of the present invention. FIG. 2 is a diagram showing a configuration of a memory cell shown in FIG. 1. It is a figure which shows the structure of the negative voltage generation circuit shown in FIG. It is a figure which shows the structure of the capacity | capacitance added to the node which receives a negative voltage, and a diode. It is a figure which shows the structure of the word driver shown in FIG. 6 is a timing chart for explaining the operation of the word driver shown in FIG. 5. 3 is a timing chart for explaining the operation of the SRAM shown in FIG. 1. It is a figure for demonstrating the reduction effect of the consumption current in standby mode. It is a figure for demonstrating a GIDL electric current. It is a figure for demonstrating the reduction effect of the consumption current in standby mode. It is a figure which shows the structure of SRAM by 2nd Embodiment of this invention. It is a block diagram which shows the structure of the portable apparatus by 3rd Embodiment of this invention. 13 is a timing chart for explaining the operation of the mobile device shown in FIG. 12. It is a block diagram which shows the whole structure of SRAM by 4th Embodiment of this invention. It is a figure which shows the leak current which flows at the time of standby mode. It is a figure for demonstrating a GIDL electric current. It is a figure for demonstrating the reduction effect of the consumption current in standby mode.

Explanation of symbols

MC1-MC4 Memory cells WL0, WL1 Word lines BL0, / BL0, BL1, / BL1 Bit lines NT1a-NT4a, NT1b-NT4b Access transistors N1a-N4a, N1b-N4b Data holding nodes 6, 7 Precharge circuits 8, 9, 1401, 1402 Word driver 10 Negative voltage generation circuit 13, 14 Level holding circuit 200 Portable device 210 Standby microcomputer 220 System LSI
222,223 SRAM
224 logic circuit 225 switch

Claims (1)

A semiconductor memory device having a normal mode and a standby mode,
A plurality of memory cells arranged in a matrix in rows and columns;
A plurality of word lines arranged corresponding to each row of the plurality of memory cells;
A plurality of bit lines arranged corresponding to each column of the plurality of memory cells;
Provided corresponding to each of the plurality of memory cells, connected between a data holding node of the corresponding memory cell and a bit line corresponding to the memory cell, and gates a voltage of a word line corresponding to the memory cell. A plurality of access transistors
In the standby mode, the gate of the access transistor connected to the data holding node holding the logic high level data among the plurality of access transistors or the gate of the access transistor connected to the data holding node holding the logic low level data− A semiconductor memory device comprising: a potential difference supplying unit that applies a negative potential difference between the sources.

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