JP2005026273A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device structure capable of reducing the resistance of a gate electrode and a source / drain region while utilizing the advantages of both a metal replacement technique and a salicide technique, and a method for manufacturing the same.
A gate electrode formed of a replacement metal formed on a semiconductor substrate, a silicide film formed on an upper surface of the gate electrode, an impurity diffusion region formed in the semiconductor substrate, And a silicide film 30 formed on the impurity diffusion region 28. As a result, the resistance of the gate electrode and the source / drain region is reduced, and a high-speed and low-power transistor can be manufactured.
[Selection] FIG.

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly provides a semiconductor device having a gate electrode made of a replacement metal and a manufacturing method thereof.
[0002]
[Prior art]
Design rules (lines / spaces) have become stricter as semiconductor devices become more highly integrated and larger in capacity. Along with this, the width of the wiring layer is reduced, and the diameter of the via hole for forming the contact plug connecting the upper and lower wiring layers is reduced. For this reason, it is necessary to use a material having a lower resistance as a material for forming the wiring layer and the contact plug.
[0003]
Up to now, as a gate electrode material of a MIS transistor, polycrystalline silicon has been used as a material that can form a source / drain diffusion layer in a self-aligned manner, that is, a material that can withstand an activation heat treatment for forming the source / drain diffusion layer. Has been widely used. However, since polycrystalline silicon has a specific resistance that is about two orders of magnitude higher than that of metal, it has been desired to reduce the resistance of the gate electrode.
[0004]
In recent years, a technique for replacing polycrystalline silicon with aluminum has been proposed, and there is a movement to apply this technique to a manufacturing process of a semiconductor device. The inventor of the present application forms a MIS transistor having a gate electrode made of polycrystalline silicon, and then performs aluminum replacement using the above-described technology for replacing the polycrystalline silicon with aluminum, thereby forming an MIS transistor having a gate electrode made of aluminum. A forming method is proposed in Patent Document 1. Further, the metal replacement technique of the gate electrode is also described in Patent Document 2, Non-Patent Document 1, and the like.
[0005]
Next, a conventional method for manufacturing a semiconductor device in which a gate electrode is formed using a metal replacement technique will be described with reference to FIGS.
[0006]
First, a P well 104 is formed by ion implantation in the element region of the silicon substrate 100 defined by the element isolation film 102.
[0007]
Next, a dummy gate electrode 106 made of a polycrystalline silicon film and source / drain diffusion layers formed in the silicon substrate 100 on both sides of the gate electrode 106 are formed on the element region in the same manner as in a normal MOS transistor forming method. And a MOS transistor having.
[0008]
Next, after a silicon oxide film was deposited on the silicon substrate 100 on which the MOS transistor was formed by the CVD method, the silicon oxide film was planarized by the CMP method until the surface of the dummy gate electrode 106 was exposed, and the surface was planarized. An interlayer insulating film 110 made of a silicon oxide film is formed (FIG. 29A).
[0009]
Next, an aluminum film 112 and a titanium film 114 are deposited on the interlayer insulating film 110 by sputtering (FIG. 29B).
[0010]
Next, heat treatment is performed at about 400 ° C. in a nitrogen atmosphere. By this heat treatment, a reaction proceeds from the interface between the dummy gate electrode 106 and the aluminum film 112, and silicon atoms constituting the dummy gate electrode 106 diffuse in the direction of the aluminum film 112 and aluminum atoms constituting the aluminum film 112. Diffuses in the direction of the dummy gate electrode 106. Thereby, the polycrystalline silicon constituting the dummy gate electrode 106 is replaced with aluminum. Thus, the gate electrode 116 made of aluminum is formed (FIG. 29C).
[0011]
Next, the aluminum film 112 and the titanium film 114 on the interlayer insulating film 110 are removed by, eg, CMP (FIG. 30A).
[0012]
Next, for example, a silicon oxide film is deposited by, eg, CVD, and an interlayer insulating film 118 made of the silicon oxide film is formed.
[0013]
Next, the interlayer insulating films 118 and 110 are patterned by photolithography and dry etching, and contact holes 120 reaching the source / drain diffusion layers 108 are formed.
[0014]
Next, after depositing a barrier metal film and a tungsten film, for example, by sputtering, these films are planarized by CMP until the surface of the interlayer insulating film 118 is exposed, and contact plugs 122 embedded in the contact holes 120 are formed.
[0015]
Next, after depositing a conductive film, the conductive film is patterned by photolithography and dry etching to form a wiring layer 124 connected to the source / drain diffusion layer 108 via the contact plug 122 (FIG. 30B). .
[0016]
Thus, a semiconductor device in which the gate electrode is replaced with a metal material has been manufactured.
[0017]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-097535
[Patent Document 2]
JP 2001-274379 A
[Non-Patent Document 1]
International Electron Devices Meeting 96, p. 946-94
[0018]
[Problems to be solved by the invention]
On the other hand, as a technique for simultaneously reducing the resistance of the gate electrode and the source / drain region, a salicide (self-aligned silicide) technique for selectively forming a silicide film on the gate electrode and the source / drain diffusion layer is known. It has been.
[0019]
With the metal replacement technique, the resistance of the gate electrode can be reduced more than that achieved by the salicide technique, but the resistance of the source / drain region cannot be reduced. For this reason, it is desirable to use salicide technology in combination with metal replacement technology to replace the gate electrode with metal and to silicide the source / drain regions. However, studies on combining metal replacement technology with salicide technology have been made in the past. There wasn't.
[0020]
An object of the present invention is to provide a structure of a semiconductor device and a method of manufacturing the same that can reduce the resistance of a gate electrode and a source / drain region while taking advantage of both the metal replacement technique and the salicide technique.
[0021]
[Means for Solving the Problems]
The object is to provide a gate electrode made of a replacement metal formed on a semiconductor substrate, a first silicide film formed on an upper surface of the gate electrode, an impurity diffusion region formed in the semiconductor substrate, This is achieved by a semiconductor device having a second silicide film formed on the impurity diffusion region.
[0022]
Further, the object is to provide a gate electrode made of a replacement metal formed on a semiconductor substrate, a cap insulating film formed on an upper surface of the gate electrode, an impurity diffusion region formed in the semiconductor substrate, This is also achieved by a semiconductor device having a second silicide film formed on the impurity diffusion region.
[0023]
Further, the object is to provide a gate electrode made of a replacement metal formed on a semiconductor substrate, an impurity diffusion region formed in the semiconductor substrate, a silicide film formed on the impurity diffusion region, and the semiconductor substrate. A semiconductor comprising: an interlayer insulating film formed on the interlayer insulating film and having a height substantially equal to the gate electrode; and a wiring layer formed on the interlayer insulating film and electrically connected to the gate electrode It is also achieved by the device.
[0024]
Further, the object is to form a dummy gate electrode made of a material that can be replaced with metal on a semiconductor substrate, and to the dummy gate electrode in the semiconductor substrate on both sides of the dummy gate electrode. Forming an impurity diffusion region by self-alignment; forming a silicide film by self-alignment on the dummy gate electrode and the impurity diffusion region; and forming an interlayer insulating film on the semiconductor substrate; Forming the opening reaching the silicide film on the dummy gate electrode in the interlayer insulating film, forming a metal film on the interlayer insulating film, and performing heat treatment, thereby performing the dummy gate A step of replacing the material constituting the electrode with a metal material constituting the metal film, and forming a gate electrode made of the metal material. Also achieved by a manufacturing method of that semiconductor device.
[0025]
Further, the object is to form, on the semiconductor substrate, a dummy gate electrode made of a material to be replaced that can be replaced with metal and having an upper surface covered with a cap insulating film, and the semiconductor substrate on both sides of the dummy gate electrode. A step of forming an impurity diffusion region by self-alignment with respect to the dummy gate electrode, a step of forming a silicide film by self-alignment on the impurity diffusion region, and an interlayer insulating film on the semiconductor substrate. A step of forming, a step of forming an opening reaching the dummy gate electrode in the interlayer insulating film and the cap insulating film, a step of forming a metal film on the interlayer insulating film, and a heat treatment. , Replacing the material to be replaced constituting the dummy gate electrode with a metal material constituting the metal film, and forming a gate electrode made of the metal material. Also achieved by a method of manufacturing a semiconductor device according to claim and.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
The semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention will be described with reference to FIGS.
[0027]
1 is a plan view showing the structure of the semiconductor device according to the present embodiment, FIG. 2 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 3 to 11 show a method for manufacturing the semiconductor device according to the present embodiment. It is process sectional drawing.
[0028]
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIGS. 2A is a schematic cross-sectional view taken along the line AA ′ in FIG. 1, and FIG. 2B is a cross-sectional view taken along the line BB ′ in FIG.
[0029]
An element isolation film 12 that defines an element region is formed on the silicon substrate 10. A P well 14 is formed in the silicon substrate 10 in the N-type transistor formation region. On the element region, a gate electrode 48 made of aluminum as a replacement metal is formed via a gate insulating film 16. A cap insulating film 20 is formed on the upper surface of the gate electrode 48. A source / drain diffusion layer 28 is formed in the silicon substrate 10 on both sides of the gate electrode 48 so as to be self-aligned with the gate electrode 48. A silicide film 30 is formed on the source / drain diffusion layer 28. Thus, an N-type transistor having the gate electrode 48 and the source / drain diffusion layer 28 is formed.
[0030]
An interlayer insulating film 32 is formed on the silicon substrate 10 on which the transistors are formed. The interlayer insulating film 32 includes a contact plug 40 electrically connected to the source / drain diffusion layer 28 through the silicide film 30 and a contact plug 50 made of aluminum which is a replacement metal connected to the gate electrode 48. Embedded.
[0031]
On the interlayer insulating film 32 in which the contact plugs 40 and 50 are embedded, a wiring layer 56 electrically connected to the source / drain diffusion layer 28 via the contact plug 40 and the silicide film 30 and the contact plug 50 are interposed. Thus, a wiring layer 58 electrically connected to the gate electrode 48 is formed.
[0032]
As described above, the semiconductor device according to the present embodiment is mainly characterized in that the gate electrode 48 of the transistor is made of aluminum as a replacement metal, and the silicide film 30 is formed on the source / drain diffusion layer 28. There is.
[0033]
When the gate electrode 48 of the N-type transistor is made of aluminum, the resistance of the gate wiring can be reduced and the speed of the transistor can be increased. The work function of aluminum is also suitable for the gate electrode of an N-type transistor. Further, by forming the silicide film 30 on the source / drain diffusion layer 28, the resistance of the diffusion layer can be lowered, and the speed of the transistor can be further increased.
[0034]
Here, strictly speaking, the material constituting the gate electrode 48 is a conductor mainly containing aluminum. In the present invention, the gate electrode 48 is formed using a technique of replacing polycrystalline silicon with aluminum. For this reason, the gate electrode 48 contains silicon corresponding to the temperature of the heat treatment at the time of replacement. That is, the concentration of silicon in aluminum converges to a state where the atomic structure of the material is kept stable at the heat treatment temperature (on the line between the phases in the phase diagram), for example, heat treatment at about 350 ° C. When performing heat treatment at about 400 ° C., about 0.3% silicon is included, and when performing heat treatment at about 450 ° C., about 0.5% silicon is included. % Of silicon is contained, and when heat treatment at about 500 ° C. is performed, about 0.7% of silicon is contained. However, in this specification, for convenience, a conductor formed by replacing polycrystalline silicon with aluminum is also referred to as “aluminum”.
[0035]
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 3 to 7 are process cross-sectional views along the line AA 'in FIG. 1, and FIGS. 8 to 11 are process cross-sectional views along the line BB' in FIG.
[0036]
First, the element isolation film 12 that defines the element region is formed on the p-type silicon substrate 10 by, for example, the STI method.
[0037]
Next, a P well 14 is formed in the N-type transistor formation region by ion implantation (FIGS. 3A and 8A). In addition to the well formation, ion implantation for threshold control and ion implantation for forming an impurity region for punch-through prevention may be performed.
[0038]
Next, the surface of the silicon substrate 10 is thermally oxidized by a thermal oxidation method to form a gate insulating film 16 made of, for example, a silicon oxide film on the element region (FIGS. 3B and 8B). The gate insulating film 16 may be formed of a silicon oxynitride film, an alumina film, a high dielectric constant film, or other insulating films.
[0039]
Next, a polycrystalline silicon film of, eg, a 100 nm-thickness is deposited on the entire surface by, eg, CVD. Silicon is a material to be replaced that can be replaced by a metal material such as aluminum. Instead of the polycrystalline silicon film, other materials that can be replaced with aluminum, such as germanium (Ge) film, SiGe film, SiGeC film, carbon (C) film, and silicon carbide (SiC) film, Co _x Si _y Film, Ni _x Si _y Film, Ti _x Si _y Membrane, Pt _x Si _y A silicide film such as a film may be formed.
[0040]
Next, a silicon oxide film of, eg, a 50 nm-thickness is deposited on the polysilicon film by, eg, CVD to form a cap insulating film 20 made of the silicon oxide film.
[0041]
Next, the cap insulating film 20 and the polycrystalline silicon film are patterned by photolithography and dry etching to form a dummy gate electrode 22 made of a polycrystalline silicon film and having the upper surface covered with the cap insulating film 20.
[0042]
Next, arsenic (As) ions, for example, are ion-implanted using the dummy gate electrode 22 as a mask, and a low concentration impurity region having an LDD structure or an extension region having an extension source / drain structure is formed in the silicon substrate 10 on both sides of the dummy gate electrode 22. An impurity diffusion region 24 is formed (FIGS. 3C and 8C).
[0043]
Next, after depositing, for example, a 100 nm-thickness silicon oxide film by the CVD method, the silicon oxide film is etched back, and a sidewall insulating film 26 made of a silicon oxide film is formed on the sidewall portion of the dummy gate electrode 22.
[0044]
Next, for example, arsenic (As) ions are ion-implanted using the dummy gate electrode 22 and the sidewall insulating film 26 as a mask, and high-concentration sources / drains are formed in the silicon substrate 10 on both sides of the dummy gate electrode 22 and the sidewall insulating film 26. Impurity regions are formed.
[0045]
Next, a predetermined heat treatment is performed to activate the implanted impurities, and N-type source / drain diffusion layers 28 having an LDD structure or an extension S / D structure are formed in the silicon substrate 10 on both sides of the dummy gate electrode 22 (FIG. 4 (a), FIG. 9 (a)).
[0046]
Next, a silicide film 30 is selectively formed on the source / drain diffusion layer 28 by a salicide process (FIG. 4B). For example, a metal film such as cobalt or titanium is deposited on the entire surface, reacted with a silicon exposed portion by a heat treatment to form a silicide film, and then the unreacted metal film is removed, whereby the source / drain diffusion layer 28 is formed. A silicide film 30 is formed.
[0047]
In the semiconductor device according to the present embodiment, the cap insulating film 20 is provided on the dummy gate electrode 22 so that no silicide film is formed on the dummy gate electrode 22. In a general salicide process, a polysilicon film constituting a gate electrode and a metal film are reacted to form a silicide film on the polysilicon film. In this case, since a part of the polysilicon film is consumed, the thickness of the polysilicon film becomes thinner than before the silicidation reaction. However, when the polysilicon film is replaced with aluminum as in the present invention, the thinning of the polysilicon film before the replacement leads to a significant increase in gate resistance. Therefore, in the semiconductor device according to the present embodiment, the upper surface of the dummy gate electrode 22 is previously covered with the cap insulating film 20 to prevent the dummy gate electrode 22 from undergoing a silicidation reaction.
[0048]
Next, for example, a silicon oxide film having a film thickness of, for example, 500 nm is deposited by, for example, a CVD method, and then this silicon oxide film is planarized by, for example, a CMP (Chemical Mechanical Polishing) method to form a silicon oxide having a planarized surface. An interlayer insulating film 32 made of a film is formed (FIGS. 5A and 9B).
[0049]
Note that the silicon oxide film may be planarized until the surface of the cap insulating film 20 is exposed, and the interlayer insulating film 32 having a height substantially equal to the cap insulating film 20 may be formed. In this case, the cap insulating film 20 may be removed so that the silicide film 30 on the dummy gate electrode 22 is removed in a fifth embodiment to be described later.
[0050]
Next, a contact hole 34 reaching the silicide film 30 is formed in the interlayer insulating film 32 by photolithography and dry etching.
[0051]
Next, a titanium film (Ti) having a thickness of, for example, 5 nm and a titanium nitride (TiN) film having a thickness of, for example, 20 nm are deposited by CVD, for example, to form a barrier metal 36 having a TiN / Ti structure.
[0052]
Next, a tungsten film 38 of, eg, a 300 nm-thickness is formed on the barrier metal 36 by, eg, sputtering.
[0053]
Next, the tungsten film 38 and the barrier metal 36 are removed flatly by CMP, for example, until the surface of the interlayer insulating film 32 is exposed, and the barrier metal 36 and the tungsten film 38 are selectively left in the contact holes 34. Thus, the contact plug 40 made of the barrier metal 36 and the tungsten film 38 is formed in the contact hole 34 (FIG. 5B).
[0054]
Next, a contact hole 42 reaching the dummy gate electrode 22 is formed in the interlayer insulating film 32 and the cap insulating film 20 by photolithography and dry etching (FIG. 9C).
[0055]
Next, on the interlayer insulating film 32 in which the contact plug 40 is embedded and the contact hole 42 reaching the dummy gate electrode 22 is formed, for example, by sputtering, an aluminum (Al) film 44 having a film thickness of 400 nm, for example, A 200 nm titanium film 46 is deposited (FIGS. 6A and 10A). As a result, the dummy gate electrode 22 and the aluminum film 44 are in direct contact within the contact hole 42.
[0056]
Next, heat treatment is performed in a nitrogen atmosphere at 300 to 500 ° C., for example, 400 ° C., for example, for 30 minutes. By this heat treatment, a reaction proceeds from the interface between the dummy gate electrode 22 and the aluminum film 44, and silicon atoms constituting the dummy gate electrode 22 diffuse in the direction of the aluminum film 44 and aluminum atoms constituting the aluminum film 44. Diffuses in the direction of the dummy gate electrode 22. When a dummy gate electrode made of a polycrystalline silicon film having a gate length of 0.1 μm and a height of 0.15 μm is replaced with aluminum, if a heat treatment is performed in a nitrogen atmosphere at 400 ° C. for 30 minutes, the gate width direction is about 10 μm. The region can be replaced with aluminum. It is desirable that the heat treatment time be appropriately selected according to the shape of the gate electrode, the heat treatment temperature, and the like.
[0057]
Thereby, the dummy gate electrode 22 and the aluminum film 44 are replaced with an aluminum film containing silicon having a concentration corresponding to the heat treatment temperature. Excess silicon is sucked into the titanium film 46. Thus, the gate electrode 48 made of aluminum is formed (FIGS. 6B and 10B).
[0058]
As described above, the heat treatment for aluminum replacement is desirably performed in the range of 300 to 500 ° C. This is because the reaction between polycrystalline silicon and aluminum does not occur when the temperature is lower than 300 ° C., and the reaction between aluminum and the interlayer insulating film occurs when the temperature is higher than 500 ° C.
[0059]
Next, the aluminum film 44 and the titanium film 46 on the interlayer insulating film 32 are removed by, eg, CMP (FIGS. 7A and 11A). At this time, the contact plug 50 made of aluminum integrally formed with the gate electrode 48 remains in the contact hole 42.
[0060]
Next, for example, a titanium nitride film 52 and an aluminum film 54 are deposited on the interlayer insulating film 32 by, eg, sputtering.
[0061]
Next, the titanium nitride film 52 and the aluminum film 54 are patterned by photolithography and dry etching, and the titanium nitride film 52 and the aluminum film 54 are electrically connected to the source / drain diffusion layer 28 via the contact plug 40. The wiring layer 56 and the wiring layer 58 electrically connected to the gate electrode 48 through the contact plug 50 are formed (FIGS. 7B and 11B).
[0062]
As described above, according to the present embodiment, the cap film is provided on the dummy gate electrode, and the silicide film is selectively formed on the source / drain diffusion layer. Therefore, the gate electrode due to the consumption of the polysilicon film accompanying silicidation. Can be prevented from increasing in resistance. Therefore, a silicide film can be formed on the source / drain diffusion layer without impairing the merit of the replacement metal gate, and the speed of the transistor can be increased.
[0063]
[Second Embodiment]
A semiconductor device and a manufacturing method thereof according to the second embodiment of the present invention will be described with reference to FIGS. Components similar to those of the semiconductor device and the manufacturing method thereof according to the first embodiment shown in FIGS. 1 to 11 are denoted by the same reference numerals, and description thereof is omitted or simplified.
[0064]
FIG. 12 is a schematic sectional view showing the structure of the semiconductor device according to the present embodiment. FIGS. 13 to 15 are process sectional views showing the method for manufacturing the semiconductor device according to the present embodiment.
[0065]
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. 12A is a schematic cross-sectional view taken along the line AA ′ in FIG. 1, and FIG. 12B is a schematic cross-sectional view taken along the line BB ′ in FIG.
[0066]
An element isolation film 12 that defines an element region is formed on the silicon substrate 10. A P well 14 is formed in the silicon substrate 10 in the N-type transistor formation region. On the element region, a gate electrode 48 made of aluminum as a replacement metal is formed via a gate insulating film 16. A source / drain diffusion layer 28 is formed in the silicon substrate 10 on both sides of the gate electrode 48 so as to be self-aligned with the gate electrode 48. A silicide film 30 is formed on the gate electrode 48 and the source / drain diffusion layer 28. Thus, an N-type transistor having the gate electrode 48 and the source / drain diffusion layer 28 is formed.
[0067]
An interlayer insulating film 32 is formed on the silicon substrate 10 on which the transistors are formed. The interlayer insulating film 32 includes a contact plug 40 electrically connected to the source / drain diffusion layer 28 through the silicide film 30 and a contact plug 50 made of aluminum which is a replacement metal connected to the gate electrode 48. Embedded.
[0068]
On the interlayer insulating film 32 in which the contact plugs 40 and 50 are embedded, a wiring layer 56 electrically connected to the source / drain diffusion layer 28 via the contact plug 40 and the silicide film 30 and the contact plug 50 are interposed. Thus, a wiring layer 58 electrically connected to the gate electrode 48 is formed.
As described above, the basic structure of the semiconductor device according to the present embodiment is the same as that of the semiconductor device according to the first embodiment shown in FIGS. The main feature of the present embodiment is that a silicide film 30 is formed on the gate electrode 48 instead of the cap insulating film 20, and the contact plug 50 penetrates the silicide film 50 on the gate electrode 48 and directly becomes the gate electrode 48. Be connected.
[0069]
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 13 is a process cross-sectional view along the line AA ′ in FIG. 1, and FIGS. 14 and 15 are process cross-sectional views along the line BB ′ in FIG.
[0070]
First, for example, the element isolation film 12, the P well 14, the gate insulating film 16 and the like are formed on the silicon substrate 10 in the same manner as in the semiconductor device manufacturing method according to the first embodiment.
[0071]
Next, a polycrystalline silicon film of, eg, a 100 nm-thickness is deposited on the entire surface by, eg, CVD.
[0072]
Next, the polycrystalline silicon film is patterned by photolithography and dry etching to form a dummy gate electrode 22 made of the polycrystalline silicon film.
[0073]
In the semiconductor device manufacturing method according to the present embodiment, it is not necessary to form the cap insulating film 20 on the dummy gate electrode 22 as in the semiconductor device manufacturing method according to the first embodiment. Therefore, the manufacturing process can be simplified by not performing the process of forming the cap insulating film 20.
[0074]
Next, for example, arsenic ions are ion-implanted using the dummy gate electrode 22 as a mask, and an impurity that becomes a low concentration impurity region of the LDD structure or an extension region of the extension source / drain structure is formed in the silicon substrate 10 on both sides of the dummy gate electrode 22. A diffusion region 24 is formed (FIG. 13A).
[0075]
Next, sidewall insulating films 26 and source / drain diffusion layers 28 are formed in the same manner as in the semiconductor device manufacturing method according to the first embodiment, for example (FIG. 13B).
[0076]
Next, a silicide film 30 is selectively formed on the dummy gate electrode 22 and the source / drain diffusion layer 28 by a salicide process. For example, a metal film such as cobalt or titanium is deposited on the entire surface, reacted with a silicon exposed portion by a heat treatment to form a silicide film, and then the unreacted metal film is removed, whereby the dummy gate electrode 22 and the source / source A silicide film 30 is formed on the drain diffusion layer 28 (FIGS. 13C and 14A).
[0077]
Next, after depositing a silicon oxide film of, eg, a 500 nm-thickness by, eg, CVD, the silicon oxide film is planarized by, eg, CMP, and an interlayer insulating film 32 made of a silicon oxide film having a planarized surface is formed (see FIG. FIG. 14 (b)).
[0078]
Next, a contact plug 40 electrically connected to the source / drain diffusion layer 28 is formed in the interlayer insulating film 32 in the same manner as in the semiconductor device manufacturing method according to the first embodiment, for example.
[0079]
Next, a contact hole 42 reaching the dummy gate electrode 22 is formed in the silicide film 30 on the interlayer insulating film 32 and the dummy gate electrode 22 by photolithography and dry etching (FIG. 14C).
[0080]
Next, an aluminum film 44 having a thickness of, for example, 400 nm and titanium having a thickness of, for example, 200 nm are formed on the interlayer insulating film 32 in which the contact plug 40 is embedded and the contact hole 42 reaching the dummy gate electrode 22 is formed by, for example, sputtering. A film 46 is deposited (FIG. 15A). As a result, the dummy gate electrode 22 and the aluminum film 44 are in direct contact within the contact hole 42.
[0081]
Next, heat treatment is performed in a nitrogen atmosphere at 300 to 500 ° C., for example, 400 ° C., for 30 minutes, for example, and the dummy gate electrode 22 and the aluminum film 44 are replaced with an aluminum film containing silicon having a concentration corresponding to the heat treatment temperature. Thus, the gate electrode 48 made of aluminum is formed (FIG. 15B).
[0082]
In the method for manufacturing the semiconductor device according to the present embodiment, the silicide film 30 in the contact hole 42 is removed. If the silicide film 30 remains in the contact hole 42, the silicide film 30 is interposed between the dummy gate electrode 22 and the aluminum film 44. For this reason, depending on the silicide material, there is a concern that the aluminum substitution reaction may be hindered. Therefore, in the method of manufacturing the semiconductor device according to the present embodiment, the silicide film 30 in the contact hole 42 is removed so that the aluminum replacement reaction is performed smoothly.
[0083]
When the silicide film 30 is formed on the dummy gate electrode 22 as in the method of manufacturing the semiconductor device according to the present embodiment, there is a concern that a part of the dummy gate electrode 22 is consumed and the resistance value of the gate electrode 48 increases. The However, aluminum is a material having a very low specific resistance, and the resistance value does not increase much. In addition, an increase in the resistance value of the gate electrode 48 can be suppressed by appropriately setting the film thickness of the dummy gate electrode 22 and the silicide film 30.
[0084]
Thereafter, the contact plug 50 and the wiring layers 56 and 58 are formed in the same manner as in the semiconductor device manufacturing method according to the first embodiment, for example.
[0085]
Thus, according to the present embodiment, after the silicide film on the dummy gate electrode is removed and the metal material and the dummy gate electrode are in direct contact with each other, the dummy gate electrode is replaced with metal. It is possible to prevent the substitution reaction from being inhibited by the silicide film formed thereon. Thereby, even when the salicide process is applied, the metal replacement of the gate electrode can be performed smoothly.
[0086]
[Third Embodiment]
A semiconductor device and a manufacturing method thereof according to the third embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first and second embodiments shown in FIGS. 1 to 15 are denoted by the same reference numerals, and description thereof is omitted or simplified.
[0087]
FIG. 16 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 17 and 18 are process cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment.
[0088]
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. 16A is a schematic cross-sectional view taken along the line AA 'in FIG. 1, and FIG. 16B is a schematic cross-sectional view taken along the line BB' in FIG.
[0089]
An element isolation film 12 that defines an element region is formed on the silicon substrate 10. A P well 14 is formed in the silicon substrate 10 in the N-type transistor formation region. On the element region, a gate electrode 48 made of aluminum as a replacement metal is formed via a gate insulating film 16. A source / drain diffusion layer 28 is formed in the silicon substrate 10 on both sides of the gate electrode 48 so as to be self-aligned with the gate electrode 48. A silicide film 30 is formed on the gate electrode 48 and the source / drain diffusion layer 28. Thus, an N-type transistor having the gate electrode 48 and the source / drain diffusion layer 28 is formed.
[0090]
An interlayer insulating film 32 is formed on the silicon substrate 10 on which the transistors are formed. The interlayer insulating film 32 includes a contact plug 40 electrically connected to the source / drain diffusion layer 28 through the silicide film 30, and aluminum as a replacement metal connected to the gate electrode 48 through the silicide film 30. A contact plug 50 is embedded.
[0091]
On the interlayer insulating film 32 in which the contact plugs 40 and 50 are embedded, a wiring layer 56 electrically connected to the source / drain diffusion layer 28 via the contact plug 40 and the silicide film 30, and the contact plug 50 and the silicide A wiring layer 58 that is electrically connected to the gate electrode 48 through the film 30 is formed.
[0092]
As described above, the basic structure of the semiconductor device according to the present embodiment is the same as that of the semiconductor device according to the second embodiment shown in FIG. The main feature of the semiconductor device according to the present embodiment is that a contact plug 50 electrically connected to the gate electrode 48 is formed via a silicide film 30 formed on the gate electrode 48.
[0093]
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 17 and 18 are process cross-sectional views along the line BB 'in FIG.
[0094]
First, for example, in the same way as in the method of manufacturing the semiconductor device according to the second embodiment, an element isolation film 12, a dummy gate electrode 22, a source / drain diffusion layer 28, a silicide film 30, an interlayer insulating film 32, Contact plugs 40 and the like are formed.
[0095]
Next, a contact hole 42 reaching the silicide film 30 on the dummy gate electrode 22 is formed in the interlayer insulating film 32 by photolithography and dry etching (FIG. 17A).
[0096]
Next, an aluminum film 44 having a thickness of, for example, 400 nm is formed on the interlayer insulating film 32 in which the contact plug 40 is buried and the contact hole 42 reaching the silicide film 30 on the dummy gate electrode 22 is formed, for example, by sputtering. A titanium film 46 having a thickness of 200 nm is deposited. Thereby, in the contact hole 42, the aluminum film 44 is formed on the dummy gate electrode 22 via the silicide film 30 (FIG. 17B).
[0097]
Next, heat treatment is performed in a nitrogen atmosphere at 300 to 500 ° C., for example, 400 ° C., for 30 minutes, for example, and the dummy gate electrode 22 and the aluminum film 44 are replaced with an aluminum film containing silicon having a concentration corresponding to the heat treatment temperature. Thus, the gate electrode 48 made of aluminum is formed (FIG. 18A).
[0098]
In the second embodiment, the silicide film 30 in the contact hole 42 is removed because there is a concern that the silicide film 30 inhibits the aluminum substitution reaction. However, as a result of studies by the inventors of the present application, when at least a titanium silicide or cobalt silicide film is used as the silicide film 30, the silicide film 30 does not hinder the reaction of aluminum substitution, and the dummy gate electrode 22 is formed. It was confirmed that the aluminum can be easily replaced. Therefore, when such a silicide material is used, it is not always necessary to remove the silicide film 30 in the contact hole 42 as in the semiconductor device according to the present embodiment.
[0099]
Further, when the inventors of the present application have studied, even when aluminum replacement is performed in a state where the silicide film 30 is formed on the dummy gate electrode 22, the replacement metal reacts with the silicide to cause a silicide spike. It has been confirmed that there is no phenomenon that greatly affects the reliability, such as the formation of the gate electrode or the diffusion of the silicide to the gate insulating film region.
[0100]
Thereafter, the contact plug 50 and the wiring layers 56 and 58 are formed in the same manner as in the semiconductor device manufacturing method according to the first embodiment, for example (FIG. 18B).
[0101]
As described above, according to the present embodiment, the dummy gate electrode is replaced with metal through the silicide film on the dummy gate electrode, so that the salicide process and the metal replacement process are used in combination without complicating the manufacturing process. be able to. As a result, it is possible to reduce the resistance of both the gate electrode and the source / drain diffusion layer without increasing the manufacturing cost.
[0102]
[Fourth Embodiment]
A semiconductor device and a manufacturing method thereof according to the fourth embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first to third embodiments shown in FIGS. 1 to 18 are denoted by the same reference numerals, and description thereof is omitted or simplified.
[0103]
FIG. 19 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment. FIGS. 20 to 23 are process cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment.
[0104]
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 19A is a schematic cross-sectional view along the line AA ′ in FIG. 1, and FIG. 19B is a schematic cross-sectional view along the line BB ′ in FIG.
[0105]
An element isolation film 12 that defines an element region is formed on the silicon substrate 10. A P well 14 is formed in the silicon substrate 10 in the N-type transistor formation region. On the element region, a gate electrode 48 made of aluminum as a replacement metal is formed via a gate insulating film 16. A source / drain diffusion layer 28 is formed in the silicon substrate 10 on both sides of the gate electrode 48 so as to be self-aligned with the gate electrode 48. A silicide film 30 is formed on the gate electrode 48 and the source / drain diffusion layer 28. Thus, an N-type transistor having the gate electrode 48 and the source / drain diffusion layer 28 is formed.
[0106]
An interlayer insulating film 32 having a height substantially equal to the silicide film 30 formed on the gate electrode 48 is formed on the silicon substrate 10 on which the transistors are formed. A contact plug 40 electrically connected to the source / drain diffusion layer 28 is embedded in the interlayer insulating film 32.
[0107]
On the interlayer insulating film 32 in which the contact plug 40 is buried, a wiring layer 56 electrically connected to the source / drain diffusion layer 28 via the contact plug 40 and the silicide film 30 and a gate via the silicide film 30 are provided. A wiring layer 58 electrically connected to the electrode 48 is formed.
[0108]
As described above, the basic structure of the semiconductor device according to the present embodiment is the same as that of the semiconductor device according to the second embodiment shown in FIG. The main feature of the semiconductor device according to the present embodiment is that the height of the interlayer insulating film 32 is substantially equal to the height of the silicide film 30 formed on the gate electrode 48.
[0109]
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 20 and 21 are process cross-sectional views along the line AA ′ in FIG. 1, and FIGS. 22 and 23 are process cross-sectional views along the line BB ′ in FIG.
[0110]
First, the element isolation film 12, the dummy gate electrode 22, the source / drain diffusion layer 28, the silicide film 30 and the like are formed on the silicon substrate 10 in the same manner as in the semiconductor device manufacturing method according to the second embodiment, for example.
[0111]
Next, after depositing a silicon oxide film of, eg, a 500 nm-thickness by, eg, CVD, the silicon oxide film is planarized by, eg, CMP, until the silicide film 30 is exposed, and is formed on the dummy gate electrode 22 from the silicon oxide film. An interlayer insulating film 32 having a height substantially equal to the silicide film 30 thus formed is formed (FIGS. 20A and 22A).
[0112]
In the method of manufacturing the semiconductor device according to the present embodiment, the interlayer insulating film 32 is removed until the silicide film 30 is exposed, so that it is not necessary to form the contact hole 42 reaching the silicide film 30. Therefore, the lithography process and the dry etching process for forming the contact hole 42 can be reduced.
[0113]
Next, for example, in the same manner as the semiconductor device manufacturing method according to the first embodiment, a contact plug 40 electrically connected to the source / drain diffusion layer 28 is formed in the interlayer insulating film 32 (FIG. 20B). ).
[0114]
Next, an aluminum film 44 having a film thickness of 400 nm and a titanium film 46 having a film thickness of 200 nm, for example, are deposited on the silicide film 30 and the interlayer insulating film 32 formed on the dummy gate electrode 22 by, for example, sputtering. . Thus, the aluminum film 44 is formed on the dummy gate electrode 22 via the silicide film 30 (FIGS. 20C and 22B).
[0115]
Next, heat treatment is performed in a nitrogen atmosphere at 300 to 500 ° C., for example, 400 ° C. for 5 minutes, for example, and the dummy gate electrode 22 and the aluminum film 44 are replaced with an aluminum film containing silicon having a concentration corresponding to the heat treatment temperature. Thus, the gate electrode 48 made of aluminum is formed (FIGS. 21A and 22C).
[0116]
At this time, since the aluminum film 44 is formed on the entire surface of the dummy gate electrode 22 via the silicide film 30, the aluminum replacement proceeds simultaneously on the entire surface of the dummy gate electrode 22. Therefore, even when the gate width of the dummy gate electrode 22 is long, the heat treatment for aluminum replacement can be performed in a short time.
[0117]
Next, the aluminum film 44 and the titanium film 46 on the interlayer insulating film 32 are removed by, eg, CMP (FIGS. 21B and 23A).
[0118]
Next, for example, in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment, a wiring layer 56 electrically connected to the source / drain diffusion layer 28 via the contact plug 40 on the interlayer insulating film 32, and a silicide A wiring layer 58 electrically connected to the gate electrode 48 through the film 30 is formed (FIGS. 21C and 23B).
[0119]
As described above, according to the present embodiment, the dummy gate electrode is replaced with metal from above, so that the dummy gate electrode can be replaced with metal in a short time even when the gate width is long.
[0120]
[Fifth Embodiment]
A semiconductor device and a manufacturing method thereof according to the fifth embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first to fourth embodiments shown in FIGS. 1 to 23 are denoted by the same reference numerals, and description thereof is omitted or simplified.
[0121]
FIG. 24 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 25 to 28 are process cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment.
[0122]
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. 24A is a schematic cross-sectional view taken along the line AA ′ in FIG. 1, and FIG. 24B is a schematic cross-sectional view taken along the line BB ′ in FIG.
[0123]
An element isolation film 12 that defines an element region is formed on the silicon substrate 10. A P well 14 is formed in the silicon substrate 10 in the N-type transistor formation region. On the element region, a gate electrode 48 made of aluminum as a replacement metal is formed via a gate insulating film 16. A source / drain diffusion layer 28 is formed in the silicon substrate 10 on both sides of the gate electrode 48 so as to be self-aligned with the gate electrode 48. A silicide film 30 is formed on the source / drain diffusion layer 28. Thus, an N-type transistor having the gate electrode 48 and the source / drain diffusion layer 28 is formed.
[0124]
On the silicon substrate 10 on which the transistor is formed, an interlayer insulating film 32 having a height substantially equal to the gate electrode 48 is formed. A contact plug 40 electrically connected to the source / drain diffusion layer 28 via the silicide film 30 is embedded in the interlayer insulating film 32.
[0125]
On the interlayer insulating film 32 in which the contact plug 40 is embedded, a wiring layer 56 electrically connected to the source / drain diffusion layer 28 via the contact plug 40 and the silicide film 30 and a gate electrode 48 are electrically connected. A connected wiring layer 58 is formed.
[0126]
As described above, the semiconductor device according to the present embodiment is characterized in that the gate electrode 48 of the transistor is made of aluminum and the silicide film 30 is formed on the source / drain diffusion layer 28. The interlayer insulating film 32 is also characterized by being substantially equal to the gate electrode 48 made of aluminum.
[0127]
The height of the gate electrode 48 in the semiconductor device according to the present embodiment corresponds to the height obtained by adding the thickness of the silicide film 30 to the height of the gate electrode 48 of the semiconductor device according to the fourth embodiment. Therefore, there are more metal regions of the gate electrode and lower resistance than in the semiconductor device according to the fourth embodiment. Therefore, the speed of the transistor can be further increased.
[0128]
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 25 and 26 are process cross-sectional views along the line AA ′ in FIG. 1, and FIGS. 27 and 28 are process cross-sectional views along the line BB ′ in FIG.
[0129]
First, for example, in the same manner as the semiconductor device manufacturing method according to the fourth embodiment, an element isolation film 12, a dummy gate electrode 22, a source / drain diffusion layer 28, a silicide film 30, an interlayer insulating film 32, Contact plugs 40 and the like are formed.
[0130]
Next, the silicide film 30 on the dummy gate electrode 22 is selectively removed by wet etching, for example (FIGS. 25A and 27A).
[0131]
Next, an aluminum film 44 having a thickness of, for example, 400 nm and a titanium film 46 having a thickness of, for example, 200 nm are deposited on the dummy gate electrode 22 and the interlayer insulating film 32 by, eg, sputtering. Thus, the aluminum film 44 is formed directly on the dummy gate electrode 22 (FIGS. 25B and 27B).
[0132]
Next, heat treatment is performed in a nitrogen atmosphere at 300 to 500 ° C., for example, 400 ° C. for 5 minutes, for example, and the dummy gate electrode 22 and the aluminum film 44 are replaced with an aluminum film containing silicon having a concentration corresponding to the heat treatment temperature. Thus, the gate electrode 48 made of aluminum is formed (FIGS. 25C and 27C).
[0133]
Next, the aluminum film 44 and the titanium film 46 on the interlayer insulating film 32 are removed by, eg, CMP. At this time, the aluminum film 44 also remains in the region where the silicide film 30 is removed. Therefore, the gate electrode 48 has a height substantially equal to that of the interlayer insulating film 32 (FIGS. 26A and 28A).
[0134]
Next, for example, in the same way as in the semiconductor device manufacturing method according to the first embodiment, a wiring layer 56 electrically connected to the source / drain diffusion layer 28 via the contact plug 40 on the interlayer insulating film 32, and a gate A wiring layer 58 electrically connected to the electrode 48 is formed (FIGS. 26B and 28B).
[0135]
As described above, according to the present embodiment, the dummy gate electrode is replaced with metal from above, so that the dummy gate electrode can be replaced with metal in a short time even when the gate width is long. Further, since the silicide film does not remain on the gate electrode and can be made of a replacement metal material including the region where the silicide film is formed, the resistance of the gate electrode can be greatly reduced. Accordingly, the speed of the transistor can be increased.
[0136]
[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications can be made.
[0137]
For example, in the above embodiment, the gate electrode before aluminum replacement is formed of a polycrystalline silicon film, but it is not always necessary to be polycrystalline silicon in a state immediately after the formation. A single crystal silicon film or an amorphous silicon film may be formed instead of the polycrystalline silicon film. Even in the case of an amorphous silicon film, it is crystallized during the impurity activation heat treatment, so that it is in a polycrystalline state when aluminum substitution is performed. Further, instead of the polycrystalline silicon film, other materials that can be replaced with aluminum, such as germanium film, SiGe film, SiGeC film, carbon film, silicon carbide film, Co _x Si _y Film, Ni _x Si _y Film, Ti _x Si _y Membrane, Pt _x Si _y A silicide film such as a film can also be used.
[0138]
In the above embodiment, when the polycrystalline silicon film is replaced with aluminum, the titanium film is formed on the aluminum film serving as the aluminum source. However, the titanium film is not necessarily provided. Although the titanium film has an action of sucking out excess silicon and has an effect of promoting aluminum substitution, it is possible to perform aluminum substitution without a titanium film.
[0139]
Further, not only titanium but also a material capable of sucking out the dummy gate electrode can be used instead of the titanium film. For example, a material such as ruthenium (Ru), cobalt (Co), nickel (Ni), or platinum (Pt) that can easily form silicide by reacting with silicon can be used.
[0140]
Moreover, in the said embodiment, although the polycrystalline silicon was substituted with aluminum, it is also possible to substitute with another metal material. For example, instead of aluminum, metals such as copper, silver, ruthenium, platinum, palladium, and gold may be used, and polycrystalline silicon may be replaced with these metals. Note that the replacement metal formed by replacing the material to be replaced with a metal material includes a slight amount of the material to be replaced in the film. For example, when silicon is replaced with aluminum, the replacement aluminum contains about 0.2 to 0.7% of silicon depending on the heat treatment temperature. In other words, by measuring the concentration of the material to be replaced in the film, it is possible to infer whether or not it is a replacement metal formed by replacing the material to be replaced with a metal material.
[0141]
In the above embodiment, the sputtering method is used to deposit the aluminum film 44 and the titanium film 46, but other film forming methods such as a CVD method may be used. As semiconductor devices become highly integrated, the contact hole 42 is also miniaturized, and it becomes difficult to form aluminum in the deep part of the hole. In such a case, it is desirable to apply a deposition method with excellent coverage such as a CVD method.
[0142]
In the above embodiment, after the plug 40 is formed, the dummy gate electrode 22 is replaced with metal, and the gate electrode 48 made of the replacement metal is formed. However, the plug 40 is not necessarily formed in this order. For example, the plug 40 may be formed after the gate electrode 48 is formed.
[0143]
As described above in detail, the characteristics of the present invention are summarized as follows.
[0144]
(Appendix 1) A gate electrode made of a replacement metal formed on a semiconductor substrate;
A first silicide film formed on an upper surface of the gate electrode;
An impurity diffusion region formed in the semiconductor substrate;
A second silicide film formed on the impurity diffusion region;
A semiconductor device comprising:
[0145]
(Appendix 2) In the semiconductor device according to Appendix 1,
An interlayer insulating film formed on the semiconductor substrate;
A wiring layer formed on the interlayer insulating film and electrically connected to the gate electrode through an opening formed in the interlayer insulating film;
A semiconductor device.
[0146]
(Appendix 3) In the semiconductor device described in Appendix 2,
The wiring layer is electrically connected to the gate electrode through a contact plug made of the replacement metal formed in the opening.
A semiconductor device.
[0147]
(Appendix 4) In the semiconductor device described in Appendix 2,
The interlayer insulating film has a height substantially equal to the upper surface of the first silicide film.
A semiconductor device.
[0148]
(Appendix 5) In the semiconductor device described in Appendix 3,
The contact plug is connected to the gate electrode through the first silicide film.
A semiconductor device.
[0149]
(Appendix 6) A gate electrode made of a replacement metal formed on a semiconductor substrate;
A cap insulating film formed on the upper surface of the gate electrode;
An impurity diffusion region formed in the semiconductor substrate;
A second silicide film formed on the impurity diffusion region;
A semiconductor device comprising:
[0150]
(Appendix 7) In the semiconductor device described in Appendix 6,
An interlayer insulating film formed on the semiconductor substrate;
A wiring layer formed on the interlayer insulating film and electrically connected to the gate electrode through an opening formed in the interlayer insulating film;
A semiconductor device.
[0151]
(Supplementary note 8) In the semiconductor device according to supplementary note 7,
The wiring layer is electrically connected to the gate electrode through a contact plug made of the replacement metal formed in the opening.
A semiconductor device.
[0152]
(Supplementary Note 9) A gate electrode made of a replacement metal formed on a semiconductor substrate;
An impurity diffusion region formed in the semiconductor substrate;
A silicide film formed on the impurity diffusion region;
An interlayer insulating film formed on the semiconductor substrate and having a height substantially equal to the gate electrode;
A wiring layer formed on the interlayer insulating film and electrically connected to the gate electrode;
A semiconductor device comprising:
[0153]
(Appendix 10) In the semiconductor device according to any one of appendices 1 to 9,
The impurity diffusion region is formed in a self-aligned manner with respect to the gate electrode.
A semiconductor device.
[0154]
(Additional remark 11) The process of forming the dummy gate electrode which consists of a substituted material which can be substituted by a metal on a semiconductor substrate,
Forming an impurity diffusion region in the semiconductor substrate on both sides of the dummy gate electrode in a self-aligned manner with respect to the dummy gate electrode;
Forming a silicide film on the dummy gate electrode and the impurity diffusion region by self-alignment;
Forming an interlayer insulating film on the semiconductor substrate;
Forming an opening reaching the silicide film on the dummy gate electrode in the interlayer insulating film;
Forming a metal film on the interlayer insulating film;
A step of replacing the material constituting the dummy gate electrode with a metal material constituting the metal film by performing a heat treatment to form a gate electrode made of the metal material;
A method for manufacturing a semiconductor device, comprising:
[0155]
(Additional remark 12) In the manufacturing method of the semiconductor device of Additional remark 11,
After the step of forming the gate electrode, the metal film on the interlayer insulating film is removed to form a contact plug made of the metal material embedded in the opening and connected to the gate electrode. It further has a process
A method for manufacturing a semiconductor device.
[0156]
(Additional remark 13) In the manufacturing method of the semiconductor device of Additional remark 11,
In the step of forming the opening, the opening is formed by planarizing the interlayer insulating film until the silicide film on the dummy gate electrode is exposed.
A method for manufacturing a semiconductor device.
[0157]
(Appendix 14) In the method for manufacturing a semiconductor device according to any one of appendices 11 to 13,
After the step of forming the opening, the method further includes a step of removing the silicide film in the opening.
A method for manufacturing a semiconductor device.
[0158]
(Additional remark 15) The process which forms the dummy gate electrode which consists of a to-be-substituted material which can be substituted by a metal on the semiconductor substrate, and the upper surface was covered with the cap insulating film,
Forming an impurity diffusion region in the semiconductor substrate on both sides of the dummy gate electrode in a self-aligned manner with respect to the dummy gate electrode;
Forming a silicide film in a self-aligned manner on the impurity diffusion region;
Forming an interlayer insulating film on the semiconductor substrate;
Forming an opening reaching the dummy gate electrode in the interlayer insulating film and the cap insulating film;
Forming a metal film on the interlayer insulating film;
A step of replacing the material constituting the dummy gate electrode with a metal material constituting the metal film by performing a heat treatment to form a gate electrode made of the metal material;
A method for manufacturing a semiconductor device, comprising:
[0159]
(Supplementary Note 16) In the method for manufacturing a semiconductor device according to Supplementary Note 15,
After the step of forming the gate electrode, the metal film on the interlayer insulating film is removed to form a contact plug made of the metal material embedded in the opening and connected to the gate electrode. It further has a process
A method for manufacturing a semiconductor device.
[0160]
(Supplementary Note 17) In the method for manufacturing a semiconductor device according to Supplementary Note 15,
In the step of forming the opening, after planarizing the interlayer insulating film until the cap insulating film is exposed, the opening is formed by removing the cap insulating film.
A method for manufacturing a semiconductor device.
[0161]
【The invention's effect】
As described above, according to the present invention, the silicide film can be formed on the source / drain region and the gate electrode can be replaced with the metal material, so that the resistance of both the source / drain region and the gate electrode can be reduced. be able to. Thereby, a high-speed, low-power transistor can be manufactured.
[Brief description of the drawings]
FIG. 1 is a plan view showing a structure of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention.
FIG. 3 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 4 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 5 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 6 is a process cross-sectional view (No. 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 7 is a process sectional view (No. 5) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 8 is a process cross-sectional view (No. 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 9 is a process cross-sectional view (No. 7) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 10 is a process cross-sectional view (No. 8) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 11 is a process cross-sectional view (No. 9) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 12 is a schematic cross-sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention.
FIG. 13 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment of the invention;
FIG. 14 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention;
FIG. 15 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment of the invention;
FIG. 16 is a schematic cross-sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention.
FIG. 17 is a process cross-sectional view (No. 1) illustrating the method for manufacturing the semiconductor device according to the third embodiment of the invention;
FIG. 18 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention;
FIG. 19 is a schematic sectional view showing the structure of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 20 is a process cross-sectional view (No. 1) illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the invention;
FIG. 21 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention;
FIG. 22 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention;
FIG. 23 is a process cross-sectional view (No. 4) illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the invention;
FIG. 24 is a schematic sectional view showing the structure of a semiconductor device according to a fifth embodiment of the present invention.
FIG. 25 is a process cross-sectional view (No. 1) illustrating the method for manufacturing the semiconductor device according to the fifth embodiment of the invention;
FIG. 26 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention;
FIG. 27 is a process cross-sectional view (No. 3) illustrating the method for manufacturing the semiconductor device according to the fifth embodiment of the invention;
FIG. 28 is a process cross-sectional view (No. 4) illustrating the method for manufacturing the semiconductor device according to the fifth embodiment of the invention;
FIG. 29 is a process cross-sectional view (part 1) illustrating the conventional method for manufacturing a semiconductor device;
FIG. 30 is a process cross-sectional view (part 2) illustrating the conventional method for manufacturing a semiconductor device;
[Explanation of symbols]
10 ... Silicon substrate
12 ... element isolation film
14 ... P well
16 ... Gate insulating film
20 ... Cap insulating film
22 ... Dummy gate electrode
24 ... Impurity diffusion region
26. Side wall insulating film
28 ... Source / drain diffusion layer
30. Silicide film
32. Interlayer insulating film
34, 42 ... contact hole
36 ... Barrier metal
38 ... Tungsten film
40, 50 ... contact plug
44 ... Aluminum film
46 ... Titanium film
48 ... Gate electrode
52. Titanium nitride film
54. Aluminum film
56, 58 ... wiring layer
100: Silicon substrate
102: Element isolation film
104 ... P well
106: Dummy gate electrode
108: Source / drain diffusion layer
110, 118 ... interlayer insulating film
112 ... Aluminum film
114 ... Titanium film
116: Gate electrode
120 ... Contact hole
122 ... contact plug
124: Wiring layer

Claims (5)

A gate electrode made of a replacement metal formed on a semiconductor substrate;
A first silicide film formed on an upper surface of the gate electrode;
An impurity diffusion region formed in the semiconductor substrate;
And a second silicide film formed on the impurity diffusion region. A gate electrode made of a replacement metal formed on a semiconductor substrate;
A cap insulating film formed on the upper surface of the gate electrode;
An impurity diffusion region formed in the semiconductor substrate;
And a second silicide film formed on the impurity diffusion region. A gate electrode made of a replacement metal formed on a semiconductor substrate;
An impurity diffusion region formed in the semiconductor substrate;
A silicide film formed on the impurity diffusion region;
An interlayer insulating film formed on the semiconductor substrate and having a height substantially equal to the gate electrode;
And a wiring layer formed on the interlayer insulating film and electrically connected to the gate electrode. Forming a dummy gate electrode made of a material that can be replaced with metal on a semiconductor substrate;
Forming an impurity diffusion region in the semiconductor substrate on both sides of the dummy gate electrode in a self-aligned manner with respect to the dummy gate electrode;
Forming a silicide film on the dummy gate electrode and the impurity diffusion region by self-alignment;
Forming an interlayer insulating film on the semiconductor substrate;
Forming an opening reaching the silicide film on the dummy gate electrode in the interlayer insulating film;
Forming a metal film on the interlayer insulating film;
A step of replacing the material constituting the dummy gate electrode with a metal material constituting the metal film by performing a heat treatment, and forming a gate electrode made of the metal material. Device manufacturing method. Forming a dummy gate electrode on a semiconductor substrate, made of a material that can be replaced with metal, and having an upper surface covered with a cap insulating film;
Forming an impurity diffusion region in the semiconductor substrate on both sides of the dummy gate electrode in a self-aligned manner with respect to the dummy gate electrode;
Forming a silicide film in a self-aligned manner on the impurity diffusion region;
Forming an interlayer insulating film on the semiconductor substrate;
Forming an opening reaching the dummy gate electrode in the interlayer insulating film and the cap insulating film;
Forming a metal film on the interlayer insulating film;
A step of replacing the material constituting the dummy gate electrode with a metal material constituting the metal film by performing a heat treatment, and forming a gate electrode made of the metal material. Device manufacturing method.

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