JP2005025864A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory that can reduce the number of chip selection signal lines without any additional semiconductor chips and whose yield hardly deteriorates even if the number of semiconductor memory chips is increased in the semiconductor memory comprising a plurality of semiconductor memory chips. <P>SOLUTION: A comparison circuit section 3 detects that a chip identification number coincides with a chip selection signal, and is provided on each semiconductor memory chip 1 for composing the semiconductor memory, thus the semiconductor memory chip is selected by the combination of each bit of the chip selection signal, and all signals other than the chip identification number is connected in a shared manner among semiconductor memory chips. Additionally, the semiconductor memory chips 1 to which different chip identification numbers are set respectively are assembled to packages that can be laminated, and signal connection is mutually made for forming modules. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device composed of a plurality of semiconductor memory chips, and more particularly to a semiconductor memory device capable of reducing the number of signal lines required when a specific chip is selected from a plurality of semiconductor memory chips. It is about.
[0002]
[Prior art]
In a conventional semiconductor memory device, particularly a memory module including a plurality of semiconductor memory chips, a plurality of semiconductor memories and a decoder for performing chip selection of the semiconductor memories are mounted on the same IC package. (For example, see Patent Document 1)
[0003]
[Patent Document 1]
JP 62-146482 A (page 3, FIG. 2)
[0004]
[Problems to be solved by the invention]
Since the conventional semiconductor memory device is configured as described above, a dedicated semiconductor chip in which a decoder for selecting a semiconductor memory chip is integrated in the same package is required separately from the semiconductor memory chip. There was a problem of being bulky. In addition, a plurality of semiconductor memory chips and decoder chips need to be connected to each other and accommodated in the same package, which causes a problem that the package assembly process becomes complicated. Further, since a plurality of semiconductor memory chips and decoder chips are assembled in the same package, if even one chip is defective at the stage of assembly into the package, all remaining chips are wasted. For this reason, there is a problem that the yield decreases as the number of chips increases.
[0005]
The present invention has been made to solve the above-described problems. In a semiconductor memory device composed of a plurality of semiconductor memory chips, it is not necessary to separately provide a decoder chip for selecting a semiconductor memory chip. It is an object of the present invention to provide a semiconductor memory device that can reduce the number of selection signal lines and facilitate the securing of yield even when the number of semiconductor memory chips increases.
[0006]
[Means for Solving the Problems]
A semiconductor memory device according to the present invention includes a comparison circuit that detects a match between a chip identification number set in advance and a chip selection signal input value composed of a plurality of bits and determines that the self is selected. A plurality of memory chips are connected to form a single module.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
FIG. 1 shows a configuration of a semiconductor memory chip constituting a semiconductor memory device according to Embodiment 1 of the present invention. In FIG. 1, a memory circuit portion 2 and a comparison circuit portion 3 are formed on a semiconductor memory chip 1. Selection signal terminals 4 and 5 for inputting respective bits of 2-bit chip selection signals CE0 and CE1 used for selection of a semiconductor memory chip are connected to the comparison circuit unit 3. The comparison circuit unit 3 is connected to input terminals 6 and 7 having a unique number (hereinafter referred to as a chip identification number) with respect to the semiconductor memory chip 1, and this terminal is used to set a chip identification number. Chip identification signals REF0 and REF1 are input as comparison targets for the chip selection signals CE0 and CE1. An output signal CE from the output terminal 8 of the comparison circuit unit 3 is applied to the memory circuit unit 2. An input terminal 9 for the address signal group A, an input / output terminal 10 for the data signal group D, an input terminal 11 for the write control signal WE, and an input terminal 12 for the output control signal OE are connected to the memory circuit unit 2. .
[0008]
Next, the operation of the semiconductor memory chip 1 of FIG. 1 will be described. Corresponding bits of the chip selection signals CE0 and CE1 from the selection signal terminals 4 and 5 and the chip identification numbers REF0 and REF1 from the identification number terminals 6 and 7, that is, in this example, the chip selection signal CE0 and the chip. When the input signal values of the identification number REF0, the chip selection signal CE1 and the chip identification number REF1 are compared by the comparison circuit unit 3 and all bits match, the output signal CE is output from the output terminal 8 of the comparison circuit unit 3 to the L level. Is output.
[0009]
When the output signal CE of the comparison circuit unit 3 becomes L level, the memory circuit unit 2 can be accessed, and the semiconductor memory chip 1 is selected. In this state, when the write control signal WE from the input terminal 11 is input at the H level and the output control signal OE from the input terminal 12 is input at the L level, the memory circuit unit 2 enters the read state and the input terminal 9 Information of the memory circuit unit 2 whose address is designated by the address signal group A is output to the input / output terminal 10 as a data signal group D. When the write control signal WE from the input terminal 11 is at L level and the output control signal OE from the input terminal 12 is at H level, the memory circuit unit 2 is in a write state, and the data signal group D is input from the input / output terminal 10. The given information is written to the address of the memory circuit unit 2 designated by the address signal group A from the input terminal 9. When the output signal CE of the comparison circuit unit 3 is at the H level, that is, when the chip is not selected, the address signal group A from the input terminal 9, the write control signal WE from the input terminal 11, and the output control signal from the input terminal 12 Regardless of the input value of OE, neither writing nor reading is performed on the memory circuit unit 2, and the data signal group D of the input / output terminal 10 is fixed to Hi-Z.
[0010]
Therefore, by fixing the chip identification numbers REF0 and REF1 from the identification number terminals 6 and 7 of the semiconductor memory chip 1 to arbitrary signal values of H or L level, respectively, the chip selection signal CE0 from the selection signal terminals 4 and 5 is obtained. , CE1 enables chip selection. Four values of LL, LH, HL, and HH levels can be realized with 2 bits of chip identification numbers REF0 and REF1 from the identification number terminals 6 and 7, and by assigning these values to individual semiconductor memory chips, Up to 4 chips can be identified and designated by 2 bits of the chip selection signals CE0 and CE1 from the selection signal terminals 4 and 5.
[0011]
FIG. 2 shows a circuit configuration example of the comparison circuit unit 3 provided on the semiconductor memory chip 1 of FIG. The comparison circuit unit 3 includes Ex-NOR circuits 13 a and 13 b and a NAND circuit 14. The Ex-NOR circuits 13a and 13b are circuits that output the H level when the inputs of the selection signal terminal 4 and the identification number terminal 6, the selection signal terminal 5 and the identification number terminal 7 match, and the L level when they do not match. The coincidence detection of the corresponding bits of the chip selection signal input and the chip identification number input is performed. By receiving these outputs by the NAND circuit 14, when all bits of the chip selection signal input and the chip identification number input match, the output signal CE is output at the L level to the output terminal 8 of the comparison circuit unit 3. It has become.
[0012]
In this embodiment, the coincidence detection of the 2-bit chip selection signal input and the chip identification number input is performed. However, the required number of Ex-NOR circuits can be prepared and the same configuration can be used to easily expand to multiple bits. Needless to say.
[0013]
FIG. 3 is a diagram showing a circuit configuration of a semiconductor memory device in which a plurality of the semiconductor memory chips of FIG. 1 assembled in a package are connected to form one module. In addition, a, b, and c attached to the reference numerals in the drawing are suffixes for convenience for identifying each package. Here, 1a, 1b, 1c are semiconductor memory packages in which the semiconductor memory chips 1 of FIG. 1 are assembled one by one into a package, and the chip identification numbers of the identification number terminals 6 and 7 of the semiconductor memory chip 1 when the package is assembled. Are connected to the power supply (VCC) or GND so as to be fixed to the LL level (in the case of 1a), the LH level (in the case of 1b), and the HL level (in the case of 1c), respectively, inside the package.
[0014]
The selection signal terminal 4a and the selection signal terminal 5a, the selection signal terminal 4b and the selection signal terminal 5b, the selection signal terminal 4c and the selection signal terminal 5c are the chip selection signal terminals of the semiconductor memory packages 1a, 1b and 1c, respectively. 4a, 4b, 4c and selection signal terminals 5a, 5b, 5c are connected to common chip selection signal lines 4x, 5x, respectively. Similarly, the input terminals 9a, 9b, and 9c of the address signal group of the semiconductor memory packages 1a, 1b, and 1c are written to the address signal line 9x, and the input / output terminals 10a, 10b, and 10c of the data signal group are written to the data signal line 10x. The input terminals 11a, 11b, and 11c are commonly connected to the write control signal line 11x, and the input terminals 12a, 12b, and 12c for the output control signal are commonly connected to the output control signal line 12x.
[0015]
In the configuration of FIG. 3, a semiconductor in which the L level is set to the chip identification numbers of the identification number terminals 6 and 7 of the semiconductor memory chip 1 by giving an L level to each of the chip selection signal lines 4 x and 5 x. The memory package 1a is selected. Similarly, by applying an L level to the chip selection signal line 4x and an H level to the chip selection signal line 5x, the semiconductor memory package 1b applies an H level to the chip selection signal line 4x and an L level to the chip selection signal line 5x. The semiconductor memory package 1c is selected. The read / write operation of the selected semiconductor memory package is the same as the read / write operation of the semiconductor memory chip 1 described above with reference to FIG.
[0016]
The semiconductor memory packages 1a, 1b, and 1c are connected to a common signal line. However, as described above, the semiconductor memory that is not selected for the chip includes the address signal line 9x, the write control signal line 11x, and the output control signal. Regardless of the signal value of the line 12x, rewriting of data in the memory portion does not occur, and the data signal terminal is fixed to Hi-Z, so that it is affected by the data write / read operation of the semiconductor memory selected on the chip. There is no impact. Further, in order to realize a state in which none of the semiconductor memory packages 1a, 1b, and 1c is selected, the case where the H level is given to both of the chip selection signal lines 4x and 5x is assigned to this state. A semiconductor memory having a setting of the corresponding chip identification number terminals 6 and 7 (both 6 and 7 are fixed at H level) is not connected.
[0017]
In the semiconductor memory chip of FIG. 1, the chip selection signal input and the chip identification number input are 2 bits, and it is possible to identify up to 4 chips that can be expressed by 2 bits. Since it is necessary to provide a state in which no semiconductor memory chip is selected, the number of connectable semiconductor memories is up to three.
[0018]
FIG. 4 is a side sectional view of the semiconductor memory package 1a showing a typical example of the structure of the semiconductor memory package. 6, 7 and 8 are plan views (upper surfaces) of the semiconductor memory packages 1a, 1b and 1c, respectively. However, for the sake of simplicity, the semiconductor memory chip 1 is not shown, and its arrangement frame is indicated by a broken line 26. As an example, in a CSP (Chip Scale Package) type package, the selection signal terminals 4 and 5, the address signal group input terminal 9, the data signal group input terminal 10, the write control signal input terminal 11, and the output control signal of the semiconductor memory chip 1. A bump 20a, which is a protruding connection terminal, is formed on the input terminal 12, the power supply terminal, and the GND terminal. The respective terminals of the semiconductor memory chip 1 flip-chip mounted on the CSP substrate 21a through these bumps 20a are connected to the connection terminals 24a through signal wirings 22a formed on the CPS substrate 21a. The connection terminal 24a is connected to a solder ball 23a on the lower side of the CSP substrate 21a through a via 25a for electrically connecting the upper and lower conductor layers of the CSP substrate 21a. The via 25a is made of a hole formed in the CSP substrate 21a and a plating layer that electrically connects the upper and lower conductor layers through the hole or a conductor paste filled in the hole. That is, the solder balls 23a on the lower surface of the CSP substrate 21a and the connection terminals 24a on the upper surface of the package are located on the same coordinates with the CSP substrate 21a interposed therebetween, and are connected to each other via the vias 25a.
[0019]
Similarly, the chip identification number terminals 6 and 7 of the semiconductor memory chip 1 are connected to the CSP substrate 21a via bumps, but unlike other signal line terminals, they are not a package terminal for signal transmission but a power supply (VCC) or An arbitrary chip identification number is set for the semiconductor memory chip 1 connected to the GND. In the semiconductor memory package 1a, both REF0 and REF1 are connected to GND as shown in FIG. 6, and in the semiconductor memory package 1b, as shown in FIG. 7, REF0 is connected to GND and REF1 is connected to the power supply (VCC). In the package 1c, as shown in FIG. 8, REF0 is connected to the power supply (VCC), and REF1 is connected to GND.
[0020]
5 is a side sectional view showing a module in which the semiconductor memory package 1a shown in FIGS. 4 and 6 and semiconductor memory packages 1b and 1c similar to these are stacked, and FIG. 9 is a plan view (lower surface) of this module. As shown in FIG. 5, the semiconductor memory packages 1a, 1b and 1c having the structures shown in FIGS. 6 to 8 having different chip identification numbers are simply stacked one above the other via solder balls 23a, 23b and 23c. And implement. The semiconductor memory package 1a is disposed on the solder balls 23a, the connection terminals 24a on the upper surface of the CSP substrate 21a of the semiconductor memory package 1a, the solder balls 23b of the semiconductor memory package 1b, and the connection terminals 24b on the upper surface of the CSP substrate 21b of the semiconductor memory package 1b. Each of the signal terminals on each of the semiconductor memory chips 1 of the semiconductor memory packages 1a, 1b, and 1c that are connected to the CSP substrate by the bumps 20a, 20b, and 20c are connected to the solder balls 23c of the semiconductor memory package 1c. Connection to the signal line is realized. Since the signal terminal arrays of the semiconductor memory packages 1a, 1b, and 1c are all common, the corresponding signal terminals of each package are all connected on the same signal line, and the module that realizes the circuit configuration of FIG. Become.
[0021]
As described above, in a semiconductor memory device composed of a plurality of semiconductor memory chips, it is specified by a combination of each bit signal value of a chip selection signal consisting of a plurality of bits based on a chip identification number assigned to each semiconductor memory chip. A semiconductor memory chip is designated, and a comparator circuit for detecting coincidence between the chip identification number and the chip selection signal input value is integrated on each memory chip, so that a decoder circuit for a chip selection signal composed of a plurality of bits is integrated. This eliminates the need for a separate semiconductor chip, and can reduce the number of chip selection signal lines in the semiconductor memory device. In a general method of assigning one dedicated chip selection signal line to each semiconductor memory chip, only N chips can be selected by N chip selection signal lines. However, according to the chip selection method of the present invention, (2 ^N −1) chips can be selected by removing one state where no chip is selected from the number of possible combinations of N chip selection signal lines, and the number of chip selection signal lines decreases as the number of chips increases. The effect is increased. In this embodiment, three semiconductor memory chips are included in the semiconductor memory device. However, it is obvious that the number of semiconductor memory chips is not limited to this. Further, although the package form is described as CSP, it may be QFP (Quad Flat Package) or TSOP (Thin Small Outline Package) as long as it has a stackable terminal shape.
[0022]
Conventionally, one dedicated chip selection signal line is assigned to each memory chip constituting the semiconductor memory device. However, in the present invention, a chip selection signal line composed of a plurality of bits corresponding to the number of semiconductor memory chips is provided. Since each semiconductor memory chip is shared, all signal terminals of each memory chip can be shared and connected between the memory chips except for the chip identification number input unique to the present invention. Therefore, it is possible to assemble a package with chip identification numbers assigned to individual semiconductor memory chips and connect corresponding signal terminals of each package to form a single module. By assembling individually tested semiconductor memory packages into modules, it is possible to obtain a semiconductor memory device composed of a plurality of semiconductor memory chips that does not deteriorate the yield even when the number of semiconductor memory chips increases. Further, by stacking and mounting packages, a module including a plurality of packages can be realized with a mounting area similar to that of a single package.
[0023]
【The invention's effect】
As described above, according to the present invention, a semiconductor memory device composed of a plurality of semiconductor memory chips does not require a separate decoder chip for performing chip selection of the semiconductor memory chip, and can reduce chip selection signal lines. In addition, it is possible to provide a semiconductor memory device that can easily secure the yield even when the number of semiconductor memory chips increases.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a semiconductor memory chip used in a semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a schematic diagram showing a circuit example of a comparison circuit unit integrated on the semiconductor memory chip in the first embodiment of the present invention.
FIG. 3 is a configuration diagram showing a semiconductor memory device according to the first embodiment of the present invention;
FIG. 4 is a cross-sectional view showing a semiconductor memory assembled in a package according to the first embodiment of the present invention.
FIG. 5 is a side sectional view showing the semiconductor memory device according to the first embodiment of the present invention.
FIG. 6 is a plan view (upper surface) of the CSP substrate of the semiconductor memory according to the first embodiment of the present invention.
FIG. 7 is a CSP substrate plan view (upper surface) of the semiconductor memory according to the first embodiment of the present invention;
FIG. 8 is a plan view (upper surface) of the CSP substrate of the semiconductor memory according to the first embodiment of the present invention;
FIG. 9 is a plan view (bottom surface) of the CSP substrate of the semiconductor memory according to the first embodiment of the present invention;
[Explanation of symbols]
1 semiconductor memory chip,
1a, 1b, 1c semiconductor memory package,
2 memory circuit section,
3 comparison circuit section,
4,5 chip selection signal terminal,
4a, 4b, 4c, 5a, 5b, 5c Chip selection signal terminals,
4x, 5x chip selection signal line,
6,7 Chip identification number terminal,
8 Comparison circuit part output signal terminal,
9 Address signal group input terminal,
9a, 9b, 9c address signal group input terminals,
9x address signal lines,
10 Data signal group input / output terminals,
10a, 10b, 10c Data signal group input / output terminals,
10x data signal line group,
11 Write control signal input terminal,
11a, 11b, 11c Write control signal input terminals,
11x write control signal line,
12 Output control signal input terminal,
12a, 12b, 12c output control signal input terminals,
12x output control signal line,
13a, 13b Ex-NOR circuit,
14 NAND circuit,
20a, 20b, 20c Bump,
21a, 21b, 21c CSP substrate,
22a, 22b, 22c signal wiring,
23a, 23b, 23c solder balls,
24a, 24b, 24c connection terminals,
25a, 25b, 25c vias,
26 An arrangement frame for a semiconductor memory chip.

Claims (3)

A plurality of semiconductor memory chips having a comparison circuit for detecting that the chip identification number set in advance and a chip selection signal input value composed of a plurality of bits are matched to determine that the self is selected are connected to each other. A semiconductor memory device characterized by being a module. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory chip includes a plurality of signal terminals for setting a chip identification number, and the chip identification number is set by connecting these signal terminals to a power supply or GND. A semiconductor memory device characterized by that. 3. The semiconductor memory device according to claim 1, wherein a semiconductor memory chip is housed in a semiconductor memory package having a configuration in which signal connection is made between upper and lower packages when stacked, and a plurality of the semiconductor memory packages are stacked. A semiconductor memory device comprising a single module.

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