JP2005025411A - Clock supply device and clock generation control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic apparatus capable of stopping supply of a predetermined clock in predetermined timing. <P>SOLUTION: This electronic apparatus is in an operation condition after clock skew adjustment. In this condition, a CLK_EN23b in a High condition is inputted into a frequency division part 11 when supply of a clock of 1MHz is stopped. When supply of the clock of 1MHz is started again to a bit stream processing part 3, the CLK_EN23b in a Low condition is inputted to an AND circuit 26 of a negative logic in the frequency division part 11. In this process, since the electronic apparatus is in the operation condition after the clock skew adjustment, a RESET signal 42 in a High condition is inputted to a clock comparison part 12 and stored in the clock skew adjusted condition. Therefore, the clock of 1MHz can be fed to the bit stream processing part 3 without performing clock skew adjustment again. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock supply device, and more particularly to a clock supply device that divides a reference clock.
[0002]
[Prior art]
Conventionally, in a portable electronic device such as a PDA (Personal Digital Assistant), if the entire circuit is operated using the same clock frequency, power consumption increases, resulting in a short battery operation time. there were.
[0003]
Therefore, a circuit that can operate at a clock frequency lower than a reference clock frequency (hereinafter referred to as a reference clock), rather than operating the entire circuit using the same clock frequency, has a clock frequency ( Hereinafter, the operation is preferably performed using a frequency-divided clock. Further, if the supply of the clock frequency to the circuit in the unused state is stopped, the power consumption can be further reduced.
[0004]
As a prior art for stopping the clock frequency, there has been a technique for preventing a clock stop and a hazard at the start by latching a clock stop signal at a low level of the clock. (See Patent Document 1).
[0005]
[Patent Document 1]
JP 2000-99189 A (page 3, FIG. 1)
[0006]
[Problems to be solved by the invention]
However, Patent Document 1 does not describe the timing of stopping and starting the clock.
[0007]
Accordingly, an object of the present invention is to provide a clock supply device capable of stopping the supply of a predetermined clock at a predetermined timing.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, in the invention according to claim 1, a clock generation unit that generates the first clock, a frequency division unit that generates the second clock by dividing the first clock, A delay for generating a predetermined amount of delay time to be inserted into the first clock by comparing the skew between the first clock generated by the clock generator and the second clock divided by the divider An element and a stop signal that is input to the frequency division unit and stops generation of the second clock, and inserting a predetermined amount of delay time generated by the delay element into the first clock, After adjusting the skew with the second clock, the generation of the second clock is stopped by inputting the stop signal to the frequency divider.
[0009]
With such a configuration, it is possible to stop the supply of the clock.
[0010]
In the invention according to claim 3, the clock generator generates the first clock, the frequency divider that generates the second clock by dividing the first clock, and the clock generator. A clock comparison unit that compares the skew between the first clock and the second clock divided by the frequency division unit, and a result of comparison between the first clock and the second clock by the clock comparison unit. A delay element that generates a predetermined amount of time to be inserted into the first clock; a first stop signal that is input to the frequency divider, and stops generating the second clock; and is input to the clock comparator And having a second stop signal for stopping the comparison between the first clock and the second clock, and inserting a predetermined delay time amount generated by the delay element into the first clock. , Second clock and After adjusting the queue, the second stop signal is input to the clock comparison unit to stop the comparison between the first clock and the second clock, and the first stop signal is input to the frequency dividing unit. Thus, the generation of the second clock is stopped.
[0011]
With such a configuration, after the skew adjustment between the reference clock and the divided clock, the skew comparison operation between the reference clock and the divided clock is stopped, and the supply of the clock can be stopped.
[0012]
In the invention according to claim 5, the first clock is generated, the second clock is generated by dividing the first clock, and the skew between the first clock and the second clock is compared. Thus, a predetermined delay time amount inserted into the first clock is generated, and the generated predetermined delay time amount is inserted into the first clock, whereby the first clock and the second clock are And the second clock generation is stopped after adjusting the skew between the first clock and the second clock.
[0013]
With such a configuration, it is possible to stop the supply of the clock.
[0014]
In the invention according to claim 6, the first clock is generated, the second clock is generated by dividing the first clock, and the skew between the first clock and the second clock is compared. Thus, a predetermined delay time amount inserted into the first clock is generated, and the generated predetermined delay time amount is inserted into the first clock, whereby the first clock and the second clock are The skew is adjusted, and after the adjustment, the skew comparison between the first clock and the second clock is stopped, and the generation of the second clock is further stopped.
[0015]
With such a configuration, after the skew adjustment between the reference clock and the divided clock, the skew comparison operation between the reference clock and the divided clock is stopped, and the supply of the clock can be stopped.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0017]
FIG. 1 is a hardware block diagram of an electronic device according to the present invention.
[0018]
The electronic apparatus includes a CPU (Central Processor Unit) 1, a memory 2, a bit stream processing unit 3, a DMAC (Direct Memory Access Controller) 4, a clock supply unit 5, and a wireless module 6.
[0019]
The CPU 1 performs control of the entire electronic device, calculation of data, and the like. The memory 2 stores program instructions and processing data. The bit stream processing unit 3 sequentially accesses the data to be transferred in bit units and performs bit processing. The DMAC 4 transmits data between the memory 2 and the bit stream processing unit 3 without going through the CPU 1. The wireless module 6 modulates data processed by the bit stream processing unit 3 or demodulates radio waves received by an antenna (not shown) and transmits the data to the bit stream processing unit 3. For example, the clock supply unit 5 supplies an operation clock of 13 MHz to the CPU 1, the memory 2, and the DMAC 4, and supplies an operation clock of 1 MHz to the bit stream processing unit 3.
[0020]
FIG. 2 is a diagram illustrating a hardware configuration of the clock supply unit.
[0021]
The clock supply unit 5 includes an original oscillation unit 10, a frequency division unit 11, a clock comparison unit 12, an up / down counter 13, a multiplexer 14, and a delay element 15.
[0022]
The original oscillation unit (clock generation unit) 10 generates an original clock CLK_ORG (first clock) 10a that is 13 MHz.
[0023]
The frequency divider 11 generates a 1 MHz clock (second clock) 11b and a signal DLY_EN 11a obtained by dividing the CLK_ORG 10a of 13 MHz. Further, CLK_EN 23b, which is a signal for controlling generation of the 1 MHz clock 11b, is input to the frequency divider 11.
[0024]
The clock comparison unit (delay control signal generation unit) 12 compares the phase difference (skew) between the 1 MHz clock 11b divided by the frequency division unit 11 and the 13 MHz clock 14a into which a delay described later is inserted. . As a comparison result in the clock comparison unit 12, an upcount clock UCLK (first delay control signal) 12a and a downcount clock DCLK (second delay control signal) 12b are output. Further, the clock comparison unit 12 receives a RESET signal 42 that is a signal for controlling generation of the UCLK 12 a and the DCLK 12 b.
[0025]
The up / down counter (delay time amount designating unit) 13 counts up when the up count clock UCLK12a is input, and counts down when the down count clock DCLK12b is input. Based on the count-up operation or the count-down operation in the up / down counter 13, the select signal 13a is output.
[0026]
The delay element 15 includes elements D1 to DN. Each element constituting the delay element 15 has a delay time inserted into the CLK_ORG 10a.
[0027]
A selector signal 13 a is input to the multiplexer (delay insertion unit) 14. Based on the selector signal 13a, an element group having a delay input to the CLK_ORG 10a is determined. The multiplexer 14 outputs a 13 MHz clock 14a obtained by inputting a delay to the CLK_ORG 10a.
[0028]
FIG. 3 is a diagram illustrating a hardware configuration of the frequency dividing unit.
[0029]
FIG. 4 is a diagram illustrating a process of generating a 1 MHz clock.
[0030]
FIG. 5 is a diagram illustrating a process of generating a signal DLY_EN that is a 1 MHz clock.
[0031]
The frequency divider 11 includes a synchronous clear counter 20, a NOT circuit 21, a NAND circuit 22, negative logic AND circuits 23, 25 and 26, and a flip-flop (FF) 24.
[0032]
The synchronous clear counter 20 is up-counted at the rising edge of the input CLK_ORG 10a. When the low state of CLY_PLS 22a, which will be described in detail later, is input at the rising edge of CLK_ORG 10a, the counter value of the synchronous clear counter 20 is reset to zero.
[0033]
The synchronous clear counter 20 outputs via the wirings 20a, 20b, 20c, and 20d. The wiring 20a represents a 2 0th digit, the wiring 20b represents a 2nd power digit, the wiring 20c represents a 2nd power digit, and the wiring 20d represents a 2th power digit. For example, if the value of the synchronous clear counter 20 is 3, the state of the signal output to the wiring 20a is 1 (High), the state of the signal output to the wiring 20b is 1 (High), and the signal output to the wiring 20c. Is 0 (Low), and the signal output to the wiring 20d is 0 (Low).
[0034]
A signal output from the synchronous clear counter 20 is input to the NOT circuit 21 and the NAND circuit 22, and a clear pulse CLR_PLS 22a is output. When the value of the synchronous clear counter 20 is 0 to 11, the state of the signal CLR_PLS 22a is 1 (High). However, when the value of the synchronous clear counter 20 is 12, the state of the signal CLR_PLS 22a is 0 (Low). The low state of the CLR_PLS 22a is input to the synchronous clear counter 20, and the value of the synchronous clear counter 20 is reset to zero. In accordance with the method described above, the NOT circuit 21 and the NAND circuit 22 operate the synchronous clear counter 20 as a 13-digit counter.
[0035]
The FF 24 receives the CLR_PLS 22a and the CLK_ORG 10a, and outputs a signal 24a obtained by delaying the CLR_PLS 22a by one cycle.
[0036]
Hereinafter, a description will be given with reference to FIG. The negative logic AND circuit 23 receives CLR_PLS 22a and CLK_ORG 10a and generates 1 MHz_ORG 23a which is a 1 MHz clock.
[0037]
Further, the negative logic AND circuit 26 receives 1 MHz_ORG 23a, which is the output of the negative logic AND circuit 23, and CLK_EN 23b controlled by the CPU 1, for example, and generates a 1 MHz clock as the output signal 11b.
[0038]
When the state of CLK_EN 23b is 0 (Low), the output signal 11b generates a negative pulse. That is, a 1 MHz clock is generated. On the other hand, when the state of CLK_EN 23b is 1 (High), the state of the output signal 11b is 1 (High) regardless of the state of 1 MHz_ORG 23a, and a 1 MHz clock is not generated.
[0039]
The CPU 1 can control the generation of the 1 MHz clock 11b by controlling the state of the CLK_EN 23b to either High or Low. For example, when the wireless communication function is not used, it is not necessary to supply a 1 MHz clock to the bit stream processing unit 3. Therefore, by keeping the state of CLK_EN 23b High, it is possible to stop the 1 MHz clock supply to the bit stream processing unit 3 and reduce power consumption.
[0040]
When restarting the 1 MHz clock supply to the bit stream processing unit 3, the state of the CLK_EN 23b is changed from High to Low.
[0041]
The negative logic AND circuit 25 receives the signal 24a obtained by delaying the CLR_PLS 22a by one cycle and the CLK_ORG 10a, and generates DLY_EN which is a 1 MHz clock as the output signal 11a as shown in FIG. This DLY_EN is a signal that determines the output timing of DCLK 12a and UCLK 12b, which will be described in detail later.
[0042]
FIG. 6 is a diagram illustrating a hardware configuration of the clock comparison unit.
[0043]
Hereinafter, the configuration of the clock comparison unit 12 will be described. The FF 30 continues toggling by taking in the signal 31a obtained by inverting the output signal 30a of the FF 30 by the NOT circuit 31 based on the rising edge of the 13 MHz clock 14a in which a delay is input to the CLK_ORG 10a described in detail later.
[0044]
The FF 32 takes in the signal 30a at the rising edge of the 1 MHz clock 11b generated by the frequency divider 11b and generates an output signal 32a.
[0045]
The EXOR circuit 33 receives the output signal 30a of the FF 30 and the output signal 32a of the FF 32, and outputs a signal 33a.
[0046]
The negative logic AND circuit 34 receives the DLY_EN 11a and the output signal 33a of the EXOR circuit 33, and outputs a signal 34a.
[0047]
The negative logic AND circuit 40 receives an output signal 34a of the negative logic AND circuit 34 and a RESET signal 42 which initializes the entire apparatus, and outputs UCLK 12a.
[0048]
The FF 35 maintains the toggle by taking in the signal 36a obtained by inverting the output signal 35a of the FF 35 itself by the NOT circuit 31 at the rising edge of the 1 MHz clock 11b generated by the frequency divider 11b.
[0049]
The FF 37 takes in the signal 35a and generates an output signal 37a based on the rising edge of the 13 MHz clock 14a in which a delay is input to the CLK_ORG 10a described in detail later.
[0050]
The EXOR circuit 38 receives the output signal 35a of the FF 35 and the output signal 37a of the FF 37, and outputs a signal 38a.
[0051]
The negative logic AND circuit 39 receives the DLY_EN 11a and the output signal 38a of the EXOR circuit 38, and outputs a signal 39a.
[0052]
The negative logic AND circuit 41 receives the output signal 39a of the negative logic AND circuit 39 and the RESET signal 42 used when initializing the entire apparatus, and outputs DCLK 12b.
[0053]
FIG. 7 is a diagram comparing the waveform of a 13 MHz clock signal with the waveform of a 1 MHz clock signal.
[0054]
FIG. 8 is a diagram illustrating generation of a signal to be compared using the FF.
[0055]
FIG. 9 is a diagram illustrating comparison of signals by the EXOR circuit.
[0056]
FIG. 10 is a diagram illustrating generation of a signal by a negative logic AND circuit.
[0057]
FIG. 11 is a diagram illustrating generation of UCLK when the RESET signal is in the Low state.
[0058]
FIG. 12 is a diagram illustrating generation of UCLK when the RESET signal is in a high state.
[0059]
Hereinafter, UCLK generation when the 1 MHz clock signal 11b is delayed compared to the 13 MHz clock signal 14a will be described with reference to FIGS.
[0060]
As shown in FIG. 7, the signal 14a is a waveform of a 13 MHz clock signal. The signal 11c is a waveform of a 1 MHz clock signal, and this signal 11c is not delayed as compared with the signal 14a. Therefore, the signal 11b obtained by sliding the signal 11c to the right side is in a state delayed from the signal 14a.
[0061]
As shown in FIG. 8, the FF 32 captures the state (High) of the output signal 30a of the FF 30 based on the rising operation of the signal 11b of the 1 MHz clock. Using this captured state, a signal 32a which is an output signal of the FF 32 is generated.
[0062]
As shown in FIG. 9, the signal 30 a that is the output signal of the FF 30 and the signal 32 a that is the output signal of the FF 32 are compared by the EXOR circuit 33, thereby generating a signal 33 a that is the output signal of the EXOR circuit 33.
[0063]
As shown in FIG. 10, the DLY_EN 11 a generated by the frequency divider 11 and the signal 33 a that is the output signal of the EXOR circuit 33 are input to the negative logic AND circuit 34, whereby the output of the negative logic AND circuit 34. A signal 34a, which is a signal, is generated.
[0064]
As shown in FIG. 11, the signal 34 a that is the output signal of the negative logic AND circuit 34 and the RESET signal 42 in the low state are input to the negative logic AND circuit 40, whereby the output of the negative logic AND circuit 40. A signal 12a is generated. This signal 12a is the UCLK 12a in the low state in the period a.
[0065]
Further, as shown in FIG. 12, the signal 34 a that is the output signal of the negative logic AND circuit 34 and the RESET signal 42 in the high state are input to the negative logic AND circuit 40, whereby the negative logic AND circuit 40. Output signal 12a is generated. This signal 12a is a signal in a high state.
[0066]
FIG. 13 is a diagram illustrating generation of a signal to be compared using an FF.
[0067]
FIG. 14 is a diagram illustrating comparison of signals by the EXOR circuit.
[0068]
FIG. 15 is a diagram illustrating generation of a signal by a negative logic AND circuit.
[0069]
FIG. 16 is a diagram illustrating generation of DCLK when the RESET signal is in the Low state.
[0070]
FIG. 17 is a diagram illustrating generation of DCLK when the RESET signal is in a high state.
[0071]
Hereinafter, the generation of DCLK when the 1 MHz clock signal 11b is delayed as compared with the 13 MHz clock signal 14a will be described with reference to FIGS.
[0072]
As shown in FIG. 13, the FF 37 takes in the state (High) of the output signal 35a of the FF 35 based on the rising operation of the signal 14a of the 13 MHz clock. Using this captured state, a signal 37a which is an output signal of the FF 37 is generated.
[0073]
As shown in FIG. 14, the signal 35 a that is the output signal of the FF 35 and the signal 37 a that is the output signal of the FF 37 are compared by the EXOR circuit 38, thereby generating a signal 38 a that is the output signal of the EXOR circuit 38.
[0074]
As shown in FIG. 15, the DLY_EN 11 a generated by the frequency divider 11 and the signal 38 a that is the output signal of the EXOR circuit 38 are input to the negative logic AND circuit 39, whereby the output of the negative logic AND circuit 39 is output. A signal 39a, which is a signal, is generated.
[0075]
As shown in FIG. 16, the signal 39 a that is the output signal of the negative logic AND circuit 39 and the RESET signal 42 in the low state are input to the negative logic AND circuit 41, whereby the output of the negative logic AND circuit 41 is output. A signal 12b is generated. This signal 12b is a signal in a high state.
[0076]
Further, as shown in FIG. 17, the signal 39 a which is the output signal of the negative logic AND circuit 39 and the RESET signal 42 in the high state are input to the negative logic AND circuit 41, whereby the negative logic AND circuit 41. Output signal 12b is generated. This signal 12b is a signal in a high state.
[0077]
As described with reference to FIGS. 7 to 17, when the 1 MHz clock signal 11b is delayed compared to the 13 MHz clock signal 14a, the RESET signal 42 is input to the negative logic AND circuit 40 in the low state. Sometimes, the output signal 12a of the negative logic AND circuit 40 generates a negative pulse (Low state in period a in FIG. 11), thereby generating UCLK 12a. Even if the RESET signal 42 is input to the negative logic AND circuit 41 in either the low state or the high state, the output signal 12b of the negative logic AND circuit 41 is a signal in the high state, so that the DCLK 12b is generated. Not.
[0078]
FIG. 18 is a diagram comparing the waveform of a 13 MHz clock signal with the waveform of a 1 MHz clock signal.
[0079]
FIG. 19 is a diagram illustrating generation of a signal to be compared using FF.
[0080]
FIG. 20 is a diagram illustrating comparison of signals by the EXOR circuit.
[0081]
FIG. 21 is a diagram illustrating generation of a signal by a negative logic AND circuit.
[0082]
FIG. 22 is a diagram illustrating generation of UCLK when the RESET signal is in the Low state.
[0083]
FIG. 23 is a diagram illustrating generation of UCLK when the RESET signal is in a high state.
[0084]
Hereinafter, generation of UCLK when the signal 14a of the 13 MHz clock is delayed compared to the signal 11b of the 1 MHz clock will be described with reference to FIGS.
[0085]
As shown in FIG. 18, the signal 14a is a waveform of a 13 MHz clock signal. The signal 11c is a waveform of a 1 MHz clock signal, and this signal 11c is not delayed as compared with the signal 14a. Therefore, the signal 14a is delayed as compared with the signal 11b obtained by sliding the signal 11c to the left.
[0086]
As shown in FIG. 19, the FF 32 takes in the state (Low) of the output signal 30a of the FF 30 based on the rising operation of the signal 11b of the 1 MHz clock. Using this captured state, a signal 32a which is an output signal of the FF 32 is generated.
[0087]
As shown in FIG. 20, the signal 30 a that is the output signal of the FF 30 and the signal 32 a that is the output signal of the FF 32 are compared by the EXOR circuit 33, thereby generating a signal 33 a that is the output signal of the EXOR circuit 33.
[0088]
As shown in FIG. 21, the DLY_EN 11 a generated by the frequency divider 11 and the signal 33 a that is the output signal of the EXOR circuit 33 are input to the negative logic AND circuit 34, whereby the output of the negative logic AND circuit 34. A signal 34a, which is a signal, is generated.
[0089]
As shown in FIG. 22, the signal 34 a that is the output signal of the negative logic AND circuit 34 and the RESET signal 42 in the low state are input to the negative logic AND circuit 40, whereby the output of the negative logic AND circuit 40. A signal 12a is generated. This signal 12a is a signal in a high state.
[0090]
Further, as shown in FIG. 23, the signal 34 a that is the output signal of the negative logic AND circuit 34 and the RESET signal 42 in the high state are input to the negative logic AND circuit 40, whereby the negative logic AND circuit 40. Output signal 12a is generated. This signal 12a is a signal in a high state.
[0091]
FIG. 24 is a diagram illustrating generation of a signal to be compared using FF.
[0092]
FIG. 25 is a diagram illustrating comparison of signals by the EXOR circuit.
[0093]
FIG. 26 is a diagram illustrating generation of a signal by a negative logic AND circuit.
[0094]
FIG. 27 is a diagram illustrating generation of DCLK when the RESET signal is in the Low state.
[0095]
FIG. 28 is a diagram illustrating generation of DCLK when the RESET signal is in a high state.
[0096]
Hereinafter, generation of DCLK when the signal 14a of the 13 MHz clock is delayed as compared with the signal 11b of the 1 MHz clock will be described with reference to FIGS.
[0097]
As shown in FIG. 24, the FF 37 takes in the state (Low) of the output signal 35a of the FF 35 based on the rising operation of the signal 14a of the 13 MHz clock. Using this captured state, a signal 37a which is an output signal of the FF 37 is generated.
[0098]
As shown in FIG. 25, the EXOR circuit 38 compares the signal 35a that is the output signal of the FF 35 and the signal 37a that is the output signal of the FF 37, thereby generating a signal 38a that is the output signal of the EXOR circuit 38.
[0099]
As shown in FIG. 26, the DLY_EN 11a generated by the frequency divider 11 and the signal 38a that is the output signal of the EXOR circuit 38 are input to the negative logic AND circuit 39, whereby the output of the negative logic AND circuit 39 is output. A signal 39a, which is a signal, is generated.
[0100]
As shown in FIG. 27, a signal 39a, which is an output signal of the negative logic AND circuit 39, and a RESET signal 42 in the low state are input to the negative logic AND circuit 41, whereby the output of the negative logic AND circuit 41 is output. A signal 12b is generated. This signal 12b is the DCLK 12b in the low state in the period b.
[0101]
Further, as shown in FIG. 28, the signal 39 a that is the output signal of the negative logic AND circuit 39 and the RESET signal 42 in the high state are input to the negative logic AND circuit 41, whereby the negative logic AND circuit 41. Output signal 12b is generated. This signal 12b is a signal in a high state.
[0102]
As described with reference to FIGS. 18 to 28, when the 13 MHz clock signal 14 a is delayed as compared with the 1 MHz clock signal 11 b, the negative logic indicates whether the RESET signal 42 is in the low state or the high state. Even if it is input to the AND circuit 40, the output signal 12a of the negative logic AND circuit 40 is a High state signal, and therefore, the UCLK 12a is not generated. When the RESET signal 42 is input to the negative logic AND circuit 41 in the Low state, the output signal 12b of the negative logic AND circuit 41 generates a negative pulse (Low state in the period b in FIG. 27). DCLK12b is generated.
[0103]
From the above description, when the RESET signal 42 is input to the negative logic AND circuit 40 and the negative logic AND circuit 41 in the low state, UCLK 12 a or DCLK 12 b is generated. Then, UCLK12a or DCLK12b is input to the up / down counter 13, and clock skew adjustment is performed.
[0104]
On the other hand, when the RESET signal 42 is input to the negative logic AND circuit 40 and the negative logic AND circuit 41 in a high state, the signal 12a and the signal 12b do not generate a pulse. That is, UCLK12a or DCLK12b is not generated. The UCLK 12a or DCLK 12b is not input to the up / down counter 13, and the clock skew adjustment is not performed.
[0105]
Therefore, when the clock skew adjustment is completed and it is not necessary to perform the clock skew adjustment thereafter, it is necessary to determine the amount of delay time input to the original clock by inputting UCLK 12a or DCLK 12b to the up / down counter 13. Absent. Therefore, when it is not necessary to perform clock skew adjustment, the RESET signal 42 in the high state may be input to the negative logic AND circuit 40 and the negative logic AND circuit 41.
[0106]
FIG. 29 is a flowchart for explaining a clock skew adjustment procedure.
[0107]
When the RESET signal 42 input to the clock comparison unit 12 is in the low state (S1 Yes), clock skew adjustment is performed between the 13 MHz clock and the 1 MHz clock obtained by dividing the 13 MHz clock (S2). The case where the clock skew adjustment is performed is, for example, a case where the electronic device according to the present invention is in an initialized state.
[0108]
On the other hand, when the RESET signal 42 input to the clock comparison unit 12 is in the High state (S1 No), the clock skew adjustment between the 13 MHz clock and the 1 MHz clock is not performed (S3). The case where the clock skew adjustment is not performed is, for example, a case where the electronic device according to the present invention is in an operation state in which the clock skew adjustment is finished in the initialization state and the state is shifted from the initialization state. Next, the clock skew adjustment procedure performed when the RESET signal 42 is in the low state will be described.
[0109]
FIG. 30 is a flowchart for explaining a procedure for adjusting the clock skew.
[0110]
The clock comparison unit 12 receives the 13 MHz signal 14a and the 1 MHz signal 11b into which a predetermined delay has been inserted (S4). The clock comparison unit 12 compares the signal 14a and the signal 11b (S5).
[0111]
When the clock comparison unit 12 compares the signal 14a with the signal 11b and the signal 11b is delayed from the signal 14a, the clock comparison unit 12 outputs UCLK 12a as a comparison result (S6). The UCLK 12a is input to the up / down counter 13, and the counter value is up-counted (S7). The up / down counter 13 outputs a select signal 13a based on the counter value (S8). When the select signal 13a is input to the multiplexer 14, the number of elements that generate a delay inserted into CLK_ORG is increased (S9).
[0112]
When the clock comparison unit 12 compares the signal 14a with the signal 11b and the signal 14a is delayed from the signal 11b, the clock comparison unit 12 outputs DCLK 12b as a comparison result (S10). The DCLK 12b is input to the up / down counter 13, and the counter value is counted down (S11). The up / down counter 13 outputs a select signal 13a based on the counter value (S12). When the select signal 13a is input to the multiplexer 14, the number of elements that cause a delay inserted into the CLK_ORG 10a is reduced (S13).
[0113]
The multiplexer 14 increases or decreases the number of delay elements, and based on the result, a delay is inserted into the CLK_ORG 10a (S14), and a signal 14a is generated (S15). The generated signal 14a is input again to the clock comparison unit 12, that is, fed back.
[0114]
The clock comparison unit 12 compares the 13 MHz clock signal 14 a and the 1 MHz clock signal 11 b used, and adjusts the delay inserted into the 13 MHz original clock signal 10 a based on the result, thereby using the 13 MHz clock. The skew between the clock signal 14a and the 1 MHz clock signal 11b can be adjusted.
[0115]
FIG. 31 is a flowchart illustrating a procedure for controlling generation of a 1 MHz clock when the electronic apparatus according to the invention is in an operating state.
[0116]
The electronic device according to the present invention is in an operation state in which the clock skew adjustment is completed and the state is shifted from the initialization state. In this state, when the wireless communication function is stopped, that is, when the supply of the 1 MHz clock to the bit stream processing unit 3 is stopped (S16 Yes), the negative logic AND of the frequency dividing unit 11 described with reference to FIG. The CLK_EN 23b which is in a high state is input to the circuit 26 (S17). On the other hand, when the supply of the 1 MHz clock to the bit stream processing unit 3 is not stopped (No in S16), the CLK_EN 23b in the low state is input to the negative logic AND circuit 26 of the frequency dividing unit 11 described with reference to FIG. (S17).
[0117]
After stopping the supply of the 1 MHz clock to the bit stream processing unit 3 and starting the supply of the 1 MHz clock again (Yes in S18), the negative logic AND circuit 26 of the frequency dividing unit 11 is in the low state. Is input CLK_EN23b (S19). At this time, since the electronic device according to the present invention has finished the clock skew adjustment and is in an operating state, the RESET signal 42 is input to the clock comparison unit 12 in the High state, and is stored in a state in which the clock skew adjustment has been completed. ing. Therefore, the CLK_EN 23b in the low state is input to the negative logic AND circuit 26 of the frequency divider 11 without adjusting the clock skew again, thereby supplying a 1 MHz clock to the bit stream processing unit 3. It becomes possible. On the other hand, after the supply of the 1 MHz clock to the bit stream processing unit 3 is stopped, the supply of the 1 MHz clock to the bit stream processing unit 3 is not started again (No in S18). The high-level CLK_EN 23b is input to the logical AND circuit 26 (S17).
[0118]
Based on the above description, the clock skew is adjusted in the initial state of the electronic device according to the present invention, and after the clock skew is adjusted, the comparison of the skew is stopped, so that the counter value is saved. In the operating state of the electronic device, the supply of the divided clock frequency can be stopped. Further, by storing the counter value after the clock skew adjustment, it is not necessary to adjust the clock skew again, and the supply of the divided clock frequency can be resumed.
[0119]
【The invention's effect】
According to the above-described invention, it is possible to stop the supply of a predetermined clock at a predetermined timing.
[Brief description of the drawings]
FIG. 1 is a hardware block diagram of a portable electronic device.
FIG. 2 is a diagram showing a hardware configuration of a clock supply unit.
FIG. 3 is a diagram showing a hardware configuration of a frequency divider.
FIG. 4 is a diagram showing a process of generating a 1 MHz clock.
FIG. 5 is a diagram illustrating a process of generating a signal DLY_EN that is a 1 MHz clock;
FIG. 6 is a diagram showing a hardware configuration of a clock comparison unit.
FIG. 7 is a diagram comparing the waveform of a 13 MHz clock signal with the waveform of a 1 MHz clock signal.
FIG. 8 is a diagram illustrating generation of a signal to be compared using an FF.
FIG. 9 is a diagram illustrating comparison of signals by an EXOR circuit.
FIG. 10 is a diagram showing that a signal is generated by a negative logic AND circuit;
FIG. 11 is a diagram illustrating generation of UCLK when a RESET signal is in a low state.
FIG. 12 is a diagram illustrating generation of UCLK when a RESET signal is in a high state.
FIG. 13 is a diagram illustrating generation of a signal to be compared using an FF.
FIG. 14 is a diagram illustrating comparison of signals by an EXOR circuit.
FIG. 15 is a diagram showing generation of a signal by a negative logic AND circuit;
FIG. 16 is a diagram showing that DCLK is generated when a RESET signal is in a Low state.
FIG. 17 is a diagram illustrating generation of DCLK when a RESET signal is in a high state.
FIG. 18 is a diagram comparing the waveform of a 13 MHz clock signal with the waveform of a 1 MHz clock signal.
FIG. 19 is a diagram illustrating generation of a signal to be compared using an FF.
FIG. 20 is a diagram illustrating comparison of signals by an EXOR circuit.
FIG. 21 is a diagram showing that a signal is generated by a negative logic AND circuit;
FIG. 22 is a diagram illustrating generation of UCLK when a RESET signal is in a Low state.
FIG. 23 is a diagram illustrating generation of UCLK when a RESET signal is in a high state.
FIG. 24 is a diagram illustrating generation of a signal to be compared using an FF.
FIG. 25 is a diagram showing comparison of signals by an EXOR circuit.
FIG. 26 is a diagram showing that a signal is generated by a negative logic AND circuit;
FIG. 27 is a diagram showing that DCLK is generated when a RESET signal is in a Low state.
FIG. 28 is a diagram showing that DCLK is generated when a RESET signal is in a high state.
FIG. 29 is a flowchart for explaining a clock skew adjustment procedure;
FIG. 30 is a flowchart illustrating a procedure for adjusting clock skew.
FIG. 31 is a flowchart illustrating a procedure for controlling generation of a 1 MHz clock when the electronic apparatus according to the invention is in an operating state;
[Explanation of symbols]
1 ... CPU, 2 ... memory, 3 ... bitstream generation unit, 4 ... DMAC,
5 ... Clock supply unit, 6 ... Wireless module, 10 ... Original oscillation unit, 11 ... Frequency division unit,
12 ... Clock comparison unit, 13 ... Up / down counter, 14 ... Multiplexer,
15 ... Delay element, 20 ... Synchronous clear counter,
21, 31, 36 ... NOT circuit, 22 ... NAND circuit,
23, 25, 26, 34, 39, 40, 41, ... negative logic AND circuit,
24, 30, 32, 35, 37 ... flip-flop (FF),
33, 38 ... EXOR circuit,

Claims (7)

A clock generator for generating a first clock;
A frequency divider that divides the first clock to generate a second clock;
A predetermined delay time inserted into the first clock by comparing the skew between the first clock generated by the clock generator and the second clock divided by the divider A delay element for generating a quantity;
A stop signal that is input to the frequency divider and stops the generation of the second clock;
Inserting the predetermined delay time amount generated by the delay element into the first clock to adjust a skew with the second clock, and then inputting the stop signal to the frequency divider. Then, the clock supply device stops generating the second clock. A start signal that is input to the frequency divider and starts generating the second clock;
The generation of the second clock is stopped by inputting the stop signal to the frequency divider, and then the generation of the second clock is started by inputting the start signal to the frequency divider. The clock supply device according to claim 1, wherein: A clock generator for generating a first clock;
A frequency divider that divides the first clock to generate a second clock;
A clock comparison unit for comparing a skew between the first clock generated by the clock generation unit and the second clock divided by the frequency division unit;
A delay element that generates a predetermined amount of time to be inserted into the first clock based on a result of comparing the first clock and the second clock by the clock comparison unit;
A first stop signal that is input to the frequency divider and stops generating the second clock;
A second stop signal that is input to the clock comparison unit and stops the comparison between the first clock and the second clock;
After adjusting the skew with the second clock by inserting the predetermined amount of delay time generated by the delay element into the first clock, the second stop signal is sent to the clock comparison unit. The comparison between the first clock and the second clock is stopped by inputting, and the generation of the second clock is stopped by inputting the first stop signal to the frequency divider. A clock supply device. A start signal that is input to the frequency divider and starts generating the second clock;
By stopping the generation of the second clock by inputting the first stop signal to the frequency divider, and by inputting the start signal to the frequency divider, 4. The clock supply device according to claim 3, wherein generation is started. Generate a first clock,
Generating a second clock by dividing the first clock;
By comparing the skew between the first clock and the second clock, a predetermined amount of delay time inserted into the first clock is generated,
The skew between the first clock and the second clock is adjusted by inserting the generated predetermined delay time amount into the first clock,
A clock generation control method characterized by stopping generation of the second clock after adjusting a skew between the first clock and the second clock. Generate a first clock,
Generating a second clock by dividing the first clock;
By comparing the skew between the first clock and the second clock, a predetermined amount of delay time inserted into the first clock is generated,
The skew between the first clock and the second clock is adjusted by inserting the generated predetermined delay time amount into the first clock,
After the adjustment, a skew comparison between the first clock and the second clock is stopped, and generation of the second clock is further stopped. 7. The clock supply device according to claim 5, wherein the generation of the second clock is started after the generation of the second clock is stopped.

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