JP2005020284A - Phase-shifter circuit and phase shifter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a phase shifter circuit and a phase shifter small in size and not easily influenced by the variations in manufacturing. <P>SOLUTION: The phase shifter circuit comprises the serial circuit of an FET 4 which shows a capacitive property under the OFF state, and an inductor 8 connected in series to this FET4, to connect one terminal of the serial circuit to a high frequency signal input/output terminal 2, and then to connect the other terminal to the ground 9. Moreover, this phase shifter circuit is connected to a 90° hybrid coupler having a high frequency input terminal and a high frequency output terminal to form a phase shifter. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a phase shift circuit and a phase shifter having a small and broadband phase shift amount characteristic.
[0002]
[Prior art]
As a conventional phase shift circuit, a series circuit of an inductor and a field effect transistor (hereinafter abbreviated as FET) is provided between a high-frequency signal input / output terminal and a ground, and a capacitor is connected in parallel to the series circuit. Yes (for example, see Non-Patent Document 1).
[0003]
In a conventional phase shift circuit, the FET operates as a switch for switching between an on state and an off state. When a gate voltage having the same potential as the drain voltage and the source voltage of the FET is applied to the bias terminal, the FET is turned on and has resistance ( Hereinafter, the on-resistance is indicated. On the other hand, when a gate voltage equal to or lower than the pinch-off voltage is applied to the bias terminal, the FET is turned off and exhibits capacitance (hereinafter referred to as off-capacitance).
[0004]
If the on-resistance of the FET is sufficiently small, the conventional phase shift circuit can be regarded as a parallel LC circuit composed of an inductor and a capacitor, and the signal input from the high-frequency signal input / output terminal is phase-shifted by the parallel LC circuit. Rotation occurs and the light is reflected and output from the high-frequency signal input / output terminal.
[0005]
On the other hand, when the FET is turned off, assuming that the admittance exhibited by the capacitor is sufficiently small, the conventional phase shift circuit can be regarded as a series LC circuit composed of an inductor and off-capacitance, and from the high-frequency signal input / output terminal The input signal undergoes phase rotation by the serial LC circuit, is reflected, and is output from the high-frequency signal input / output terminal.
[0006]
By setting the difference between the reflection phase generated by the parallel LC circuit and the reflection phase generated by the series LC circuit as a required phase shift amount, the signal input from the high-frequency signal input / output terminal switches the on / off state of the FET As a result, a desired phase shift amount is obtained and reflected and output from the high-frequency signal input / output terminal.
[0007]
[Non-Patent Document 1]
IEICE Technical Report, MW 2002-56, pp. 27-31, 2002
[0008]
[Problems to be solved by the invention]
As described above, the conventional phase shift circuit has a configuration in which three circuit elements are required, and thus there is a problem that the circuit becomes large. Further, there is a problem that the amount of phase shift obtained by the manufactured phase shift circuit is likely to deviate from a desired value due to manufacturing variations of capacitors.
[0009]
The present invention has been made to solve the above-described problems, and an object of the present invention is to realize a phase shift circuit and a phase shifter that are small in size and hardly affected by manufacturing variations.
[0010]
[Means for Solving the Problems]
A phase shift circuit according to the present invention includes a series circuit of a switching element that exhibits capacitance when turned off, and an inductor connected in series to the switching element, and one end of the series circuit is connected to a high-frequency signal input / output terminal, The other end is connected to the ground.
[0011]
The phase shifter according to the present invention is characterized in that the phase shift circuit is connected to a 90 ° hybrid coupler having a high frequency signal input terminal and a high frequency signal output terminal.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
1 is a block diagram showing a phase shift circuit according to Embodiment 1 of the present invention. The phase shift circuit shown in FIG. 1 is configured monolithically on a semiconductor substrate 1, and a spiral inductor 3, an FET 4, and a high-frequency signal input / output terminal 2 formed on the semiconductor substrate 1 and a through hole 5. The gate of the FET 4 is connected to the bias terminal 7 through the resistor 6.
[0013]
FIG. 2 is an equivalent circuit diagram of the phase shift circuit shown in FIG. In the equivalent circuit diagram shown in FIG. 2, the same or corresponding components as those in FIG. As new symbols, 8 is an inductor corresponding to the spiral inductor 3, and 9 is a ground corresponding to the through hole 5.
[0014]
Here, the FET 4 operates as a switch for switching the on / off state. The bias terminal 7 is connected to the gate electrode of the FET 4. When a gate voltage having the same potential as the drain voltage and source voltage of the FET 4 is applied to the bias terminal 7, the FET 4 is turned on and exhibits resistance (hereinafter referred to as on-resistance). On the other hand, when a gate voltage equal to or lower than the pinch-off voltage is applied to the bias terminal 7, the FET 4 is turned off and exhibits capacitance (hereinafter referred to as off-capacitance).
[0015]
Next, the operation of FIG. 1 will be described with reference to FIG. 2 which is an equivalent circuit of FIG. FIG. 3 shows an equivalent circuit diagram of FIG. 1 when the FET 4 is on. Reference numeral 10 denotes an on-resistance of the FET 4. Here, if the on-resistance 10 is sufficiently small, the circuit shown in FIG. 3 can be regarded as a circuit including the inductor 8. Therefore, the signal input from the high-frequency signal input / output terminal 2 is reflected by the phase rotation caused by the inductor 8 and is output from the high-frequency signal input / output terminal 2.
[0016]
FIG. 4 shows an equivalent circuit diagram of FIG. 1 when the FET 4 is in an OFF state. Reference numeral 11 denotes an off capacitance of the FET 4. The circuit shown in FIG. 4 can be regarded as a series LC circuit including an inductor 8 and an off-capacitance 11. Therefore, the signal input from the high frequency signal input / output terminal 2 is reflected by the phase rotation generated by the serial LC circuit, and is output from the high frequency signal input / output terminal 2.
[0017]
As described above, the phase shift circuit of the first embodiment shown in FIG. 1 switches the inductor and the serial LC circuit by the on / off switching operation of the FET 4 and the signal input from the high frequency signal input / output terminal 2 is reflected. The amount of phase rotation generated in is changed.
[0018]
Therefore, according to the phase shift circuit according to the first embodiment, if the inductance of the inductor 8 and the capacitance of the off-capacitance 11 are appropriately set, a desired phase shift amount can be obtained from the difference in the phase rotation amount. That is, since a phase shift circuit can be configured with one FET and one inductor, the number of capacitors can be reduced as compared with the conventional example, and the size can be reduced.
[0019]
Further, since no capacitor is used, it is possible to eliminate a deviation from a desired value of the amount of phase shift due to manufacturing variations of the capacitor.
[0020]
In the phase shift circuit according to the first embodiment shown in FIG. 1, the FET 4 is used as a switching element. However, any type can be used as long as it has a switching function capable of switching the on / off state. But you can.
[0021]
In addition, the phase shift circuit according to the first embodiment shown in FIG. 1 is monolithically formed on the semiconductor substrate 1, but the passive element is formed on the dielectric substrate, the active element is formed on the semiconductor substrate, and the metal wire is formed. Alternatively, the phase shift circuit may be configured by electrically connecting both substrates with gold bumps or the like.
[0022]
Embodiment 2. FIG.
FIG. 5 is a diagram showing the configuration of the phase shift circuit according to the second embodiment of the present invention. About the structure which is the same as that of FIG. 1, FIG. 2, or equivalent, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted. As a new code, 12 is a resistor. The phase shift circuit according to the second embodiment is obtained by connecting a resistor 12 in parallel to a series circuit including an inductor 8 and an FET 4 in FIG. 2 showing the configuration of the phase shift circuit according to the first embodiment.
[0023]
Next, the operation of the phase shift circuit according to the second embodiment having the above configuration will be described. When the FET 4 is in the on state, the circuit shown in FIG. 5 can be regarded as a circuit including the inductor 8 as in the first embodiment. Further, when the FET 4 is in the off state, the circuit shown in FIG. 5 can be regarded as a series LC circuit including the inductor 8 and the off-capacitance 11 as in the first embodiment. At that time, the resistor 12 reduces the difference between the amount of attenuation when operated as the inductor 8 and the amount of attenuation when operated as the series LC circuit.
[0024]
Therefore, according to the phase shift circuit according to the second embodiment, the same effect as that of the first embodiment can be obtained, and the FET 4 is turned on to operate as an inductor by appropriately setting the resistor 12. In this case, the difference between the amount of attenuation and the amount of attenuation when the FET 4 is turned off and operated as a series LC circuit can be reduced, and level compensation of the high-frequency output signal can be easily realized.
[0025]
In the phase shift circuit according to the second embodiment shown in FIG. 5, the FET 4 is used as a switch. However, any type can be used as long as it has a switching function capable of switching the on / off state. Good.
[0026]
Further, the phase shift circuit according to the second embodiment shown in FIG. 5 is monolithically formed on the semiconductor substrate 1, but the passive element is formed on the dielectric substrate, the active element is formed on the semiconductor substrate, and the metal wire is formed. Alternatively, the phase shift circuit may be configured by electrically connecting both substrates with gold bumps or the like.
[0027]
Embodiment 3 FIG.
Phase shift circuit according to the first embodiment shown in FIG. 2, the phase shift circuit according to the second embodiment shown in FIG. 5, placing the inductance of the inductor 8 L, the capacitance of the off capacitance 11 and C _1. With the characteristic impedance of the high-frequency signal input / output terminal 2 as Z ₀ , a phase shift circuit that satisfies Equation (1) is configured.
Z ₀ = (L / C ₁ ) ^1/2 ... (1)
[0028]
Next, the operation of the phase shift circuit according to the third embodiment will be described. When the reflection phase of the inductor is φ1 and the reflection phase of the series LC circuit is φ2, the phase shift amount Φ is represented by the difference between the reflection phases of both circuits, and Φ = φ1−φ2. If the differential coefficient of the phase shift amount with respect to the frequency becomes zero, the phase shift amount becomes constant at all frequencies. That is, dΦ / dω = d (φ1-φ2) / dω = 0 may be satisfied at all frequencies. The solution satisfying the conditional expression is expressed by Expression (1) if the intermediate expression is omitted. At this time, in the series LC circuit, the reactance due to the inductor 8 is ignored, assuming that the reactance due to the off-capacitance 11 is sufficiently larger than the reactance due to the inductor 8.
[0029]
In DC, since the circuit composed of the inductor is in a short circuit state, the reflection phase is zero. Since the series LC circuit is in an open state, the reflection phase is delayed by 180 °. Therefore, in DC, the difference between the reflection phases of both circuits, that is, the amount of phase shift is 180 °. Furthermore, if the expression (1) is satisfied, the phase shift amount is constant at 180 ° at all frequencies.
[0030]
Therefore, according to the phase shift circuit according to the third embodiment, the same effect as in the first or second embodiment can be obtained, and by satisfying the formula (1), the phase shift amount can be 180 ° in a wide frequency range. realizable.
[0031]
Embodiment 4 FIG.
Phase shift circuit according to the first embodiment shown in FIG. 2, the phase shift circuit according to the second embodiment shown in FIG. 5, placing the inductance of the inductor 8 L, the capacitance of the off capacitance 11 and C _1. With the characteristic impedance of the high-frequency signal input / output terminal 2 as Z ₀ , a phase shift circuit that satisfies Equation (2) is configured.
Z ₀ <(L / C ₁ ) ^1/2 ... (2)
[0032]
Next, the operation of the phase shift circuit according to the fourth embodiment will be described. When the reflection phase of the inductor is φ3 and the reflection phase of the series LC circuit is φ4, the phase shift amount Φ is expressed by the difference between the reflection phases of both circuits, and Φ = φ3−φ4. When the differential coefficient of the phase shift amount with respect to the frequency becomes zero, the phase shift amount becomes constant at all frequencies. That is, dΦ / dω = d (φ3-φ4) / dω = 0 may be satisfied at all frequencies. As in the third embodiment, the solution satisfying the conditional expression is represented by expression (1) if the intermediate expression is omitted. At this time, in the series LC circuit, the reactance due to the inductor 8 is ignored, assuming that the reactance due to the off-capacitance 11 is sufficiently larger than the reactance due to the inductor 8.
[0033]
In DC, since the circuit composed of the inductor is in a short circuit state, the reflection phase is zero. Since the series LC circuit is in an open state, the reflection phase is delayed by 180 °. Therefore, in DC, the difference between the reflection phases of both circuits, that is, the amount of phase shift is 180 °.
[0034]
Actually, when the frequency increases, the reactance due to the inductor 8 cannot be ignored, and the phase shift amount deviates from 180 °. Therefore, by decreasing the C _1, the reactance due to the inductor 8 also is set to be sufficiently smaller than the reactance due to the off capacity 11 at high frequencies. At this time, the inductance L of the inductor 8 and the capacitance C ₁ of the off-capacitance 11 satisfy Expression (2).
[0035]
When Expression (2) is satisfied, dΦ / dω = 0 at the frequency fu = ((L / C ₁ −Z ₀ ² ) / 3L ² ) ^1/2 / 2π. At this time, dΦ / dω> 0 when 0 <f <fu, dΦ / dω = 0 when f = fu, and dΦ / dω <0 when fu <f. That is, the phase shift amount is 180 ° at f = 0 and fu2 (fu2> f).
[0036]
Therefore, according to the phase shift circuit according to the fourth embodiment, the same effect as in the third embodiment can be obtained, and a phase shift amount of 180 ° can be realized in a wide frequency range by satisfying the equation (2). .
[0037]
Embodiment 5 FIG.
6 is a block diagram showing a configuration of a phase shifter according to Embodiment 5 of the present invention. The phase shifter shown in FIG. 6 applies the phase shift circuit described in any of the first to fourth embodiments as the reflective termination circuit 16 (generally referred to as 16a and 16b). Is connected to a 90 ° hybrid coupler 15 having a high-frequency signal input terminal 13 and a high-frequency signal output terminal 14.
[0038]
Next, the operation of the phase shifter according to the fifth embodiment will be described. A high frequency signal is input to the 90 ° hybrid coupler 15 from the high frequency signal input terminal 13. A signal having the same phase as the high-frequency signal input to the 90 ° hybrid coupler 15 is input to the reflective termination circuit 16a, and a signal delayed by 90 ° is input to the reflective termination circuit 16b. High-frequency signals whose phases are different from each other by 90 ° are reflected by the reflective termination circuits 16a and 16b, respectively, with a desired phase rotation.
[0039]
The reflected high frequency signal is input to the 90 ° hybrid coupler 15 again. At the high-frequency signal input terminal 13, the signals reflected by the reflective termination circuits 16 a and 16 b are different from each other by 180 °, so that no output appears. At the high-frequency signal output terminal 14, the reflective termination circuits 16 a and 16 b Since the reflected signals are in phase, they are combined and output.
[0040]
Here, the phase shift circuit described in any of the first to third embodiments is applied to the reflective termination circuits 16a and 16b, and by simultaneously switching the states of the reflective termination circuits 16a and 16b, A desired amount of phase shift is obtained from the difference in reflection phase in each state. Thereby, the input signal and the output signal can be separated, and only the signal reflected by the reflective termination circuit 16 can be taken out as an output signal.
[0041]
Therefore, according to the phase shifter according to the fifth embodiment, it is possible to configure a 1-bit phase shifter that uses only the signal reflected by the reflective termination circuit 16 as an output signal.
[0042]
Note that the phase shifter according to the fifth embodiment shown in FIG. 6 may be configured monolithically on a semiconductor substrate. Alternatively, a passive element and a 90 ° hybrid coupler may be configured on a dielectric substrate, an active element may be configured on a semiconductor substrate, and the two substrates may be electrically connected with metal wires or gold bumps to configure a phase shifter. .
[0043]
Embodiment 6 FIG.
FIG. 7 is a diagram showing a configuration of a phase shifter according to Embodiment 6 of the present invention. The phase shifter shown in FIG. 7 is configured by applying the phase shifter according to the fifth embodiment as the 1-bit phase shifter 17 and connecting a plurality of phase shifters 17 in multiple stages. About the structure which is the same as that of FIG. 6, or equivalent, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted. By constructing a phase shifter by connecting the 1-bit phase shifter 17 in multiple stages, a phase shifter that operates in multiple bits can be realized.
[0044]
Note that the phase shifter according to the sixth embodiment shown in FIG. 7 may be monolithically configured on a semiconductor substrate. Alternatively, a passive element and a 90 ° hybrid coupler may be configured on a dielectric substrate, an active element may be configured on a semiconductor substrate, and the two substrates may be electrically connected with metal wires or gold bumps to configure a phase shifter. .
[0045]
【The invention's effect】
As described above, according to the present invention, it is possible to realize a phase shift circuit and a phase shifter that are small in size and hardly affected by manufacturing variations.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a phase shift circuit according to a first embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram showing a configuration of a phase shift circuit according to the first embodiment of the present invention.
FIG. 3 is an equivalent circuit diagram when the FET 4 of the phase shift circuit according to the first embodiment of the present invention is turned on.
FIG. 4 is an equivalent circuit diagram when the FET 4 of the phase shift circuit according to the first embodiment of the present invention is turned off.
FIG. 5 is a circuit diagram showing a configuration of a phase shift circuit according to a second embodiment of the present invention.
FIG. 6 is a circuit diagram showing a configuration of a phase shifter according to a fifth embodiment of the present invention.
FIG. 7 is a circuit diagram showing a configuration of a phase shifter according to Embodiment 6 of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 High frequency signal input / output terminal, 3 Spiral inductor, 4FET, 5 Through hole, 6 Resistance, 7 Bias terminal, 8 Inductor, 9 Ground, 10 On resistance, 11 Off capacity, 12 Capacitor, 13 High frequency signal input terminal , 14 High-frequency signal output terminal, 15 90 ° hybrid coupler, 16 Reflective termination circuit, 17 Phase shifter.

Claims (6)

It has a series circuit of a switching element that exhibits capacitance when turned off and an inductor connected in series to the switching element, and one end of the series circuit is connected to the high-frequency signal input / output terminal and the other end is connected to the ground. A phase shift circuit. The phase shift circuit according to claim 1,
A phase shift circuit, wherein a resistor is connected in parallel to a series circuit of the switching element and the inductor. The phase shift circuit according to claim 1 or 2,
The inductance of the inductor L, when the OFF-time capacity of the switching element is a C _1, the characteristic impedance Z ₀ of the high frequency signal input and output terminals,
Z ₀ = (L / C ₁ ) ^1/2
A phase shift circuit characterized by satisfying The phase shift circuit according to claim 1 or 2,
The inductance of the inductor L, when the OFF-time capacity of the switching element is a C _1, the characteristic impedance Z ₀ of the high frequency signal input and output terminals,
Z ₀ <(L / C ₁ ) ^1/2
A phase shift circuit characterized by satisfying 5. A phase shifter, wherein the phase shift circuit according to claim 1 is connected to a 90 ° hybrid coupler having a high frequency signal input terminal and a high frequency signal output terminal. 6. The phase shifter according to claim 5, wherein the high-frequency signal input terminal and the high-frequency signal output terminal are connected to each other in multiple stages.

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