JP2005012560A - Microwave amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microwave amplifier circuit easily designed and preventive in a cause to a fault and a malfunction so as to stably maintain performance. <P>SOLUTION: The microwave amplifier circuit configured by connecting FETs in multi-stages includes: a first gate bias line 16 whose one end is connected to a first gate circuit 15 of a first stage FET 12 and whose other end is connected to a bias terminal 19; a second gate bias line 25 whose one end is connected to a gate circuit of a next-stage FET 14 and whose other end is connected to the bias terminal 19; and a damping resistor 20 connected to the first gate bias line 16. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microwave amplifier circuit using an FET (field effect transistor), and more particularly to a microwave amplifier circuit that facilitates performance improvement and design by preventing malfunction.
[0002]
[Prior art]
A high-frequency signal applied to a moving body such as a radio communication apparatus or a radar apparatus, for example, a transmission side output stage of a transmission / reception apparatus using high-frequency or microwaves, is a MOSFET (Metal Oxide Field Field-Effect-Transistor) or a GaAs-MESFET. A multi-stage microwave amplifier circuit, for example, a high-frequency power amplifier circuit, which is dependent on a semiconductor amplifier element, is incorporated.
[0003]
This type of high-frequency power amplifier circuit is disclosed in Japanese Patent Laid-Open No. 2003-37454 (see Patent Document 1).
[0004]
According to Patent Document 1, as shown in FIG. 4 of the accompanying drawings, a high-frequency power amplifier circuit 1 having a multistage configuration in which a plurality of semiconductor elements are cascade-connected is shown.
[0005]
The high-frequency power amplifier circuit 1 has a circuit configuration in which FETs (electrolytic effect transistors) Q1, Q2, and Q3 are cascade-connected in three stages.
[0006]
This circuit configuration is a three-stage configuration in which the gate terminal of the middle stage FET Q2 is connected to the drain terminal of the first stage FET Q1, and the gate terminal of the last stage FET Q3 is connected to the drain terminal of the middle stage FET Q2.
[0007]
The high frequency power amplifier circuit 1 is effective when used as a high frequency power amplifier circuit for a cellular phone as a wireless communication device.
[0008]
The final stage FET Q3 is composed of discrete components (such as output power MOSFET), and the first and middle stage FETs Q1 and Q2 and the bias control circuit 2 are configured as a semiconductor integrated circuit on one semiconductor chip.
[0009]
Capacitors c1 to c4 are connected as external elements.
[0010]
In the high frequency power amplifier circuit 1, the input terminal Pin is connected to the gate terminal of the first stage FET Q1 via the capacitive element C1, a high frequency signal is input to the gate terminal from the input terminal Pin, and the drain terminal of the final stage FET Q3 is the capacitive element. It is connected to the output terminal Pout via C4, cuts the DC component of the high-frequency signal, amplifies the AC component, and outputs it.
[0011]
The output power at this time is controlled by the bias control circuit 2.
[0012]
In FIG. 1, symbols SM <b> 1 to SM <b> 6 are microstrip lines that function as inductance elements for matching impedance between the respective stages, and each of the microstrip lines SM <b> 1 to SM <b> 6 is a semiconductor including a bias control circuit 2. It is composed of a conductive layer pattern such as copper formed on the ceramic substrate on which the chip is mounted so as to have a desired inductance value.
[0013]
Capacitors C1 to C4 connected in series with the microstrip lines SM1 to SM6 have a function of cutting off the DC voltages of the power supply voltages (Vdd1 to Vdd3) and the gate bias voltages (Vg1 to Vg3).
[0014]
In the GSM wireless communication apparatus, the bias control circuit 2 includes a control terminal to which the power control signal voltage Vapc output from the automatic power control circuit is input, and gate bias voltages (Vg1 to Vg3) of the output FETs Q1 to Q3. Is provided.
[0015]
The resistors R1, R2, and R3 provided between the output terminal of the bias control circuit 2 and the gate terminals of the FETs Q1 to Q3 are for preventing the high frequency signal from leaking to the bias control circuit 2.
[0016]
[Patent Document 1]
JP 2003-37454 A (page 6, left column, line 28 to right column, line 27 and FIG. 1)
[0017]
[Problems to be solved by the invention]
According to Patent Document 1, the bias control circuit 2 is configured to generate a bias voltage in each of the first to final stage FETs Q1 to Q3.
[0018]
The bias control circuit 2 can control the gate bias voltage for each of the first-stage FET to the final-stage FET Q1 to Q3, thereby controlling the power of the high-frequency signal input from the input terminal Pin and outputting it from the output terminal Pout.
[0019]
However, since the resistance values of the resistors R1 to R3 are made constant and the outputs of the gate bias voltages Vg1 to Vg3 on the bias control circuit 2 side are switched and connected, the gate bias control circuit 2 is set one by one. The switching control must be performed, and the configuration of the bias control circuit itself for controlling the gate bias voltage is complicated and not easy to design, but it may cause failure or malfunction. .
[0020]
The present invention has been made in consideration of the above points, and does not require a gate bias control circuit, is easy to design, and prevents the cause of a failure or malfunction and maintains and improves the performance stably. An object is to provide a circuit.
[0021]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, in the microwave amplifier circuit configured by connecting a plurality of FETs in multiple stages between the high-frequency signal input terminal and the output terminal, the gate circuit of the first-stage FET is used. A first gate bias line in which one is connected and the other is connected to the bias terminal side, and a second gate bias line in which one is connected to the gate circuit of the next stage FET and the other is connected to the bias terminal side The first gate bias line is provided with a damping resistor that prevents a high-frequency signal from the input terminal side from leaking to the bias terminal side.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of a microwave amplifier circuit according to the present invention will be described with reference to the accompanying drawings.
[0023]
(First embodiment)
FIG. 1 is a schematic diagram showing a first embodiment of a microwave amplifier circuit according to the present invention.
[0024]
The microwave amplifier circuit of the present invention can be applied to a high-frequency power amplifier circuit 10 applied to a radar apparatus mounted on a moving body such as an aircraft.
[0025]
The high-frequency power amplifier circuit 10 has an amplifier circuit configuration in which FETs (electrolytic effect transistors) are connected in cascade.
[0026]
The high-frequency power amplifier circuit 10 has a multi-stage circuit configuration in which, for example, a first stage FET 12 provided on the input terminal 11 side and a next stage FET 14 provided on the output terminal 13 side are sequentially connected as active elements.
[0027]
It has a two-stage configuration in which the gate terminal of the next stage FET 14 is connected to the drain terminal of the first stage FET 12.
[0028]
On the gate terminal 12 a side of the first stage FET 12, a first gate circuit 15 and a first gate bias line 16 connected to the first gate circuit 15 are provided.
[0029]
In the first gate circuit 15, one end of a series circuit of the inductor 17 and the capacitor 18 is connected to the gate terminal 12 a of the first stage FET 12, and the other end side is grounded.
[0030]
One of the first gate bias lines 16 is connected between the inductor 17 and the capacitor 18 of the first gate circuit 15 and the other is connected to the bias terminal 19 side.
[0031]
The first gate bias line 16 is provided with a damping resistor 20.
[0032]
The damping resistor 20 is provided to prevent or attenuate a high frequency signal output from the input terminal 11 side to the bias terminal 19 side.
[0033]
Further, by providing the damping resistor 20 in the first gate bias line 16, the gate bias voltage can be kept low.
[0034]
For example, in the relationship between the gate bias voltage (V) and the gain on the amplifier circuit side, as shown in FIG. 2, normally, in order to obtain a predetermined high-frequency signal amplification characteristic, a region indicated by a solid line a is obtained. Become.
[0035]
That is, when the gate bias voltage (V) becomes a specified value or less due to voltage fluctuation, the gain can be suppressed.
[0036]
That is, in the relatively low voltage region of the gate bias voltage (V), as shown by the solid line a1, the high gain state is changed to the relatively low gain state as shown by the dotted line b.
[0037]
As described above, when the gate bias voltage fluctuates in the decreasing direction as a result of suppressing the gain, it is possible to reduce the influence of the malfunction caused by the gain increase outside the range of the specified operating characteristics.
[0038]
The second stage FET 14 is provided with a second gate circuit 24 and a second gate bias line 25 connected to the second gate circuit 24.
[0039]
In the second gate circuit 24, one end of the series circuit of the inductor 26 and the capacitor 27 is connected to the gate terminal 14a of the next stage FET 14, and the other end side is grounded.
[0040]
One of the second gate bias lines 25 is connected to the lower side of the inductor 26 connected to the second gate circuit 24, and the other is connected to the bias terminal 19 side.
[0041]
The first-stage FET 12 and the next-stage FET 14 provided in multiple stages are composed of, for example, discrete components (such as output power MOSFET).
[0042]
The first stage FET 12 and the next stage FET 14 are configured as a semiconductor integrated circuit (not shown) on one semiconductor chip together with the first gate bias line 16 and the second gate bias line 25.
[0043]
Next, the operation of the high-frequency power amplifier circuit 10 will be described with reference to FIG.
[0044]
A high frequency signal input from the upper transmission line (not shown) side through the input terminal 11 is temporarily amplified from the first stage FET 12 through the next stage FET 14 to be amplified from the output terminal 13 to the lower transmission line (not shown). To be sent).
[0045]
The steps from the input terminal 11 to the output terminal 13 until the high frequency signal is amplified and output by the first stage FET 12 and the next stage FET 14 will be described.
[0046]
When a high-frequency signal input from the input terminal 11 side is input to the gate terminal 12a side of the first stage FET 12, a gate bias having a predetermined potential is applied to the gate terminal 12a side of the first stage FET 12 by the first gate circuit 15 and the first gate bias line 16. A voltage is applied.
[0047]
By applying the gate bias voltage at the predetermined potential, the first-stage FET 12 operates, amplifies the high-frequency signal with a predetermined output, and outputs it to the next-stage FET 14 side.
[0048]
At this time, due to the damping action by the damping resistor 20 of the first gate bias line 16, the high frequency signal on the bias terminal 19 side suppresses leakage.
[0049]
Thereby, the first stage FET 12 operates in a state where a predetermined gate bias voltage is maintained.
[0050]
Here, when the gate bias voltage fluctuates to a low voltage region below the specified value, the effect of malfunction is reduced because the gain of the amplifier circuit is relatively low <step 1>.
[0051]
When the first stage FET 12 is activated, it is amplified to a predetermined high frequency signal from the output terminal (drain) side and output.
[0052]
The amplified high frequency signal is input to the gate terminal 14a side of the next stage FET14.
[0053]
On the other hand, a gate bias voltage having a predetermined potential is applied to the gate terminal side by the second gate circuit 24 and the second gate bias line 25.
[0054]
By applying the gate bias voltage, the next stage FET 14 operates in a predetermined operation state <Step 2>.
[0055]
When the next stage FET 14 operates in a predetermined operating state, a predetermined high-frequency signal is amplified to a predetermined value from the output terminal (drain) side and output from the output terminal 13 side <Step 3>.
[0056]
As described above, the high-frequency signal having a predetermined current (voltage) value input from the input terminal 11 side through <Step 1> to <Step 3> is output as the high-frequency signal amplified to the predetermined value. Can be output from.
[0057]
In the high frequency power amplifier circuit 10 according to the present invention, since the damping resistance 20 is provided in the first gate bias line 16, it is not necessary to control the bias voltage (V) from the bias terminal 19 side, and the first gate bias line 16. Thus, the first stage FET 12 can be stably operated without causing any abnormality in the bias control.
[0058]
In addition, stable operating characteristics can be obtained with the first stage FET 12, while on the second gate bias line 25 side, the effect of suppressing high-frequency signal leakage by the damping resistor 20 provided in the first gate bias line 16 is affected. By receiving it, the desired operating characteristics can be obtained.
[0059]
Furthermore, in the high frequency power amplifier circuit 10 of the present invention, the first gate bias line 16 and the second gate bias line 25 include the bias terminal 19 for supplying a common bias voltage. There is no need to provide a bias terminal 19 (bias voltage output device) for each FET 14, and the configuration on the bias terminal side can be simplified.
[0060]
Therefore, it is easy to design and can contribute to the prevention of failure and malfunction, while the performance can be stably maintained and improved.
[0061]
(Second Embodiment)
Next, a second embodiment of the microwave amplifier circuit according to the present invention will be described with reference to FIG.
[0062]
FIG. 3 shows an example in which the microwave amplifier circuit of the present invention is implemented as the high-frequency power amplifier circuit 30.
[0063]
The high-frequency power amplifier circuit 30 is a high-frequency power amplifier circuit with further improved performance compared to the high-frequency power amplifier circuit 10 in the first embodiment.
[0064]
The high-frequency power amplifier circuit 30 will be described by attaching the same reference numerals to the same portions as those in FIG. 1 in the first embodiment.
[0065]
An amplifier circuit configuration in which FETs (electrolytic effect transistors) 12 and 14 are cascade-connected in multiple stages is shown.
[0066]
This amplifier circuit configuration is a multistage circuit configuration in which, for example, a first stage FET 12 provided on the input terminal 11 side and a next stage FET 14 provided on the output terminal 13 side are sequentially connected as active elements.
[0067]
That is, it has a two-stage configuration in which the drain terminal of the first stage FET 12 is connected to the gate terminal of the next stage FET 14.
[0068]
On the first stage FET 12 side, a first gate circuit 15 and a first gate bias line 31 connected to the first gate circuit 15 are provided.
[0069]
In the first gate circuit 15, one end of a series circuit of the inductor 17 and the capacitor 18 is connected to the gate terminal 12 a of the first stage FET 12, and the other end side is grounded.
[0070]
One of the first gate bias lines 31 is connected to the lower side of the inductor 17 connected to the first gate circuit 15 and the other is connected to the bias terminal 19 side.
[0071]
A filter circuit 32 and a damping resistor 20 are connected in series to the first gate bias line 31.
[0072]
The filter circuit 32 is configured, for example, by connecting an inductor 34 and a capacitor 35, which are passive elements, in parallel.
[0073]
The filter circuit 32 has a characteristic of reducing only the amplifier gain in the low frequency band of the high frequency signal input on the input terminal 11 side.
[0074]
Further, by providing the damping resistor 20 in the first gate bias line 16, the gate bias voltage can be kept low.
[0075]
For example, in the relationship between the gate bias voltage (V) and the gain on the amplifier circuit side, when there is no damping resistor 20, normally, as shown in FIG. The area shown is obtained.
[0076]
However, by providing the damping resistor 20, the gain can be suppressed when the gate bias voltage (V) becomes a specified value or less due to voltage fluctuation.
[0077]
That is, in the relatively low voltage region of the gate bias voltage (V), as shown by the solid line a1, the high gain state is changed to the relatively low gain state as shown by the dotted line b.
[0078]
As described above, when the gate bias voltage fluctuates in the decreasing direction as a result of suppressing the gain, it is possible to reduce the influence of the malfunction caused by the gain increase outside the range of the specified operating characteristics.
[0079]
In addition, it has a characteristic of preventing the oscillation for suppressing the fluctuation of the output current (voltage) with respect to the first stage FET 12.
[0080]
Other configurations such as the next-stage FET 14 side are the same as the configurations shown in the first embodiment, and thus description thereof is omitted.
[0081]
Next, the operation of the high-frequency power amplifier circuit 30 of the present invention will be described with reference to FIG.
[0082]
A high frequency signal input from the upper transmission line (not shown) side through the input terminal 11 is temporarily amplified from the first stage FET 12 through the next stage FET 14 to be amplified from the output terminal 13 to the lower transmission line (not shown). To be sent).
[0083]
The steps from the input terminal 11 to the output terminal 13 until the high frequency signal is amplified and output by the first stage FET 12 and the next stage FET 14 will be described.
[0084]
When a high frequency signal input from the input terminal 11 side is input to the gate terminal side of the first stage FET 12, a gate bias voltage having a predetermined potential is applied to the first stage FET 12 side by the first gate circuit 15 and the first gate bias line 31. .
[0085]
By applying the gate bias voltage at the predetermined potential, the first-stage FET 12 operates, amplifies the high-frequency signal with a predetermined output, and outputs it to the next-stage FET 14 side.
[0086]
At this time, due to the damping action by the damping resistor 20 of the first gate bias line 31, the high frequency signal on the bias terminal 19 side suppresses leakage.
[0087]
Further, the operation of the first stage FET 12 is further stabilized by the amplifier gain lowering action in the low frequency band by the filter circuit 32 of the first gate bias line 31 and the gate bias side oscillation preventing action for the first stage FET 12, while the next stage FET 14 is more stable. A more stable operation is also performed on the side as a multistage amplifier circuit.
[0088]
Here, when the gate bias voltage fluctuates to a low voltage region below the specified value, the effect of malfunction is reduced because the gain of the amplifier circuit is relatively low <step 1>.
[0089]
When the first stage FET 12 is activated, it is amplified to a predetermined high frequency signal from the output terminal (drain) side and output.
[0090]
The amplified high frequency signal is input to the gate terminal 14a side of the next stage FET14.
[0091]
On the other hand, a gate bias voltage having a predetermined potential is applied to the gate terminal side by the second gate circuit 24 and the second gate bias line 25.
[0092]
By applying the gate bias voltage, the next stage FET 14 operates in a predetermined operation state <Step 2>.
[0093]
When the next stage FET 14 operates in a predetermined operating state, a predetermined high-frequency signal is amplified to a predetermined value from the output terminal (drain) side and output from the output terminal 13 side <Step 3>.
[0094]
As described above, the high-frequency signal having a predetermined current (voltage) value input from the input terminal 11 side through <Step 1> to <Step 3> is output as the high-frequency signal amplified to the predetermined value. Can be output from.
[0095]
Since the high-frequency power amplifier circuit 30 has a configuration in which the damping resistor 20 and the filter circuit 32 are provided in the first gate bias line 31, it is not necessary to control the bias voltage (V) from the bias terminal 19 side. The first stage FET 12 can be stably operated without causing any abnormality in the bias control by one gate bias line 31.
[0096]
Although the filter circuit 32 and the damping resistor 20 are directly connected to the first gate bias line 31, only the filter circuit 32 may be provided.
[0097]
In that case, it is also possible to adjust the resistance value of the resistor 34 of the filter circuit 32 so as to obtain a damping action.
[0098]
Further, as an alternative to the filter circuit 32 connected to the first gate bias line 31, a capacitor (not shown) having a predetermined capacitance value is connected in parallel with the damping resistor 20 so as to perform the filter action. You can also
[0099]
Further, stable operating characteristics can be obtained by the first stage FET 12, while the second gate bias line 25 side has an effect of suppressing the high frequency signal leakage by the damping resistor 20 provided in the first gate bias line 31. By receiving it, the desired operating characteristics can be obtained.
[0100]
Therefore, it is not necessary to control the bias voltage (V) from the bias terminal 19 side with respect to the first FET 12 and the second FET 14 side, and the high frequency power amplifier circuit can be operated as set (no malfunction).
[0101]
Further, since the filter circuit 32 is used on the first gate bias line 31 side, the effect of reducing the influence on the fluctuation of the gate bias voltage by the filter action that reduces only the amplifier gain in the low frequency band. Is obtained.
[0102]
Furthermore, in the high-frequency power amplifier circuit 30 of the present invention, the first gate bias line 31 and the second gate bias line 25 include the bias terminal 19 that supplies a common bias voltage. There is no need to provide a bias terminal 19 (bias voltage output device) for each FET 14, and the configuration on the bias terminal side can be simplified.
[0103]
Therefore, it is easy to design and can contribute to the prevention of failure and malfunction, while maintaining stable performance.
[0104]
【The invention's effect】
According to the present invention, it is possible to provide a microwave amplifier circuit that is easy to design and that can prevent failure and malfunction and maintain stable performance.
[Brief description of the drawings]
FIG. 1 is a schematic diagram of a high-frequency power amplifier circuit showing a first embodiment of the present invention.
2 is a graph showing a relationship between a gate bias voltage and an amplifier circuit gain in the high-frequency power amplifier circuit of FIG. 1;
FIG. 3 is a schematic diagram of a high-frequency power amplifier circuit showing a second embodiment of the present invention.
FIG. 4 is a schematic diagram of a conventional high-frequency power amplifier circuit.
[Explanation of symbols]
10, 30 High frequency power amplifier circuit (microwave amplifier circuit)
11 Input terminal 12 First stage FET
12a, 14a Gate terminal 13 Output terminal 14 Next stage FET
15 First gate circuit 16, 31 First gate bias line 17, 26 Inductor 18, 27, 35 Capacitor 19 Bias terminal 20 Damping resistor 24 Second gate circuit 25 Second gate bias line 32 Filter circuit 34 Resistance

Claims (3)

In a microwave amplifier circuit configured by connecting a plurality of FETs in multiple stages between a high-frequency signal input terminal and an output terminal,
A first gate bias line having one connected to the gate circuit side of the first stage FET and the other connected to the bias terminal side;
A second gate bias line in which one is connected to the gate circuit side of the next stage FET and the other is connected to the bias terminal side;
The microwave amplifying circuit according to claim 1, wherein the first gate bias line includes a damping resistor for preventing a high frequency signal from the input terminal side from leaking to the bias terminal side. The microwave amplifier circuit according to claim 1, wherein the first gate bias line includes a filter circuit. 2. The microwave amplifier circuit according to claim 1, wherein a filter circuit is formed on the first gate bias line by connecting a capacitor in parallel with a damping resistor.

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