JP2005005723A - Nitride semiconductor epitaxial wafer manufacturing method and nitride semiconductor epitaxial wafer - Google Patents
Nitride semiconductor epitaxial wafer manufacturing method and nitride semiconductor epitaxial wafer Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 88
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 84
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 96
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 60
- 239000010980 sapphire Substances 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims abstract description 45
- 239000013078 crystal Substances 0.000 claims abstract description 33
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 18
- 150000002500 ions Chemical class 0.000 claims abstract description 15
- 239000001257 hydrogen Substances 0.000 claims abstract description 14
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 14
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 10
- 239000001301 oxygen Substances 0.000 claims abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims description 10
- -1 hydrogen ions Chemical class 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 8
- 230000001133 acceleration Effects 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 12
- 230000000694 effects Effects 0.000 abstract description 6
- 238000010521 absorption reaction Methods 0.000 abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 4
- 239000011800 void material Substances 0.000 abstract description 4
- 125000004435 hydrogen atom Chemical class [H]* 0.000 abstract 1
- 229910002601 GaN Inorganic materials 0.000 description 16
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 8
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 7
- 230000003139 buffering effect Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 229910002704 AlGaN Inorganic materials 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 238000003763 carbonization Methods 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- XOYLJNJLGBYDTH-UHFFFAOYSA-M chlorogallium Chemical compound [Ga]Cl XOYLJNJLGBYDTH-UHFFFAOYSA-M 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
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Abstract
【課題】結晶欠陥や反りやクラックが少なく大面積の窒化物半導体エピタキシャルが得られる窒化物半導体エピタキシャルウェハの製造方法及び窒化物半導体エピタキシャルウェハを提供する。
【解決手段】サファイア基板1の表面近傍に水素や窒素、酸素等のイオンを打ち込むことにより得られる中間層2は、アモルファス的な構造となるため、歪みを吸収、緩和し、クラックや反り等が低減する。中間層2は窒化物半導体層3の成長中に加熱されることによりボイドが生じる。ボイドは歪みの吸収、緩和効果が高く、クラックや反り等が低減し、結晶緩和を減少させる。基板表面が異種基板1のため、ボイドを有する中間層2の歪み吸収効果が大きくなり、高品質で大口径の窒化物半導体エピタキシャルウェハが得られる。
【選択図】 図1A method for manufacturing a nitride semiconductor epitaxial wafer and a nitride semiconductor epitaxial wafer with which a large-area nitride semiconductor epitaxial is obtained with few crystal defects, warpage, and cracks are provided.
An intermediate layer 2 obtained by implanting ions of hydrogen, nitrogen, oxygen or the like in the vicinity of the surface of a sapphire substrate 1 has an amorphous structure. To reduce. The intermediate layer 2 is heated during the growth of the nitride semiconductor layer 3 to generate voids. Voids have high strain absorption and relaxation effects, reduce cracks and warpage, and reduce crystal relaxation. Since the substrate surface is the heterogeneous substrate 1, the strain absorption effect of the void-containing intermediate layer 2 is increased, and a high-quality and large-diameter nitride semiconductor epitaxial wafer can be obtained.
[Selection] Figure 1
Description
本発明は、窒化物半導体エピタキシャルウェハの製造方法及び窒化物半導体エピタキシャルウェハに関する。 The present invention relates to a method for manufacturing a nitride semiconductor epitaxial wafer and a nitride semiconductor epitaxial wafer.
近年、発光ダイオード(LED)やレーザダイオード(LD)等の高出力化、高効率化等を図るため、バンドギャップが大きく(3.4eV)、直接遷移型であり、しかもバンドギャップを広範囲で制御できることから窒化物半導体が用いられるようになってきた。 In recent years, the band gap is large (3.4 eV), direct transition type, and the band gap is controlled over a wide range in order to increase the output and efficiency of light emitting diodes (LEDs) and laser diodes (LDs). For this reason, nitride semiconductors have been used.
ところで、GaNあるいはその混晶であるAlGaNやInGaN等は実用的な同種の基板がないため、サファイアやSiC等の異種基板上で結晶成長が行われる。これら異種基板は格子定数が成長層と大きく異なるために成長層の結晶欠陥が多い。また、膨張係数も大きく異なるために厚膜成長時や成長後に反りやクラックが発生する。これらの反りやクラックは特に窒化物半導体厚膜を成長させるときに深刻な問題となる。 By the way, GaN or its mixed crystals such as AlGaN and InGaN do not have practically the same type of substrates, and therefore crystal growth is performed on different types of substrates such as sapphire and SiC. These dissimilar substrates have many crystal defects in the growth layer because the lattice constant is significantly different from that of the growth layer. Further, since the expansion coefficients are greatly different, warping and cracking occur during or after the thick film growth. These warpages and cracks are particularly serious problems when growing a nitride semiconductor thick film.
そこでこのような問題を根本的に解決するためにGaN基板の開発が進められており、高温高圧下でGaN単結晶を合成する高温高圧法(S.Porowski et al,J.Cryst.Growth 178(1997)p174)やサファイア基板上にHVPE法で数百μm程度の厚膜を成長させた後、サファイア基板を取り除くことによってGaNの自立単結晶基板を得る方法(Michael K.Kelly et al,Jpn.J.Appl.Phys.38(1999)Pt.2,No.3A,pp.L217)等の方法が代表的である。 Therefore, development of a GaN substrate has been underway in order to fundamentally solve such problems, and a high-temperature high-pressure method (S. Porowski et al, J. Cryst. Growth 178 ( 1997) p174) and a method of obtaining a GaN free-standing single crystal substrate by growing a thick film of about several hundreds μm on a sapphire substrate by HVPE method and then removing the sapphire substrate (Michael K. Kelly et al, Jpn. J. Appl.Phys.38 (1999) Pt.2, No.3A, pp.L217) and the like are typical.
しかし、高温高圧法は超高圧セル中で結晶成長が行われるため、得られるGaN単結晶のサイズをあまり大きくすることができず、現在のところ直径10mm程度のものしか得られていない。そのうえ製造コストが非常に高く、実用的ではない。HVPE(ハイドライド気相成長法:Hydride Vapor Phase Epitaxy)でサファイア基板上に直接GaN厚膜を成長させる方法はより現実的ではあるが、この場合でも結晶欠陥はかなり多く、サファイア基板の実用的な除去方法が無い。しかも、除去後もGaN厚膜には反りが残る等の問題がある。 However, in the high-temperature and high-pressure method, since crystal growth is performed in an ultra-high pressure cell, the size of the obtained GaN single crystal cannot be increased so much, and currently only a diameter of about 10 mm is obtained. In addition, the manufacturing costs are very high and not practical. Although a method of growing a GaN thick film directly on a sapphire substrate by HVPE (hydride vapor phase epitaxy) is more realistic, there are still many crystal defects in this case, and practical removal of the sapphire substrate is practical. There is no way. Moreover, there is a problem that the GaN thick film remains warped after removal.
窒化物半導体のエピタキシャル成長の時サファイア基板の反りは、窒化物半導体のエピタキシャル成長中に、例えばグラファイトのサセプタ等の加熱物体との接触の不均一を生じ、成長層のキャリア濃度や組成等の特性を不均一にする。特にInGaNではこの濃度不均一は致命的である。また、成長後のサファイア基板の反りは、フォトリソグラフィにおける微細パターンの露光で大きな問題となる。 During epitaxial growth of nitride semiconductors, warpage of the sapphire substrate causes non-uniform contact with a heated object such as a graphite susceptor during the epitaxial growth of nitride semiconductors, and the characteristics such as carrier concentration and composition of the growth layer are not uniform. Make uniform. In particular, this concentration non-uniformity is fatal in InGaN. Further, warping of the sapphire substrate after growth becomes a serious problem in exposure of a fine pattern in photolithography.
また、結晶欠陥は光素子の発光特性や信頼性を悪化させ、電子デバイスのリーク電流や非線形性、信頼性低下等の原因となる。 In addition, the crystal defect deteriorates the light emission characteristics and reliability of the optical element, and causes leakage current, nonlinearity, and deterioration of reliability of the electronic device.
この対策として、選択成長によるラテラル方向成長を利用したELO法(O.H.Nam et al,Appl.phys.Lett.71(1997)2472)やFIELO法(A.Sakai et al,Appl.Phys.Lett.71(1997)2259)等が開発されているが、いまだに結晶欠陥は106 〜107 cm-3ほど存在し、反りの問題はまったく改善されていないという問題があった。 As countermeasures, the ELO method using lateral growth by selective growth (OH Nam et al, Appl. Phys. Lett. 71 (1997) 2472) or the FIELO method (A. Sakai et al, Appl. Phys. Lett. 71 (1997) 2259) and the like have been developed, but there are still crystal defects of about 10 6 to 10 7 cm −3 , and the problem of warping has not been improved at all.
一方、反りを軽減する方法に関しては例えば特開平9−223819号公報に開示されているように、Si基板の表面より下に酸素若しくは窒素のイオン打ち込みによって緩和層兼剥離層を形成し、さらに表面を炭化してSiCとしたSi基板上に窒化物半導体を成長させ、その後のエッチングによってSi基板を除去する方法がある。 On the other hand, with respect to a method for reducing the warpage, for example, as disclosed in JP-A-9-223819, a relaxation layer / peeling layer is formed by ion implantation of oxygen or nitrogen below the surface of the Si substrate. There is a method in which a nitride semiconductor is grown on a Si substrate that is carbonized to form SiC, and the Si substrate is removed by subsequent etching.
しかし、この方法では窒化物半導体への応力を軽減するためにSi基板とそのSi基板上に形成するSiC層、AlGaNバッファ層及び窒化物半導体層構造の厚さのバランスを精密に制御しなければならない。特に窒素打ち込みによって形成した窒化物半導体層を歪み緩和層とした場合、Si基板をエッチングによって除去するためにSiC層と歪み緩和層との間にSiの層を残さなければならないので、表面炭化の条件が厳しく、かつ歪み緩和層が窒化物半導体成長層から遠くなるので、歪み緩和効果が小さくなってしまう。また、基板表面を完全に覆うほどに表面炭化を行うのは量産を考えた場合困難である。 However, in this method, in order to reduce the stress on the nitride semiconductor, the balance of the thickness of the Si substrate and the SiC layer, AlGaN buffer layer, and nitride semiconductor layer structure formed on the Si substrate must be precisely controlled. Don't be. In particular, when a nitride semiconductor layer formed by nitrogen implantation is used as a strain relaxation layer, a Si layer must be left between the SiC layer and the strain relaxation layer in order to remove the Si substrate by etching. Since the conditions are severe and the strain relaxation layer is far from the nitride semiconductor growth layer, the strain relaxation effect is reduced. In addition, it is difficult to carry out surface carbonization so as to completely cover the substrate surface in consideration of mass production.
そこで、本発明の目的は、上記課題を解決し、結晶欠陥が少なく、反りやクラックの少ない窒化物半導体エピタキシャルウェハの製造方法及び窒化物半導体エピタキシャルウェハを提供することにある。 SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-described problems and provide a method for manufacturing a nitride semiconductor epitaxial wafer and a nitride semiconductor epitaxial wafer with less crystal defects and less warpage and cracks.
さらに、本発明の目的は、上記課題を解決し、結晶欠陥や反りやクラックが少なく大面積の窒化物半導体エピタキシャルが得られる窒化物半導体エピタキシャルウェハの製造方法及び窒化物半導体エピタキシャルウェハを提供することにある。 Furthermore, an object of the present invention is to provide a nitride semiconductor epitaxial wafer manufacturing method and a nitride semiconductor epitaxial wafer that solve the above-mentioned problems and that can obtain a nitride semiconductor epitaxial having a large area with few crystal defects, warpage, and cracks. It is in.
上記目的を達成するために本発明の窒化物半導体エピタキシャルウェハの製造方法は、サファイア基板の表面近傍にサファイア基板より機械的強度の弱い中間層を形成し、中間層を形成したサファイア基板の上にデバイス用窒化物半導体層をエピタキシャル成長させるものである。 In order to achieve the above object, the nitride semiconductor epitaxial wafer manufacturing method of the present invention forms an intermediate layer having a lower mechanical strength than the sapphire substrate in the vicinity of the surface of the sapphire substrate, and on the sapphire substrate on which the intermediate layer is formed. A nitride semiconductor layer for devices is epitaxially grown.
上記構成に加え本発明の窒化物半導体エピタキシャルウェハの製造方法は、デバイス用窒化物半導体層の厚さを10μm以下とするのが好ましい。 In the nitride semiconductor epitaxial wafer manufacturing method of the present invention in addition to the above configuration, the thickness of the nitride semiconductor layer for devices is preferably 10 μm or less.
上記構成に加え本発明の窒化物半導体エピタキシャルウェハの製造方法は、サファイア基板の表面から中間層を形成すべき深さにイオンを打ち込むことによって中間層を形成するのが好ましい。 In addition to the above configuration, the method for manufacturing a nitride semiconductor epitaxial wafer of the present invention preferably forms the intermediate layer by implanting ions from the surface of the sapphire substrate to a depth at which the intermediate layer is to be formed.
上記構成に加え本発明の窒化物半導体エピタキシャルウェハの製造方法は、イオンとして水素イオン、窒素イオン及び酸素イオンのうち少なくとも1種類を用いるのが好ましい。 In addition to the above configuration, the method for producing a nitride semiconductor epitaxial wafer of the present invention preferably uses at least one of hydrogen ions, nitrogen ions and oxygen ions as ions.
上記構成に加え本発明の窒化物半導体エピタキシャルウェハの製造方法は、イオンの打ち込みの加速電圧を1keV以上1MeV以下とし、かつ、イオンのドーズ量を1×1015cm-2以上1×1019cm-2以下とするのが好ましい。 In addition to the above-described configuration, the nitride semiconductor epitaxial wafer manufacturing method of the present invention has an ion implantation acceleration voltage of 1 keV to 1 MeV and an ion dose of 1 × 10 15 cm −2 to 1 × 10 19 cm. -2 or less is preferable.
上記構成に加え本発明の窒化物半導体エピタキシャルウェハの製造方法は、イオンを打ち込んだ後、熱処理を行ってサファイア基板の表面結晶層のイオン打ち込みによるダメージを回復させると共に、表面近傍に微細なボイド及びボイドの集合体を生じさせることにより中間層を形成してもよい。 In addition to the above-described structure, the nitride semiconductor epitaxial wafer manufacturing method of the present invention performs ion treatment and then heat treatment to recover the damage caused by ion implantation of the surface crystal layer of the sapphire substrate, and also provides fine voids and The intermediate layer may be formed by generating an aggregate of voids.
上記構成に加え本発明の窒化物半導体エピタキシャルウェハの製造方法は、熱処理をH2 若しくはNH3 あるいは両者の混合雰囲気下で行うのが好ましい。 In addition to the above-described configuration, the nitride semiconductor epitaxial wafer manufacturing method of the present invention preferably performs the heat treatment in H 2 or NH 3 or a mixed atmosphere of both.
上記構成に加え本発明の窒化物半導体エピタキシャルウェハの製造方法は、中間層からサファイア基板までの部分を中間層を境に剥離させて除去するのが好ましい。 In addition to the above configuration, the method for producing a nitride semiconductor epitaxial wafer of the present invention preferably removes the portion from the intermediate layer to the sapphire substrate by peeling off the intermediate layer as a boundary.
上記構成に加え本発明の窒化物半導体エピタキシャルウェハの製造方法は、デバイス用窒化物半導体層の表面に他の基板を貼り付けた後中間層からサファイア基板までの部分を、中間層を境に剥離、除去してもよい。 In addition to the above-described structure, the method for manufacturing a nitride semiconductor epitaxial wafer of the present invention peels off the portion from the intermediate layer to the sapphire substrate after attaching another substrate to the surface of the nitride semiconductor layer for devices. , May be removed.
上記構成に加え本発明の窒化物半導体エピタキシャルウェハの製造方法は、他の基板としてSi等の半導体若しくはAlN等の高熱伝導性基板あるいはCu、Al等の金属を用いてもよい。 In addition to the above configuration, the nitride semiconductor epitaxial wafer manufacturing method of the present invention may use a semiconductor such as Si, a highly thermally conductive substrate such as AlN, or a metal such as Cu or Al as another substrate.
上記構成に加え本発明の窒化物半導体エピタキシャルウェハの製造方法は、サファイア基板を除去したデバイス用窒化物半導体層に残ったサファイア基板の一部を研磨等の方法によって除去してもよい。 In addition to the above configuration, in the method for manufacturing a nitride semiconductor epitaxial wafer of the present invention, a part of the sapphire substrate remaining on the device nitride semiconductor layer from which the sapphire substrate is removed may be removed by a method such as polishing.
本発明の窒化物半導体エピタキシャルウェハは上記いずれかに記載の方法で製造された、Inx Aly Ga1-x-y N(x,y≧1、x+y≦1)の組成を有するものである。 Nitride semiconductor epitaxial wafer of the present invention has a composition of the produced by the method according to any one, In x Al y Ga 1- xy N (x, y ≧ 1, x + y ≦ 1).
本発明によれば、窒化物半導体と異なるサファイア基板の表面近傍に水素や窒素、酸素等のイオンを打ち込むことにより得られる中間層は、アモルファス的な構造となるため、歪みを吸収、緩和し、クラックや反り等が低減する。水素が打ち込まれた中間層は窒化物半導体層の成長中に加熱されることによりボイドが生じる。ボイドは歪みの吸収、緩和効果が高く、クラックや反り等が低減し、結晶欠陥を減少させる。基板表面がサファイア基板であり、ボイドを有する中間層の歪み吸収効果、歪み緩和効果が大きいので、面倒な表面炭化処理や複数の層の膜厚バランスを精密に制御する必要もなく、高品質で大口径の窒化物半導体エピタキシャルウェハが得られる。 According to the present invention, the intermediate layer obtained by implanting ions of hydrogen, nitrogen, oxygen, or the like in the vicinity of the surface of the sapphire substrate different from the nitride semiconductor has an amorphous structure, so it absorbs and relaxes strain, Cracks and warpage are reduced. The intermediate layer into which hydrogen is implanted is heated during the growth of the nitride semiconductor layer, thereby generating voids. Voids have a high strain absorption and relaxation effect, reduce cracks and warpage, and reduce crystal defects. The substrate surface is a sapphire substrate, and the effect of strain absorption and strain relaxation of the intermediate layer with voids is large, so there is no need for cumbersome surface carbonization treatment and precise control of the film thickness balance of multiple layers, and high quality A large-diameter nitride semiconductor epitaxial wafer is obtained.
以上、要するに本発明によれば、次のような優れた効果を発揮する。 As described above, according to the present invention, the following excellent effects are exhibited.
結晶欠陥が少なく、反りやクラックのない窒化物半導体エピタキシャルウェハの製造方法及び窒化物半導体エピタキシャルウェハの提供を実現することができる。 It is possible to realize a nitride semiconductor epitaxial wafer manufacturing method and a nitride semiconductor epitaxial wafer with few crystal defects and no warpage or cracks.
以下、本発明の実施の形態について説明する。 Embodiments of the present invention will be described below.
本発明の窒化物半導体エピタキシャルウェハの製造方法は、サファイア基板の表面近傍にサファイア基板より機械的強度の弱い中間層を形成し、この中間層を形成したサファイア基板の上にデバイス用窒化物半導体層をエピタキシャル成長させるものである。成長する層構造は1層以上のエピタキシャル構造であり、P/N接合、ヘテロ接合等の半導体構造を有してもよい。発光ダイオード、レーザ、受光素子、電界効果トランジスタ、HEMT、HBT等種々の半導体素子に適した層構造、あるいはその一部を構成するエピタキシャル層構造となる。 In the method for producing a nitride semiconductor epitaxial wafer of the present invention, an intermediate layer having a mechanical strength lower than that of the sapphire substrate is formed near the surface of the sapphire substrate, and the nitride semiconductor layer for devices is formed on the sapphire substrate on which the intermediate layer is formed. Is epitaxially grown. The growing layer structure is an epitaxial structure of one or more layers, and may have a semiconductor structure such as a P / N junction or a heterojunction. A layer structure suitable for various semiconductor elements such as a light emitting diode, a laser, a light receiving element, a field effect transistor, HEMT, and HBT, or an epitaxial layer structure constituting a part thereof.
中間層は、サファイア基板の表面近傍に水素や窒素、酸素等のイオンを打ち込むことにより機械的強度をサファイア基板よりも小さくした層である。イオン打ち込み後のサファイア基板に熱処理を加えることにより中間層に多数の微細なボイドを生じさせることができ、中間層の機械的強度をさらに小さくすることができる。 The intermediate layer is a layer whose mechanical strength is made smaller than that of the sapphire substrate by implanting ions of hydrogen, nitrogen, oxygen, or the like near the surface of the sapphire substrate. By applying heat treatment to the sapphire substrate after ion implantation, a large number of fine voids can be generated in the intermediate layer, and the mechanical strength of the intermediate layer can be further reduced.
この中間層がデバイス用窒化物半導体結晶とサファイア基板との熱膨張差を緩和するバッファ層として機能するため、従来問題となっていたクラックや反りが解消し、高品質な窒化物半導体エピタキシャルウェハが得られる。さらにこの中間層を境にしてサファイア基板までの部分は容易に剥離、除去することができる。 Since this intermediate layer functions as a buffer layer that relieves the difference in thermal expansion between the nitride semiconductor crystal for devices and the sapphire substrate, the cracks and warpage that have been problems in the past are eliminated, and a high-quality nitride semiconductor epitaxial wafer is obtained. can get. Further, the portion up to the sapphire substrate with this intermediate layer as a boundary can be easily peeled off and removed.
剥離の方法は、デバイス用窒化物半導体層の結晶膜成長過程での加熱による自然剥離、あるいはその後の熱処理による剥離、側面からの窒素ジェットによる剥離、ウォータジェットによる剥離、レーザ照射による剥離等種々の方法が使用できる。 There are various peeling methods such as natural peeling by heating in the crystal film growth process of nitride semiconductor layer for devices, or peeling by subsequent heat treatment, peeling by nitrogen jet from the side, peeling by water jet, peeling by laser irradiation, etc. The method can be used.
剥離後にデバイス用窒化物半導体層の裏面にわずかに残ったサファイア基板の一部を研磨等によって除去することにより、大口径でフラットな自立窒化物半導体エピタキシャルウェハを容易に得ることができる。 By removing a part of the sapphire substrate slightly remaining on the back surface of the device nitride semiconductor layer after peeling by polishing or the like, a large-diameter flat self-supporting nitride semiconductor epitaxial wafer can be easily obtained.
デバイス用窒化物半導体層の膜厚は10μm以下が好ましい。これはサファイア基板の反りを防ぐためであり、これ以上の厚さになると、窒化物半導体とサファイアとの熱膨張差によって基板が反ってしまうためである。 The film thickness of the nitride semiconductor layer for devices is preferably 10 μm or less. This is to prevent warping of the sapphire substrate, and when the thickness exceeds this, the substrate warps due to a difference in thermal expansion between the nitride semiconductor and sapphire.
イオン打ち込みの加速電圧は1keV以上1MeV以下が好ましい。これは、中間層の形成深さを適切にし、サファイア基板表面の結晶状態を良好に保つためである。1keV以下では中間層の形成される位置が浅すぎて、サファイア基板表面の結晶性に悪影響を与える。これとは逆に1MeV以上では打ち込んだイオンが基板表面の結晶に与えるダメージが無視できなくなる。また、中間層の形成される位置が深くなりすぎて中間層による歪み緩衝効果が小さくなったり、サファイア基板剥離後にデバイス用窒化物半導体結晶の裏面に残るサファイア等が厚くなり、除去するための研磨に時間がかかってしまうためである。 The acceleration voltage for ion implantation is preferably 1 keV or more and 1 MeV or less. This is because the formation depth of the intermediate layer is made appropriate and the crystal state of the sapphire substrate surface is kept good. Below 1 keV, the position where the intermediate layer is formed is too shallow, which adversely affects the crystallinity of the sapphire substrate surface. On the other hand, at 1 MeV or higher, the damage given to the crystals on the substrate surface by the implanted ions cannot be ignored. In addition, the position where the intermediate layer is formed becomes too deep and the strain buffering effect by the intermediate layer becomes small, or the sapphire remaining on the back surface of the nitride semiconductor crystal for devices after the sapphire substrate peeling becomes thick and polished for removal This is because it takes time.
ドーズ量は1×1015cm-2以上1×1019cm-2以下とするのが好ましい。これは、サファイア基板表面の結晶のダメージを無視できる範囲に抑えつつ反りを緩和し、歪み緩衝と基板の剥離に十分なほどのボイドを発生させるためである。ドーズ量が1×1015cm-2以下の場合にはボイドの発生密度が小さいため歪み緩衝効果が小さくなり、基板を剥離するのに不十分である。これとは逆にドーズ量が1×1019cm-2以上になると打ち込んだイオンがサファイア基板の表面の結晶に与えるダメージが無視できなくなってしまうためである。 The dose is preferably 1 × 10 15 cm −2 or more and 1 × 10 19 cm −2 or less. This is because warping is relaxed while suppressing damage to crystals on the surface of the sapphire substrate to a negligible range, and voids sufficient for strain buffering and substrate peeling are generated. When the dose amount is 1 × 10 15 cm −2 or less, the generation density of voids is small, so that the strain buffering effect is small, which is insufficient for peeling off the substrate. On the contrary, if the dose amount is 1 × 10 19 cm −2 or more, the damage caused by the implanted ions to the crystal on the surface of the sapphire substrate cannot be ignored.
(実施例1)
図1(a)〜(e)は本発明の窒化物半導体基板の製造方法の一実例を示す工程図である。
(Example 1)
1A to 1E are process diagrams showing an example of the method for manufacturing a nitride semiconductor substrate of the present invention.
基板として、サファイア基板(直径約50mm、厚さ約0.33mm)を準備する(図1(a))。 As a substrate, a sapphire substrate (diameter: about 50 mm, thickness: about 0.33 mm) is prepared (FIG. 1 (a)).
サファイア基板1に水素のイオン打ち込みを行う。その条件はドーズ量を1×1017cm-2とし、加速電圧を100keVとして、サファイア基板1の表面から0.5μmの深さに厚さ0.1μmの中間層2を形成する。水素を打ち込んだサファイア基板1の表面近傍1aには単結晶層が維持されており、その単結晶層1aの下に水素の打ち込み層、すなわち中間層2が存在する(図1(b))。
Hydrogen ions are implanted into the sapphire substrate 1. The condition is that the dose is 1 × 10 17 cm −2 , the acceleration voltage is 100 keV, and the
サファイア基板1aの表面に有機金属気相成長法(MOVPE法)を用いてデバイス用窒化物半導体層3となるGaN単結晶を2μmエピタキシャル成長させた。成長炉は、横型常圧MOVPE炉を用い、原料としてアンモニアガスとトリメチルガリウムを用い、キャリアガスとして水素と窒素との混合ガスを用いた。
A GaN single crystal serving as the device
まず、基板を水素雰囲気で1100℃に加熱し、表面の酸化物等をクリーニングする。続いて基板温度を550℃に下げてGaNを20nm成長させ、さらに基板温度を1050℃に上げて、GaNを2μm成長させる。 First, the substrate is heated to 1100 ° C. in a hydrogen atmosphere to clean the surface oxide and the like. Subsequently, the substrate temperature is lowered to 550 ° C. to grow GaN by 20 nm, and the substrate temperature is further raised to 1050 ° C. to grow GaN by 2 μm.
MOVPE炉から取り出したGaNエピタキシャル成長基板のうちの1枚を割ってその断面を走査型電子顕微鏡で観察したところ、中間層に微細なボイドが多数発生している様子が観測された。 When one of the GaN epitaxial growth substrates taken out from the MOVPE furnace was divided and the cross section was observed with a scanning electron microscope, it was observed that many fine voids were generated in the intermediate layer.
作製したGaNエピタキシャル成長基板4上に、HVPE法を用いてGaN単結晶を300μmエピタキシャル成長させる。装置は横型常圧HVPE炉を用いる。原料としてアンモニアガス及び金属Gaと、HClガスとを850℃で反応させたGaClを用い、キャリアガスとして水素ガスを用いる。成長温度を1050℃とし、成長速度を80μm/hとする(図1(c))。
A GaN single crystal is epitaxially grown 300 μm on the produced GaN
エピタキシャル成長終了後、成長温度から室温までの冷却過程において中間層(ボイド層)2を境に中間層2からサファイア基板1bまでの部分が自然に剥離する(図1(d))。
After the epitaxial growth is completed, a portion from the
得られたGaN単結晶からなるデバイス用窒化物半導体層3の裏面に残った薄いサファイア層1aを研磨して除去することにより、直径約50mm、厚さ約300μmのGaN自立単結晶基板が得られた。この基板は無色透明であり、クラックや反りが全くなかった(図1(e))。
By polishing and removing the thin sapphire layer 1a remaining on the back surface of the device
上述した実施例では、基板としてサファイア基板を用い、打ち込むイオンとして水素を用いた場合について説明したが、サファイア基板以外の基板や水素イオン以外のイオンを用いてもよい。 In the above-described embodiments, the case where a sapphire substrate is used as a substrate and hydrogen is used as ions to be implanted has been described. However, a substrate other than a sapphire substrate or ions other than hydrogen ions may be used.
窒化物半導体のエピタキシャル成長法としては、MOVPE法、HVPE法、MBE法等とすでに公知の様々な方法があり、利用することができる。また、窒化ガリウムや窒化アルミニウム等の低温バッファ層を用いる2段階成長方法、直接高温で成長する方法、成長の途中で微細加工と再成長を用いてラテラル成長による転位低減を図るELO法、FIELO法等公知の種々の方法を用いることができる。 As a method for epitaxial growth of nitride semiconductor, there are various known methods such as MOVPE method, HVPE method, MBE method and the like, which can be used. In addition, a two-stage growth method using a low-temperature buffer layer such as gallium nitride or aluminum nitride, a method of growing directly at a high temperature, an ELO method or a FIELO method for reducing dislocation by lateral growth using microfabrication and regrowth during the growth Various known methods such as these can be used.
中間層をボイド層とするのは他の窒化物半導体層の成長前の昇温中、冷却中、成長後のいずれか、あるいは全ての過程あるいは幾つかの複数の過程で行うことができる。またはイオン打ち込み後、他の窒化物半導体層の成長開始前に熱処理を行ってもよい。 The void layer can be used as the void layer during the temperature rise before the growth of the other nitride semiconductor layers, during the cooling, after the growth, in the whole process, or in several processes. Alternatively, heat treatment may be performed after ion implantation and before the start of growth of another nitride semiconductor layer.
中間層を境にサファイア基板を剥離する方法は、成長後の熱処理による剥離、側面からの窒素ジェットによる剥離、ウォータジェットによる剥離、レーザ照射による剥離等の種々の方法でも実施できる。 The method of peeling the sapphire substrate with the intermediate layer as a boundary can be implemented by various methods such as peeling by heat treatment after growth, peeling by nitrogen jet from the side, peeling by water jet, peeling by laser irradiation, and the like.
ここで、従来、窒化物半導体のエピタキシャル成長は、熱膨張係数が大きく異なるサファイア等の基板上で行われていたので、結晶欠陥が多かったり、厚膜を成長すると反りやクラックが発生するという問題があった。この問題を根本的に解決するために窒化物半導体基板の開発も行われてきたが、窒化物半導体基板の作製は超高圧下で行われていたのでコストが非常に高く、10mm程度のものしか得られなかった。また、HVPE法で数百μm程度のGaN厚膜をサファイア基板上に成長させた後でサファイア基板を取り除くことによってGaNの自立基板を得る方法より現実的であるが、サファイア基板と窒化物半導体との熱膨張率の差に起因する反りやクラックが発生するうえ結晶欠陥がかなり多い、サファイア基板の実用的な除去方法が無い、除去後も反りが残る等の問題があった。 Here, conventionally, epitaxial growth of nitride semiconductors has been performed on a substrate such as sapphire having a significantly different thermal expansion coefficient, so that there are many crystal defects, and warping and cracking occur when a thick film is grown. there were. In order to fundamentally solve this problem, a nitride semiconductor substrate has been developed. However, since the production of the nitride semiconductor substrate was performed under an ultra-high pressure, the cost is very high, and only about 10 mm is required. It was not obtained. Further, it is more realistic than a method of obtaining a GaN free-standing substrate by removing a sapphire substrate after a GaN thick film of about several hundred μm is grown on a sapphire substrate by the HVPE method. There have been problems such as warpage and cracks due to the difference in thermal expansion coefficient between the two, and a large number of crystal defects, no practical method for removing the sapphire substrate, and warping remaining after removal.
しかしながら、本発明によれば、水素打ち込み及び熱処理によって基板中に形成された中間層が熱膨張率の差を緩和するバッファ層として機能するので、従来問題となっていた結晶欠陥が著しく減少し、反りやクラックが解消された高品質な窒化物半導体エピタキシャルウェハを容易に得ることができる。また、窒化物半導体層を、この中間層を境にして基板から剥離して窒化物半導体の大面積でフラットな自立エピタキシャルウェハを容易に得ることができる。 However, according to the present invention, since the intermediate layer formed in the substrate by hydrogen implantation and heat treatment functions as a buffer layer that alleviates the difference in thermal expansion coefficient, crystal defects that have been a problem in the past are significantly reduced, A high-quality nitride semiconductor epitaxial wafer in which warpage and cracks are eliminated can be easily obtained. In addition, the nitride semiconductor layer is peeled off from the substrate with the intermediate layer as a boundary, and a large-area and flat self-supporting epitaxial wafer of the nitride semiconductor can be easily obtained.
1、1a、1b サファイア基板
2 中間層
3 デバイス用窒化物半導体層
1, 1a,
Claims (12)
Inx Aly Ga1-x-y N(x,y≧1、x+y≦1)の組成を有することを特
徴とする窒化物半導体エピタキシャルウェハ。 Manufactured by the method according to any one of claims 1 to 11,
In x Al y Ga 1-xy N (x, y ≧ 1, x + y ≦ 1) nitride semiconductor epitaxial wafer characterized by having a composition.
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