JP2004363498A - Power semiconductor device and method of manufacturing the same - Google Patents

Abstract

An element structure for realizing a MOS FET having a low on-resistance and a high withstand voltage is provided.
In a power semiconductor device having a gate electrode embedded in a groove via a gate insulating film, a p-type depletion region enlarging layer is sandwiched between two n-type drift layers. The groove is formed so as to reach the n-type drift layer 3. In the region near the groove of the p-type depletion region expansion layer, an n-type conversion region in which the conductivity type is converted to n-type is formed, and forms a path for carriers.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a power semiconductor device and a method of manufacturing the same, and more particularly, to a trench gate type MOS gate device.
[0002]
[Prior art]
2. Description of the Related Art Power semiconductor devices for controlling large currents have been widely used from household appliances to industrial devices. In particular, as a semiconductor device supporting automotive electronics, it is used in many parts such as hydraulic valve control such as ABS, motor control such as a power window, and an inverter system for converting a battery DC voltage of an electric vehicle into an AC.
[0003]
MOS (Metal Oxide Semiconductor) gate devices, which are capable of high-speed switching and have low drive loss due to voltage drive among power semiconductor devices due to demands for higher frequency and smaller size of inverters. Is attracting attention. A MOS gate device is a MOSFET (Field Effect Transistor) which is a unipolar device in which one of electrons or holes operates as a carrier, and an IGBT (Insulated Gate Bipolar Transistor) which is a bipolar device in which both electrons and holes operate as carriers. Can be roughly divided into The MOS FET is particularly excellent in high-speed operation because there is no accumulation of minority carriers.
[0004]
Problems required for power semiconductor devices include a reduction in on-resistance for reducing reactive power and an improvement in withstand voltage for improving reliability. The on-resistance is one of the most important characteristics of a MOS FET. It refers to the resistance through all the paths in the element where the drain current flows from the drain to the source, and is mainly controlled by the resistance (channel resistance) of the channel region. Have been. On the other hand, the withstand voltage refers to the withstand voltage between the drain and the source, and it is known that there is a trade-off relationship with the on-resistance.
[0005]
To reduce the channel resistance, a trench gate structure has been developed in which a narrow and deep groove (trench) is dug in a semiconductor surface and a gate is formed on the side surface thereof. As a result, the current path was three-dimensionally expanded to the side wall of the trench, so that a remarkably low on-resistance was realized.
[0006]
On the other hand, in order to improve the withstand voltage, a structure has been proposed in which a stacked p-floating layer is buried in an n-drift region below a body-p region to reduce electric field concentration (for example, see Non-Patent Document 1).
[0007]
Further, a structure has been proposed in which a trench gate is formed to a depth of a drift region and a gate oxide film at the bottom of the trench is thickened to improve a breakdown voltage (for example, see Non-Patent Document 2). The on-resistance can be reduced and the trade-off relationship with the withstand voltage can be improved as the gate insulating film becomes thinner.
[0008]
[Non-patent document 1]
N. N. Cezac, et al., "A New Generation of Power Unipolar Devices: the Concept of the Floating Islands MOS Transistor", ISPSD'2000, IEEE, 2000, IEEE. 69-72
[Non-patent document 2]
Wye. Baba et al., "A STUDY ON A HIGH BLOCKING VOLTAGE UMOS-FET WITH A DOUBLE GATE Structure", ISPSD '1992, Japan, IEEE, 1992, p. 300-302
[0009]
[Problems to be solved by the invention]
The reduction of the on-resistance by embedding the stacked p-floating layer described above mainly involves the reduction of the drift resistance. Therefore, a low-breakdown-voltage MOS FET in which the ratio of the drift resistance to the on-resistance is small is not an effective structure in consideration of a small reduction effect and an increase in manufacturing cost for realizing a complicated laminated structure.
[0010]
Further, there is a limit to the improvement of the trade-off between the on-resistance and the withstand voltage due to the miniaturization of the trench gate due to process restrictions.
[0011]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a structure in which a reduction in ON resistance and an improvement in breakdown voltage can be realized by a simple process in a MOS FET.
[0012]
[Means for Solving the Problems]
The features of the power trench gate type semiconductor device of the present invention include a first n (p) type drift layer formed on an n (p) type semiconductor substrate and a surface of the first n (p) type drift layer. , A second n (p) drift layer formed on the surface of the p (n) type depletion region extension layer, and a second n (p) ) Type p-type body layer formed on the surface of the drift layer, and an n (p) -type source region formed on the surface of the p (n) -type body layer. The first n (p) type drift layer penetrating through the (p) type source region, the p (n) type body layer, the second n (p) drift layer, and the p (n) type depletion region extension layer The n (p) -type conversion converted to n (p) -type is formed near the side wall of the groove of the p (n) -type depletion region extension layer. It is to comprise a region.
[0013]
According to this structure, carriers can flow through the n (p) -type conversion region, and the depletion layer spreads at the p / n interface during the off operation, so that the withstand voltage increases. Can be improved.
[0014]
Another feature of the power trench gate type semiconductor device of the present invention is that the thickness of the gate insulating film in contact with the p (n) type body layer is the p (n) type depletion region extension layer and the first That is, the thickness is smaller than the thickness of the gate insulating film in contact with the n (p) type drift layer.
[0015]
According to this configuration, without increasing the gate threshold voltage, the electric field concentration near the change point of the thickness of the gate insulating film can be reduced, and the withstand voltage can be improved.
[0016]
Another feature of the power trench gate type semiconductor device of the present invention is that the impurity concentration of the first n (p) type drift layer is lower than that of the second n (p) type drift layer.
[0017]
According to this configuration, the electric field concentration near the bottom of the trench can be alleviated, and the depletion layer from the p-type depletion region extension layer is further expanded, so that the withstand voltage can be further improved.
[0018]
Another feature of the power trench gate type semiconductor device of the present invention is that the substrate is a semiconductor substrate having a polarity opposite to that of the first n (p) type drift layer.
[0019]
According to this structure, even if the polarity of the substrate is opposite to that of the first n (p) type drift layer, a structure can be realized in which the trade-off relationship between the on-resistance and the withstand voltage can be improved.
[0020]
Another feature of the power trench gate type semiconductor device of the present invention is that the thickness of the gate insulating film in contact with the upper part of the p (n) type body layer is the lower part of the p (n) type body layer and the second n ( The thickness is smaller than the thickness of the gate insulating film in contact with the p) type drift layer, the p (n) type depletion region extension layer, and the first n (p) type drift layer.
[0021]
According to this structure, the thickness of the gate insulating film above the trench changes in a region in contact with the p-type body layer, so that the electric field concentration generated in the vicinity thereof can be further reduced.
[0022]
The feature of the manufacturing method of the power trench gate type semiconductor device of the present invention is that a first n (p) type drift layer, a p (n) type depletion region extension layer, and a second E) sequentially growing the n (p) type drift layer, and the first through the n (p) type source region, the p (n) type body layer, and the p (n) type depletion region extension layer. Forming a groove reaching the n (p) type drift layer, and converting the n (p) type into an n (p) type near the side wall of the groove in the p (n) type depletion region extension layer. Forming a region.
[0023]
According to this method, it is possible to form a depletion region extension layer in which a path for carriers is secured.
[0024]
Another feature of the method for manufacturing the power trench gate type semiconductor device of the present invention is that a first silicon oxide film is deposited so as to fill the trench, and the first silicon oxide film is anisotropically dried. A step of etching to a predetermined depth by an etching method, and a step of forming a second silicon oxide film thinner than the thickness of the first silicon oxide film on an inner wall of the groove where the first silicon oxide film is etched. And
[0025]
According to this method, gate insulating films having different thicknesses can be formed in the trench.
[0026]
Another feature of the manufacturing method of the power trench gate type semiconductor device of the present invention is that a step of forming a first silicon oxide film on an inner wall of the groove and a step of forming the first silicon oxide film on the groove are performed. A step of filling the resist, a step of etching back the resist to a predetermined depth, a step of etching the first silicon oxide film using the etched back resist as an etching mask, and a step of etching the first silicon oxide film. Forming a second silicon oxide film thinner than the thickness of the first silicon oxide film on the inner wall where the silicon oxide film is etched.
[0027]
According to this method, gate insulating films having different thicknesses can be formed in the trenches.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
[Device structure]
FIG. 1 is a sectional view of the MOS FET 1 according to the first embodiment. A first n-type drift layer 3, a p-type depletion region extension layer 4, a second n-type drift layer 5, and a p-type body layer 8 are sequentially stacked on an n ⁺ -type substrate 2 made of silicon. Is formed with an n ⁺ type source region 9. A trench 6 penetrating from the surface of the n ⁺ type source region 9 to the p-type body layer 8, the second n-type layer drift layer 5 and the depletion region extension layer 4 to reach the first n-type drift layer 3 is formed. Is provided with a buried electrode (gate electrode) 11 via a gate insulating film 10. A drain electrode 14 is formed on the back surface of the n ⁺ semiconductor substrate 2, and is insulated from a buried electrode (gate electrode) 11 by an interlayer insulating film 12 on the surface of the p-type body layer 8, and is electrically connected to the source region 9. And a source electrode 13 is formed. The characteristic structure of the present invention is that the p-type depletion region extension layer 4 is sandwiched between the first n-type drift layer 3 and the second n-type drift layer 5, and the trench 6 of the p-type depletion region extension layer 4 is formed. In the region near the side wall, a conversion region 7 converted from p-type to n-type is formed.
[0029]
The MOS FET 1 according to the first embodiment is an n-type substrate and an n-channel type in which carriers are electrons. However, the conductivity type of each semiconductor layer and region is the opposite conductivity type, and a p-channel type in which holes are carriers is also used. good. For example, the substrate and the source region may be p-type, and the body region may be n-type. Further, the substrate may be a semiconductor substrate having a polarity opposite to that of the first n (p) type drift layer. Further, in this embodiment, silicon is used as the semiconductor, but a compound semiconductor can also be used.
[0030]
[Device operation]
The ON operation of the MOSFET 1 will be described with reference to FIG. First, a positive voltage, for example, 2 V, is applied to the drain electrode 14, and the source electrode 13 is grounded. In this state, when a positive voltage, for example, 5 V, is applied to the gate electrode 11, electrons in the p-type body layer 8 are attracted to the buried electrode 11, and an n-type channel is formed in a region near the groove 6. Thereby, the electrons supplied from the source electrode 13 pass from the n ⁺ -type source region 9 to the second n-type drift layer 5, the n-type conversion region 7, the first n-type drift layer 3, and the n ⁺ -type substrate 2, It reaches the drain electrode 14. This flow of electrons is indicated by arrows.
[0031]
Next, an off operation of the MOS FET 1 will be described with reference to FIG. When the gate electrode 11 is changed from a positive voltage to a negative voltage or ground, the n-type channel in the p-type body layer 7 disappears, and no current can flow. When the MOS FET 1 is off, the interface between the second n-type drift layer 5 and the p-type body layer 8, the p-type depletion region extension layer 4 and the second n-type layer drift 5, and the first n-type drift layer 3 and the p-type The depletion layer spreads from the p / n junction at the interface of the depletion region extension layer 4 and prevents electrons from flowing from the source electrode 13 to the drain electrode 14.
[0032]
According to the MOS FET 1 of the first embodiment, the on-resistance can be reduced and the withstand voltage can be improved. The channel resistance and the drift resistance decrease as the impurity concentration of the p-type body layer 8 and the first n-type drift layer 3 increases, but the depletion layer becomes narrower, so that the breakdown voltage decreases and the resistance decreases as the impurity concentration decreases. However, since the depletion layer expands, the breakdown voltage increases. In the MOS FET 1 of the first embodiment, the p-type depletion region extension layer 4 expands the depletion region as compared with the conventional structure, so that the breakdown voltage is increased. Therefore, even if the impurity concentration of the second n-type drift layer 5 and the first n-type drift layer 3 is increased in order to lower the on-resistance, a higher breakdown voltage can be provided as compared with the conventional structure.
[0033]
Further, it is preferable that the impurity concentration of the first n-type drift layer is lower than that of the second n-type drift layer. According to this configuration, the electric field concentration near the bottom of the trench can be alleviated, and the depletion layer from the p-type depletion region extension layer is further expanded, so that the withstand voltage can be further improved.
[0034]
The thickness of the gate insulating film in contact with the upper part of the p-type body layer is the same as that of the gate insulating film in contact with the lower part of the p-type body layer, the second n-type drift layer, the p-type depletion region extension layer, and the first n-type drift layer. It is also preferable that the thickness is thinner than the thickness. According to this structure, the thickness of the gate insulating film above the trench changes in a region in contact with the p-type body layer, so that the electric field concentration generated in the vicinity thereof can be further reduced. In the case of this structure, it is important to optimize the structure according to the required characteristics of the device in consideration of the influence on the gate threshold voltage.
[0035]
Embodiment 2. FIG.
[Device structure]
FIG. 4 is a cross-sectional view of the MOS FET 100 according to the second embodiment. In the MOS FET 100 of the second embodiment, in addition to the structure of the MOS FET 1 of the first embodiment, the thickness of the gate insulating film in the p-type body layer region is the same as that of the p-type depletion region extension layer and the first n-type drift layer region. Characterized in that it is thinner than the thickness in the above.
[0036]
By increasing the thickness of the gate insulating film 10 at the bottom of the groove 6, the concentration of the electric field at the tip of the buried electrode 11 is reduced, and the withstand voltage between the drain and the source can be improved. In the body layer 8 region, the gate insulating film 10 is desirably thin so as not to increase the gate threshold voltage. There is a thickness boundary 10a where the thickness of the gate insulating film changes in order to optimize the thickness of the gate insulating film 10 for each of the above regions.
[0037]
According to the structure of the second embodiment, it is possible to reduce the electric field concentration that occurs in the drift layer region near the thickness boundary 10a of the gate insulating film, and to improve the breakdown voltage.
[0038]
[Simulation of electric field distribution]
The electric field distribution in the structure of the MOS FET 100 of the second embodiment was simulated, and the breakdown voltage and the on-resistance were obtained. FIG. 5A shows a cross-sectional structure near the trench 6 of the MOS FET 100 of the second embodiment and an electric field distribution at the time of breakdown. FIG. 5B shows a p-type as a comparative example based on the structure of the MOS FET 100 of the second embodiment. The cross-sectional structure near the trench 6 and the electric field distribution at the time of breakdown of the structure without the depletion region extension layer 4 are shown.
[0039]
In the structure without the p-type depletion region extension layer 4, it can be seen that the electric field is concentrated near the trench bottom 6a and near the thickness boundary 10a of the gate insulating film. In order to study this electric field concentration in detail, FIG. 6B shows an electric field intensity distribution in the AA section of FIG. From this distribution, it can be seen that the electric field intensity near the thickness boundary 10a is the highest, and the withstand voltage of this MOS FET is determined in this region.
[0040]
On the other hand, in the structure of the MOS FET 100 according to the second embodiment, the electric field is concentrated near the bottom 6a of the groove and near the thickness boundary 10a of the gate insulating film, as in the comparative example, but the distribution spreads further downward. You can see that there is. Further, as shown in FIG. 6A, the electric field intensity distribution in the AA cross section of FIG. 5A indicates that the electric field intensity near the groove bottom 6a is relatively increased and the electric field is dispersed. Understand.
[0041]
As a result of this electric field intensity distribution, the breakdown voltage was about 46 V in the comparative example, but was improved to about 65 V in the structure of the MOS FET 100 of the second embodiment.
[0042]
FIG. 7 shows the result of plotting the normalized on-resistance (Ω · mm ² ) against the withstand voltage in order to see the effect of improving the trade-off relationship between the withstand voltage and the on-resistance. The characteristics of the structure without the p-type depletion region extension layer 4 are plotted with black circles, and the characteristics of the structure of the MOSFET 100 of the second embodiment are plotted with black triangles. According to the MOS FET 100 of the second embodiment, the normalized on-resistance (Ω · mm ² ) can be reduced by 10%, and the trade-off relationship between the withstand voltage and the on-resistance is improved.
[0043]
Embodiment 3 FIG.
[Device structure]
FIG. 21 is a sectional view of the IGBT 200 according to the third embodiment. This IGBT 200 is obtained by applying ap ⁺ type substrate 33 instead of the n ⁺ type substrate 2 in the structure of the first or second embodiment.
[0044]
According to the structure of the third embodiment, holes injected from the collector accumulate in the p-type depletion region extension layer 4 and the carrier concentration near the surface increases, so that the resistance can be made lower than that of the conventional IGBT. .
[0045]
Further, according to the structure of the third embodiment, the electric power modulation effect of the conventional IGBT is not easily impaired. Further, the presence of the p-type depletion layer diffusion layer 4 reduces the short-circuit current due to the JFET effect at the time of load short-circuit, and improves the load short-circuit withstand capability.
[0046]
[Device Manufacturing Method]
The manufacturing process of the MOS FET 100 will be described with reference to the drawings. 8 to 10 are process diagrams for explaining this.
[0047]
As shown in FIG. 8, a first n-type drift layer 3, a p-type layer (depletion region extension layer) 4, and a second n-type drift layer 5 are sequentially stacked on an n ⁺ type silicon substrate 2 by epitaxial growth.
[0048]
Next, as shown in FIG. 9, a groove (trench) 6 penetrating through the second n-type drift layer 5 and the depletion region extension layer 4 and reaching the first n-type drift layer 3 is formed. First, after an HTO (high temperature oxide chemical vapor deposition) method is formed on the entire surface of the surface of the second n-type drift layer 5 on which the epitaxial growth has been performed, an HTO (high temperature oxide) film is formed. Then, an HTO film is etched to form a trench groove opening pattern in the HTO film. Next, the second n-type drift layer 5 and the p-type depletion are formed by anisotropic dry etching such as RIE (reactive ion etching apparatus) using a CF-based gas or an HBr-based gas, using the patterned HTO film as an etching mask 30. A trench 6 penetrating through the region extension layer 4 and reaching the first n-type drift layer 3 is formed.
[0049]
Next, as shown in FIG. 10, an n-type conversion region 7 is formed on the side wall of the trench 6 by using an oblique ion implantation technique. By this ion implantation step, the trench sidewall of the p-type depletion region extension layer 4 also becomes an n-type region, and the entire trench sidewall becomes an n-type region.
[0050]
Next, a gate insulating film 10 is formed on the inner wall of the trench. As shown in FIG. 11, a first silicon oxide film 20 is deposited on the entire surface of the substrate by a CVD method so as to fill the grooves. The first silicon oxide film 20 is deposited at a high density near the trench side wall, and is deposited at a sparse density at the center.
[0051]
Further, an etching mask made of an HTO film is formed, and anisotropic dry etching such as RIE (reactive ion etching apparatus) is performed to form the first silicon oxide film 20 near the trench sidewall as shown in FIG. Etch to the position of 10a. The first silicon oxide film 20 that fills the trench has a high etching rate because the density is high near the trench side wall, and the etching rate is low because the density is low at the center. Therefore, the first silicon oxide film 20 is etched deeper in the center of the trench than in the vicinity of the side wall of the trench.
[0052]
Next, as shown in FIG. 13, a second silicon oxide film is formed on a portion of the trench sidewall above the first silicon oxide film 20. When thermal oxidation is performed on the entire surface of the substrate, the exposed portion of the silicon on the side wall of the trench becomes the second silicon oxide film 21, and the thick gate insulating film 10 is formed at the bottom of the trench together with the first silicon oxide film 20. Can be. The second silicon oxide film may be formed by deposition using a CVD method.
[0053]
Next, as shown in FIG. 14, a buried electrode 11 is formed in the trench. By the CVD method, a polysilicon layer is deposited on the entire surface so as to fill the groove, and phosphorus is injected and diffused at a high concentration to increase the conductivity, thereby forming the buried electrode 11.
[0054]
Next, as shown in FIG. 15, a p-type body layer 8 is formed on the surface of the second n-type drift layer 5 by diffusion, and an n ⁺ -type source region 9 is formed in a region near the trench opening on the surface of the p-type body layer 8. To form
[0055]
Thereafter, in the same manner as a general process for fabricating a MOS FET, an interlayer insulating film, a contact, a source electrode 13 and a drain electrode 14 are formed on the back surface of the n ⁺ semiconductor substrate 2 to complete the MOS FET 100.
[0056]
The formation of the p-type body layer 8 by diffusion can be performed before the etching of the groove 6.
[0057]
There is another method for forming gate insulating films 10 having different thicknesses in the trench. First, after the formation of the trench 6, as shown in FIG. 17, the first silicon oxide film 20 is formed with a thickness that does not completely fill the trench 6. The first silicon oxide film 20 may be formed by thermal oxidation or by depositing a silicon oxide film by a CVD method.
[0058]
Next, as shown in FIG. 18, an organic resist is applied to the entire surface of the substrate and is filled in the trench 6.
[0059]
Next, the resist is etched back to a predetermined depth, and the first silicon oxide film 20 is etched using the etched-back resist as an etching mask as shown in FIG.
[0060]
Next, after the resist is removed, a second silicon oxide film 21 is formed on the first silicon oxide film 20 as shown in FIG. When the entire surface of the substrate is thermally oxidized, the silicon exposed portion on the side wall of the trench becomes a silicon oxide film 21, and together with the silicon oxide film 20, a thick gate insulating film 10 can be formed at the bottom of the trench. The second silicon oxide film may be formed by deposition using a CVD method.
[0061]
Although the above description has been given by taking the manufacturing process of the MOS FET as an example, the present invention can be used for a device having a MOS gate having a trench structure, for example, an IGBT (Insulated Gate Bipolar Transistor).
[0062]
As described above, the embodiments of the present invention have been described with reference to the examples. However, the present invention is not limited to these examples, and may be implemented in various forms without departing from the gist of the present invention. be able to.
[Brief description of the drawings]
FIG. 1 is a cross-sectional structure of a MOS FET 1 according to an embodiment of the present invention.
FIG. 2 is a diagram showing a path of electrons when a MOSFET 1 is turned on according to the embodiment of the present invention.
FIG. 3 is a diagram showing a p / n junction where a depletion layer is formed when a MOS FET1 is turned off according to an embodiment of the present invention.
FIG. 4 is a diagram showing a cross-sectional structure of a MOS FET 100 according to a second embodiment of the present invention.
FIG. 5 is a diagram showing an electric field distribution at the time of breakdown of the MOS FET 100 according to the second embodiment of the present invention.
FIG. 6 is a diagram showing an electric field intensity distribution on an AA cross section in the electric field distribution at the time of breakdown of the MOS FET 100 according to the second embodiment of the present invention.
FIG. 7 is a diagram in which normalized on-resistance (Ω · mm ² ) is plotted with respect to the withstand voltage in order to see the effect of improving the trade-off relationship between the withstand voltage and the on-resistance of the MOS FET 100 according to the second embodiment of the present invention. is there.
FIG. 8 is a process diagram for explaining a manufacturing process of the MOS FET 100 according to the second embodiment of the present invention, and is a diagram showing a stack after epitaxial growth.
FIG. 9 is a process diagram for describing a manufacturing process of the MOS FET 100 according to the second embodiment of the present invention, and is a diagram showing a cross-sectional shape of a groove.
FIG. 10 is a process diagram for explaining a manufacturing process of the MOS FET 100 according to the second embodiment of the present invention, and is a diagram showing formation of an n-type conversion region.
FIG. 11 is a process diagram for describing a manufacturing process of the MOS FET 100 according to the second embodiment of the present invention, and is a diagram illustrating a process of depositing a first silicon oxide film in a trench.
FIG. 12 is a process diagram for describing a manufacturing process of the MOS FET 100 according to the second embodiment of the present invention, which is a cross-sectional view showing an etched shape of a first silicon oxide film.
FIG. 13 is a process diagram for describing a manufacturing process of the MOS FET 100 according to the second embodiment of the present invention, and is a diagram illustrating a process of forming a gate insulating film in a portion above a thickness boundary of a trench sidewall. .
FIG. 14 is a process diagram for describing a manufacturing process of the MOS FET 100 according to the second embodiment of the present invention, and is a diagram illustrating a process of forming a buried electrode.
FIG. 15 is a process diagram for describing the manufacturing process of the MOS FET 100 according to the second embodiment of the present invention, which illustrates the formation of the p-type body layer 8 and the n ⁺ -type source region 9.
FIG. 16 is a process diagram for explaining a manufacturing process of the MOS FET 100 according to the second embodiment of the present invention, and is a diagram showing formation of a source electrode and a drain electrode 14.
FIG. 17 is a process diagram for explaining another method for forming gate insulating films having different thicknesses, and is a diagram showing a process for forming a first silicon oxide film in a trench.
FIG. 18 is a process diagram for explaining another method for forming gate insulating films having different thicknesses, and is a diagram showing a process of filling a groove with a resist.
FIG. 19 is a process diagram for explaining another method for forming gate insulating films having different thicknesses, and shows a process of etching the first silicon oxide film using the etched back resist as an etching mask. FIG.
FIG. 20 is a process diagram for explaining another method for forming gate insulating films having different thicknesses, and is a diagram showing a process for forming a second silicon oxide film.
FIG. 21 is a sectional view of an IGBT 200 according to Embodiment 3 of the present invention.
[Explanation of symbols]
1,100 MOS FET, 2 n ⁺ type substrate, 3 first n type drift layer, 4 p type depletion region extension layer, 5 second n type drift layer, 6 groove, 7 n type conversion region, 8 p type body layer, 9 n ⁺ type source region, 10 gate insulating film, 11 buried electrode (gate electrode), 12 interlayer insulating film, 13 source electrode, 14 drain electrode, 20 first silicon oxide film, 21 second silicon oxide film, 30 Etching mask, 32 resist, 33p ⁺ type substrate, 200 IGBT.

Claims (8)

In a power trench gate type semiconductor device having a gate electrode embedded in a groove via a gate insulating film,
a first n (p) -type drift layer formed on an n (p) -type semiconductor substrate;
A p (n) -type depletion region extension layer formed on the surface of the first n (p) -type drift layer;
A second n (p) -type drift layer formed on the surface of the p (n) -type depletion region extension layer;
A p (n) -type body layer formed on the surface of the second n (p) -type drift layer;
An n (p) -type source region formed on the surface of the p (n) -type body layer;
With
The trench penetrates through the n (p) type source region, the p (n) type body layer, the second n (p) drift layer, and the p (n) type depletion region extension layer to form the first n ( formed to reach the p) type drift layer,
A power trench gate type semiconductor device comprising an n (p) type conversion region converted to n (p) type near a side wall of the trench of the p (n) type depletion region extension layer. The power trench gate type semiconductor device according to claim 1, wherein:
The thickness of the gate insulating film in contact with the p (n) -type body layer is equal to the thickness of the gate insulating film in contact with the p (n) -type depletion region extension layer and the first n (p) -type drift layer. A power trench gate type semiconductor device characterized by being thinner than that. The power trench gate type semiconductor device according to claim 1 or 2, wherein:
The power trench gate type semiconductor device according to claim 1, wherein the impurity concentration of the first n (p) type drift layer is lower than that of the second n (p) type drift layer. The power trench gate type semiconductor device according to claim 1, wherein:
A power trench type semiconductor device, wherein the substrate is a semiconductor substrate having a polarity opposite to that of the first n (p) type drift layer. The power trench gate type semiconductor device according to claim 1, wherein:
The thickness of the gate insulating film in contact with the upper part of the p (n) type body layer is the lower part of the p (n) type body layer, the second n (p) type drift layer, and the p (n) type depletion region extension layer And a power trench gate semiconductor device having a thickness smaller than a thickness of the gate insulating film in contact with the first n (p) type drift layer. A method of manufacturing a power trench gate type semiconductor device including a gate electrode embedded in a groove via a gate insulating film,
epitaxially growing a first n (p) -type drift layer, a p (n) -type depletion region extension layer, and a second n (p) -type drift layer on an n (p) -type semiconductor substrate,
The first n (p) penetrating through the n (p) type source region, the p (n) type body layer, the second n (p) type drift layer, and the p (n) type depletion region extension layer Forming a groove reaching the mold drift layer;
Forming an n (p) type conversion region converted to n (p) type near the side wall of the groove of the p (n) type depletion region extension layer;
A method for manufacturing a power trench gate type semiconductor device, comprising: A method for manufacturing a power trench gate type semiconductor device according to claim 6,
Depositing a first silicon oxide film to fill the trench;
Etching the first silicon oxide film to a predetermined depth by an anisotropic dry etching method,
Forming a second silicon oxide film thinner than the thickness of the first silicon oxide film on the inner wall of the groove where the first silicon oxide film is etched;
A method for manufacturing a power trench gate type semiconductor device, comprising: A method for manufacturing a power trench gate type semiconductor device according to claim 6,
Forming a first silicon oxide film on the inner wall of the groove;
Filling the groove in which the first silicon oxide film is formed with a resist,
A step of etching back the resist to a predetermined depth,
Etching the first silicon oxide film using the etched back resist as an etching mask,
Forming a second silicon oxide film thinner than the thickness of the first silicon oxide film on the inner wall of the groove where the first silicon oxide film is etched;
A method for manufacturing a power trench gate type semiconductor device, comprising:

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