JP2004363122A - Nonvolatile semiconductor memory device and method of manufacturing nonvolatile semiconductor memory device - Google Patents

Abstract

An object of the present invention is to remove a defect layer on a surface of a semiconductor substrate while suppressing deterioration of the shape of a sidewall spacer.
SOLUTION: By performing anisotropic etching of a silicon oxide film laminated on a semiconductor substrate 1, side wall spacers 8a and 8b are formed on side walls of a control gate electrode 7 and a floating gate electrode 4, respectively, and then oxidized. By etching the surface of the semiconductor substrate 1 under the condition that the selectivity of the silicon oxide film to Si is smaller than that of the etching of the silicon film, the dug portions 9a and 9b from which the surface layer on the semiconductor substrate 1 has been removed are removed. Form.
[Selection diagram] Fig. 4

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the nonvolatile semiconductor memory device, and is particularly suitable for application to a split gate flash memory cell.
[0002]
[Prior art]
In a conventional split gate type flash memory cell, for example, as disclosed in Patent Document 1, in order to reduce the electric field applied to the drain layer when a high voltage is applied to the control gate electrode, the control gate electrode In some cases, sidewall spacers are provided on side walls.
[0003]
On the other hand, when an element isolation film such as STI (Shallow Trench Isolation) is formed on a semiconductor substrate in order to isolate a memory cell from an element, a fine crack is generated on the surface of the semiconductor substrate, and a leak current flows on the surface of the semiconductor substrate. Therefore, the characteristics are deteriorated. For this reason, the surface of the semiconductor substrate has been removed by performing over-etching when forming the sidewall spacer.
[0004]
[Patent Document 1]
JP-A-2002-299777
[0005]
[Problems to be solved by the invention]
However, when the surface of the semiconductor substrate is etched under the same conditions as the etching conditions of the sidewall spacer, the amount of overetching of the sidewall spacer also increases. For this reason, the shape of the sidewall spacer becomes triangular, and it becomes difficult to control the shape of the sidewall spacer, so that there is a problem that the variation of the threshold value Vth of the memory cell becomes large.
[0006]
Therefore, an object of the present invention is to provide a nonvolatile semiconductor memory device capable of removing a defect layer on the surface of a semiconductor substrate while suppressing the deterioration of the shape of a sidewall spacer, and a method of manufacturing the nonvolatile semiconductor memory device. It is.
[0007]
[Means for Solving the Problems]
According to one embodiment of the present invention, there is provided a nonvolatile semiconductor memory device, comprising: a floating gate electrode formed on a semiconductor substrate via a first gate insulating film; A control gate electrode formed on the semiconductor substrate such that an end is formed on the oxide layer with a second gate insulating film interposed therebetween, and a control gate electrode and a floating gate electrode. Side wall spacers respectively provided on the side walls, at least a lower region of which is vertically steep, a source layer formed in the semiconductor substrate on the floating gate electrode side, and formed in the semiconductor substrate on the control gate electrode side A drain layer, and a semiconductor substrate on which the drain layer and the source layer are formed. Characterized in that it comprises a surface layer is removed surface layer removal region of.
[0008]
This makes it possible to stably control the shape of the sidewall spacer, reduce the variation in the threshold value of the memory cell, and remove the defect layer on the surface of the semiconductor substrate. In addition, it is possible to reduce the leak current on the surface of the semiconductor substrate.
Further, according to the nonvolatile semiconductor memory device of one embodiment of the present invention, the floating gate electrode formed on the semiconductor substrate via the first gate insulating film, and the oxide layer formed on the floating gate electrode A control gate electrode formed on the semiconductor substrate such that an end of the control gate electrode extends over the oxide layer via a second gate insulating film; and a control gate electrode provided on sidewalls of the control gate electrode and the floating gate electrode. A side wall spacer whose lower region is stood vertically, a source layer formed in the semiconductor substrate on the floating gate electrode side, and a drain formed in the semiconductor substrate via the side wall spacer on the control gate electrode side A layer and a surface of the drain layer and the source layer. Characterized in that it comprises a dug portion.
[0009]
This makes it possible to remove the surface layers of the drain layer and the source layer in a state where the lower region of the side wall spacer is stood vertically, and it is possible to stably control the shape of the side wall spacer. This makes it possible to remove a defect layer on the surface of the semiconductor substrate. For this reason, it is possible to reduce the variation in the threshold value of the memory cell, reduce the leakage current on the surface of the semiconductor substrate, and improve the manufacturing yield of the nonvolatile semiconductor memory device. Become.
[0010]
Further, according to the nonvolatile semiconductor memory device of one embodiment of the present invention, the first silicide layer formed on the drain layer is separated from the end of the control gate electrode on the oxide layer by a predetermined distance, A second silicide layer formed on the control gate electrode.
Thereby, even when the end portion of the control gate electrode is arranged on the floating gate electrode, short-circuit between the second silicide layer on the control gate electrode and the floating gate electrode is prevented, and the control gate electrode and the drain are prevented. It is possible to reduce the resistance of the layer.
[0011]
Further, according to the nonvolatile semiconductor memory device of one embodiment of the present invention, the depth of the dug portion is in a range of 200 to 500 °.
As a result, it is possible to form a dug portion on the surface of the semiconductor substrate while suppressing an increase in the resistance of the source layer and the drain layer, and to reduce the leakage current on the surface of the semiconductor substrate while suppressing the deterioration of the operation characteristics. It becomes possible.
[0012]
According to the method for manufacturing a nonvolatile semiconductor memory device of one embodiment of the present invention, the step of forming a first gate insulating film on a semiconductor substrate and the step of forming a floating gate electrode provided with an oxide layer on A step of forming a second gate insulating film on the semiconductor substrate, a step of forming a second gate insulating film on the semiconductor substrate, and one end disposed on the oxide layer; Forming a control gate electrode having the other end disposed thereon, forming a source layer in the semiconductor substrate on the floating gate electrode side, and forming an insulating film on the semiconductor substrate on which the source layer is formed. Stacking and etching the insulating film to form sidewall spacers on sidewalls of the control gate electrode and the floating gate electrode Forming a drain layer in the semiconductor substrate on the side of the control gate electrode, and the step of forming a drain layer in the semiconductor substrate on the control gate electrode side. Etching step.
[0013]
Thus, by changing the etching conditions at the time of forming the sidewall spacer, the surface of the semiconductor substrate can be etched while suppressing the sidewall spacer from being etched. For this reason, it is possible to stably control the shape of the sidewall spacer while suppressing the complexity of the manufacturing process, and it is also possible to suppress a variation in the height of the control gate electrode, thereby reducing the memory cell size. It is possible to reduce the variation in the threshold value and to remove the defect layer on the surface of the semiconductor substrate, thereby reducing the leak current on the surface of the semiconductor substrate.
[0014]
According to the method for manufacturing a nonvolatile semiconductor memory device of one embodiment of the present invention, the step of forming the first gate insulating film on the semiconductor substrate and the step of forming the first gate insulating film on the semiconductor substrate on which the first gate insulating film is formed Forming a first polycrystalline silicon layer, forming an antioxidant film on the first polycrystalline silicon layer, forming an opening in the antioxidant film, and forming the opening. Forming a oxidized layer on the first polycrystalline silicon layer by performing thermal oxidation of the first polycrystalline silicon layer using the antioxidant film as a mask; removing the antioxidant film; Forming a floating gate electrode having the oxide layer thereon by etching the first polycrystalline silicon layer using the oxide layer as a mask, and forming a second gate insulating film on the semiconductor substrate Stacking a second polycrystalline silicon layer on the semiconductor substrate on which the second gate insulating film is formed, and patterning the second polycrystalline silicon layer so that one end is disposed on the oxide layer. Forming a control gate electrode having the other end disposed on the semiconductor substrate via the second gate insulating film; and forming a first photoresist layer covering the semiconductor substrate on the control gate electrode side. Forming a source layer in the semiconductor substrate on the floating gate electrode side by performing ion implantation using the first photoresist layer, the floating gate electrode, and the control gate electrode as a mask; Laminating an insulating film on the semiconductor substrate on which the source layer is formed, and etching the insulating film; Forming a sidewall spacer on the side wall of the control gate electrode and the floating gate electrode, and the condition that the selectivity of the insulating film with respect to the semiconductor substrate is smaller than the etching of the insulating film. Etching; forming a second photoresist layer covering the semiconductor substrate on the floating gate electrode side; and forming the second photoresist layer, the floating gate electrode, the control gate electrode, and the sidewall spacer. Forming a drain layer in the semiconductor substrate on the control gate electrode side by performing ion implantation using the mask as a mask.
[0015]
Thus, by changing the etching conditions at the time of forming the sidewall spacer, the surface of the semiconductor substrate can be etched while suppressing the etching of the sidewall spacer, and the threshold value of the memory cell varies. And the leakage current on the surface of the semiconductor substrate can be reduced.
[0016]
According to the method for manufacturing a nonvolatile semiconductor memory device of one embodiment of the present invention, a step of forming an oxide film covering the source layer so that an end of the oxide film covers the control gate electrode; Forming a silicide-forming metal film on the semiconductor substrate on which is formed, and reacting the silicide-forming metal film with silicon to form a silicide layer on the drain layer and the control gate electrode. Is further provided.
[0017]
This makes it possible to form the silicide layer at a predetermined distance from the end of the control gate electrode on the oxide layer, and to form the silicide layer on the drain layer without forming the silicide layer on the source layer. It can be formed. Therefore, even when the end of the control gate electrode is disposed on the floating gate electrode, short-circuit between the silicide layer on the control gate electrode and the floating gate electrode is prevented, and the control gate electrode and the drain layer are prevented from being short-circuited. Low resistance can be achieved.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a nonvolatile semiconductor memory device and a method of manufacturing the same according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a plan view showing a schematic configuration of a nonvolatile semiconductor memory device according to one embodiment of the present invention.
[0019]
In FIG. 1, a floating gate electrode 4 is provided in a memory cell, and a drain layer 10a and a source layer 10b are provided on both sides of the floating gate electrode 4, respectively.
The memory cells provided with the floating gate electrodes 4 are arranged in a matrix, the drain layer 10a is shared by a pair of memory cells adjacent in the column direction, and the pair of memory cells sharing the drain layer 10a is , STI2 in the row direction.
[0020]
A source layer 10b extending in the row direction is arranged on the opposite side of the drain layer 10a with the floating gate electrode 4 interposed therebetween, and the source layer 10b is shared by two rows of memory cells adjacent in the column direction. .
Further, word lines WL1 to WL6 are arranged in the row direction such that the end portions extend over the floating gate electrode 4. In the column direction, bit lines BL1 to BL7 are provided so as to intersect with the word lines WL1 to WL6, and the bit lines BL1 to BL7 are connected to the drain layer 10a via bit contacts H1. ing. A source line Vss is provided in the column direction, and the source line Vss is connected to each source layer 10b via a source contact H2.
[0021]
FIG. 2A is a cross-sectional view taken along the line AA ′ of FIG. 1, and FIG. 2B is a cross-sectional view taken along the line BB ′ of FIG.
In FIG. 2, an STI 2 for separating the drain layer 10a in the row direction (BB ′ direction) is embedded in the semiconductor substrate 1. On the semiconductor substrate 1 in which the STI 2 is embedded, a floating gate electrode 4 is formed via a gate insulating film 3, and an oxide layer 5 is formed on the floating gate electrode 4. Further, a control gate electrode 7 having one end disposed on the floating gate electrode 4 via the oxide layer 5 and the other end disposed on the semiconductor substrate 1 via the gate insulating film 6 is formed. The control gate electrodes 7 arranged in the same row are connected to the common word lines WL1 to WL6 in FIG.
[0022]
Sidewall spacers 8a and 8b are formed on the side walls of the control gate electrode 7 and the floating gate electrode 4, respectively, at least in a state where the lower region is vertically raised. The semiconductor substrate 1 on the side of the control gate electrode 7 has a dug portion 9a from which the surface layer on the semiconductor substrate 1 has been removed, and the semiconductor substrate 1 on the side of the floating gate electrode 4 has a semiconductor substrate. A dug portion 9b is formed by removing the surface layer on the semiconductor substrate 1, and a crack layer on the surface of the semiconductor substrate 1 generated by the formation of the STI 2 is removed.
[0023]
A drain layer 10a is formed in the semiconductor substrate 1 on the side of the floating gate electrode 4 provided with the engraved portion 9b, and the semiconductor substrate on the side of the control gate electrode 7 provided with the engraved portion 9a. 1, a source layer 10b is formed. A silicide layer 11a is formed on the drain layer 10a, and a silicide layer 11b is formed on the control gate electrode 7 at a predetermined distance from an end of the control gate electrode 7 on the oxide layer 5. I have. Then, on the control gate electrode 7, a bit line BL is formed in the column direction (AA ′ direction) with an interlayer insulating film 12 interposed therebetween.
[0024]
When the erasing operation of the memory cell of FIG. 2 is performed, the source wiring Vss of FIG. 1 is held at the ground potential, the source layers 10b of all the memory cells are held at the ground potential, and all the bit lines BL1 to BL7 are held. Are held at the ground potential, and the drain layers 10a of all the memory cells are held at the ground potential. Further, a high voltage of 11 to 13 V is applied to the selected word lines WL1 to WL6, and a high voltage of 11 to 13 V is applied to the control gate electrode 7 of the memory cell connected to the selected word lines WL1 to WL6. At the same time, the unselected word lines WL1 to WL6 are held at the ground potential, and the control gate electrodes 7 of the memory cells connected to the unselected word lines WL1 to WL6 are held at the ground potential.
[0025]
When a high voltage of 11 to 13 V is applied to the control gate electrode 7 in a state where the drain layer 10a and the source layer 10b are held at the ground potential, the voltage between the control gate electrode 7 and the floating gate electrode 4 is increased. A high electric field is applied, and a FN (Fowler Nordheim) tunnel current flows between the control gate electrode 7 and the floating gate electrode 4. For this reason, the electrons of the floating gate electrode 4 are extracted to the control gate electrode 7 side, and the data stored in the selected memory cell can be erased.
[0026]
Here, as shown in FIG. 2A, the oxide layer 5 on the floating gate electrode 4 is formed in an elliptical shape, and the end of the floating gate electrode 4 is sharpened so that the end of the floating gate electrode 4 is formed. The electric field can be concentrated. Therefore, electrons of the floating gate electrode 4 can be efficiently extracted to the control gate electrode 7 side, and the number of times of rewriting can be increased, so that the life of the split gate type flash memory can be improved.
[0027]
In the split gate type flash memory, the erasing operation is performed on all the memory cells connected to the selected word lines WL1 to WL6 at once, and all the word lines WL1 to WL6 are selected at the same time. Thereby, the erasing operation of all the memory cells can be performed collectively.
Next, when performing the write operation of the memory cell of FIG. 2, a high voltage of 10 to 11 V is applied to the source wiring Vss of FIG. 1, and a high voltage of 10 to 11 V is applied to the source layer 10b of all the memory cells. . In addition, a voltage of 1 V is applied to the selected bit lines BL1 to BL7, and a voltage of 1 V is applied to the drain layer 10a of the memory cell connected to the selected bit lines BL1 to BL7. A voltage of 2 V is applied to the lines BL1 to BL7, and a voltage of 2 V is applied to the drain layer 10a of the memory cell connected to the unselected bit lines BL1 to BL7. Further, a low voltage of 1.8 V is applied to the selected word lines WL1 to WL6, and a low voltage of 1.8 V is applied to the control gate electrode 7 of the memory cell connected to the selected word lines WL1 to WL6. At the same time, the unselected word lines WL1 to WL6 are held at the ground potential, and the control gate electrodes 7 of the memory cells connected to the unselected word lines WL1 to WL6 are held at the ground potential.
[0028]
If the threshold Vth of the channel region below the control gate electrode 7 is, for example, 0.5 V, the channel region of the memory cell connected to the selected word line WL1 to WL6 is in an inverted state. . For this reason, when 1 V is applied to the drain layer 10a via the selected bit lines BL1 to BL7, the memory cells connected to the selected word lines WL1 to WL6 include the source layer 10b to the drain layer A current flows toward 10a. On the other hand, when the threshold value Vth of the channel region below the control gate electrode 7 is, for example, 0.5 V, the channel region of the memory cell connected to the unselected word lines WL1 to WL6 is in a depleted state. No current flows from the source layer 10b to the drain layer 10a in the memory cells connected to the selected word lines WL1 to WL6.
[0029]
Since a high voltage of 10 to 11 V is applied to the source layer 10b, the potential of the floating gate electrode 4 is raised by capacitive coupling between the source layer 10b and the floating gate electrode 4, and the channel region and the floating gate electrode 4, a high electric field is generated. Therefore, when a current flows from the source layer 10b toward the drain layer 10a, electrons flowing in the channel region are accelerated by a high electric field to become hot electrons, and electrons are injected into the floating gate electrode 4. As a result, charges are accumulated in the memory cells connected to the selected word lines WL1 to WL6 and the bit lines BL1 to BL7, and data can be written to the selected memory cells.
[0030]
Next, when the read operation of the memory cell in FIG. 2 is performed, the source wiring Vss in FIG. 1 is held at the ground potential, and the source layers 10b of all the memory cells are held at the ground potential. In addition, a low voltage of 1 V is applied to the selected bit lines BL1 to BL7, a low voltage of 1 V is applied to the drain layer 10a of the memory cell connected to the selected bit lines BL1 to BL7, and a non-selection is performed. Of the memory cells connected to the unselected bit lines BL1 to BL7 are held at the ground potential. Further, a voltage of 3 ± 0.3 V is applied to the selected word lines WL 1 to WL 6, and a voltage of 3 ± 0.3 V is applied to the control gate electrode 7 of the memory cell connected to the selected word lines WL 1 to WL 6. , The non-selected word lines WL1 to WL6 are held at the ground potential, and the control gate electrodes 7 of the memory cells connected to the unselected word lines WL1 to WL6 are held at the ground potential.
[0031]
When the memory cells selected by the bit lines BL1 to BL7 and the word lines WL1 to WL6 are in the erased state, the electrons of the floating gate electrode 4 of the selected memory cell are extracted. Therefore, the channel region below the floating gate electrode 4 of the memory cell in the erased state is turned on, and when 1 V is applied to the drain layer 10a via the selected bit lines BL1 to BL7, the selected memory cell is selected. A current flows from the drain layer 10a to the source layer 10b in the memory cells connected to the word lines WL1 to WL6.
[0032]
On the other hand, when the memory cells selected by the bit lines BL1 to BL7 and the word lines WL1 to WL6 are in a write state, electrons are accumulated in the floating gate electrode 4 of the selected memory cell. For this reason, the channel region under the floating gate electrode 4 of the memory cell in the written state is off, and even if 1 V is applied to the drain layer 10a via the selected bit lines BL1 to BL7, the selection is not performed. In the memory cells connected to the selected word lines WL1 to WL6, the current flowing from the drain layer 10a toward the source layer 10b becomes smaller than in the erased state. Therefore, by detecting the magnitude of the current flowing through the selected memory cell by the sense amplifier, the erased state and the written state of the selected memory cell can be determined.
[0033]
In addition, the non-selected word lines WL1 to WL6 are held at the ground potential, and the control gate electrodes 7 of the memory cells connected to the unselected word lines WL1 to WL6 are held at the ground potential. The lower channel region can be turned off. Therefore, even when the unselected memory cells are in the over-erased state, it is possible to prevent the unselected memory cells from being constantly in the conductive state, and to perform the read operation of the selected memory cells normally. Becomes possible.
[0034]
Here, the lower regions of the side wall spacers 8a and 8b in FIG. 2 are vertically cut, and the dug portions 9a and 9b from which the surface layer on the semiconductor substrate 1 is removed are formed. The shape control of 8a and 8b can be stably performed, and the defect layer on the surface of the semiconductor substrate 1 can be removed. For this reason, it is possible to reduce the variation in the threshold value of the memory cell, to reduce the leak current on the surface of the semiconductor substrate 1, and to improve the manufacturing yield of the nonvolatile semiconductor memory device. It becomes.
[0035]
In addition, it is preferable that the depth of the dug portions 9a and 9b be in the range of 200 to 500 °. This makes it possible to form a dug portion on the surface of the semiconductor substrate 1 while suppressing an increase in the resistance of the source layer 10b and the drain layer 10a. The current can be reduced.
[0036]
Further, a silicide layer is not formed on the drain layer 10b, and a silicide layer 11b is formed on the control gate electrode 7 at a predetermined distance from an end of the control gate electrode 7 on the oxide layer 5. Thus, even when the end of control gate electrode 7 is arranged on floating gate electrode 4, short-circuit between silicide layer 11b on control gate electrode 7 and floating gate electrode 4 is prevented, and the control gate It is possible to reduce the resistance of the electrode 11b and the drain layer 9a.
[0037]
3 to 5 are cross-sectional views illustrating a method for manufacturing a nonvolatile semiconductor memory device according to one embodiment of the present invention.
In FIG. 3A, a gate insulating film 3 is formed on the semiconductor substrate 1 by thermal oxidation. Then, a polycrystalline silicon layer 4 'is laminated on the semiconductor substrate 1 on which the gate insulating film 3 is formed by a method such as CVD, and an oxidation preventing film 21 such as a silicon nitride film is formed on the polycrystalline silicon layer 4'. .
[0038]
Next, as shown in FIG. 3B, an opening 21 'is formed in the oxidation preventing film 21 by patterning the oxidation preventing film 21 using a photolithography technique and an etching technique.
Next, as shown in FIG. 3C, the polycrystalline silicon layer 4 'is thermally oxidized using the antioxidant film 21 in which the opening 21' is formed as a mask, thereby forming an upper portion of the polycrystalline silicon layer 4 '. Oxide layer 5 is formed selectively.
[0039]
Next, as shown in FIG. 3D, the oxidation preventing film 21 on the polycrystalline silicon layer 4 'is removed. Then, the polysilicon layer 4 'is etched using the oxide layer 5 selectively formed on the polysilicon layer 4' as a mask to form the floating gate electrode 4 having the oxide layer 5 on the top.
Next, as shown in FIG. 4A, a gate insulating film 6 is formed on the semiconductor substrate 1 by thermal oxidation. Then, a polycrystalline silicon layer is stacked on the semiconductor substrate 1 on which the gate insulating film 6 is formed by a method such as CVD. Then, by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique, one end is arranged on the floating gate electrode 4 via the oxide layer 5 and on the semiconductor substrate 1 via the gate insulating film 6. A control gate electrode 7 having the other end is formed.
[0040]
Next, as shown in FIG. 4B, a photoresist layer R1 that covers the semiconductor substrate 1 on the control gate electrode 7 side is formed by using a photolithography technique. Then, ion implantation is performed on the semiconductor substrate 1 using the photoresist layer R1, the floating gate electrode 4, and the control gate electrode 7 as a mask, thereby forming the source layer 10b in the semiconductor substrate 1 on the floating gate electrode 4 side.
[0041]
Next, as shown in FIG. 4C, the photoresist layer R1 is removed. Then, a silicon oxide film is stacked on the semiconductor substrate 1 on which the source layer 10b is formed by a method such as CVD. Then, by performing anisotropic etching of the silicon oxide film stacked on the semiconductor substrate 1, sidewall spacers 8a and 8b are formed on the side walls of the control gate electrode 7 and the floating gate electrode 4, respectively. Here, when etching the silicon oxide film, it is preferable to etch the silicon oxide film under the condition that the selectivity of the silicon oxide film to Si is large. For example, as a condition for etching a silicon oxide film, CHF ₃ / CF ₄ A mixed gas containing / Ar can be used. Specifically, for example, CHF ₃ / CF ₄ The flow rate of / Ar can be set to 30 sccm, 30 sccm, and 600 sccm, respectively, and the power can be set to 1300 W.
[0042]
Thus, the silicon oxide film can be efficiently etched while suppressing the variation in the height of the control gate electrode 7, and the shape control of the sidewall spacers 8a and 8b can be stably performed.
Next, as shown in FIG. 4D, when the surface of the semiconductor substrate 1 is exposed during the etching for forming the sidewall spacers 8a and 8b, the etching conditions are switched to etch the surface of the semiconductor substrate 1. This forms the dug portions 9a and 9b from which the surface layer on the semiconductor substrate 1 has been removed.
[0043]
Here, when etching the surface of the semiconductor substrate 1, it is preferable to etch the surface of the semiconductor substrate 1 under the condition that the selectivity of the silicon oxide film to Si is smaller than that of the etching of the silicon oxide film. For example, when etching the surface of the semiconductor substrate 1, a condition for etching a silicon nitride film can be used. ₃ / CF ₄ / Ar / O ₂ Can be used. Specifically, for example, CHF ₃ / CF ₄ / Ar / O ₂ Can be set to 5 sccm, 70 sccm, 800 sccm, and 13 sccm, respectively, and the power can be set to 500 W.
[0044]
Thus, by changing the etching conditions at the time of forming the sidewall spacers 8a and 8b, the surface of the semiconductor substrate 1 can be etched while suppressing the etching of the sidewall spacers 8a and 8b. For this reason, it is possible to stably control the shape of the sidewall spacers 8a and 8b while suppressing the complexity of the manufacturing process, and it is also possible to suppress a variation in the height of the control gate electrode 7. In addition, it is possible to reduce the variation in the threshold value of the memory cell, and it is also possible to remove the defect layer on the surface of the semiconductor substrate 1, thereby reducing the leak current on the surface of the semiconductor substrate 1.
[0045]
Further, when the surface of the semiconductor substrate 1 is etched, by monitoring the end point signal, it becomes possible to stably switch the etching conditions when the surface of the semiconductor substrate 1 is exposed, and the engraved portions 9a, 9b Can be accurately controlled.
Next, as shown in FIG. 5A, a photoresist layer R2 covering the semiconductor substrate 1 on the floating gate electrode 4 side is formed by using photolithography technology. Then, ion implantation is performed on the semiconductor substrate 1 using the photoresist layer R2, the floating gate electrode 4, the control gate electrode 7, and the sidewall spacers 8a and 8b as masks, so that a drain layer is formed in the semiconductor substrate 1 on the control gate electrode 7 side. 10a is formed.
[0046]
Next, as shown in FIG. 5B, the photoresist layer R2 is removed. Then, a silicon oxide film 22 is stacked on the semiconductor substrate 1 on which the drain layer 10a is formed by a method such as CVD. Then, by using a photolithography technique and an etching technique, the silicon oxide film 22 is patterned so as to cover the source layer 10b such that the end portion is over the control gate electrode 7. Then, a metal film 23 for forming silicide such as W or Mo is laminated on the entire surface by a method such as sputtering.
[0047]
Next, as shown in FIG. 5C, the silicide-forming metal film 23 is reacted with Si by heat treatment to form silicide layers 11a and 11b on the drain layer 10a and the control gate electrode 7, respectively.
Thus, silicide layer 11b can be formed at a predetermined distance from the end of control gate electrode 7 on oxide layer 5, and drain layer 10a can be formed without forming a silicide layer on source layer 10b. The silicide layer 11 can be formed thereon. Therefore, even when the end of the control gate electrode 7 is arranged on the floating gate electrode 4, the short-circuit between the silicide layer 11b on the control gate electrode 7 and the floating gate electrode 4 is prevented while the control gate electrode 7 is short-circuited. It is possible to reduce the resistance of the electrode 7 and the drain layer 10a.
[Brief description of the drawings]
FIG. 1 is a plan view showing a configuration of a nonvolatile semiconductor memory device according to one embodiment.
FIG. 2 is a cross-sectional view illustrating a configuration of a nonvolatile semiconductor memory device according to one embodiment.
FIG. 3 is a diagram showing a method for manufacturing the nonvolatile semiconductor memory device according to one embodiment.
FIG. 4 is a diagram showing a method for manufacturing the nonvolatile semiconductor memory device according to one embodiment.
FIG. 5 is a diagram showing a method for manufacturing the nonvolatile semiconductor memory device according to one embodiment.
[Explanation of symbols]
WL1 to WL6 Word line, BL1 to BL7, BL bit line Vss source wiring, H1 bit contact, H2 source contact, 1 semiconductor substrate, 2 STI, 3, 6 gate insulating film, 4 floating gate electrode, 5 oxide layer, 7 control Gate electrode, 8a, 8b sidewall spacer, 9a, 9b dug portion, 10a drain layer, 10b source layer, 11a, 11b silicide layer, 12 interlayer insulating film, 4 'polycrystalline silicon layer, 21 antioxidant film, 21 ´ Opening, P1, P2 ion implantation, R1, R2 photoresist

Claims (7)

A floating gate electrode formed on the semiconductor substrate via the first gate insulating film;
An oxide layer formed on the floating gate electrode;
A control gate electrode formed on the semiconductor substrate such that an end of the control gate electrode extends over the oxide layer via a second gate insulating film;
Sidewall spacers respectively provided on the side walls of the control gate electrode and the floating gate electrode, and at least the lower region is vertically stood up,
A source layer formed in the semiconductor substrate on the floating gate electrode side,
A drain layer formed in the semiconductor substrate on the control gate electrode side,
A non-volatile semiconductor memory device, comprising: a surface layer removal region in which a surface layer of a semiconductor substrate on which the drain layer and the source layer are formed is removed. A floating gate electrode formed on the semiconductor substrate via the first gate insulating film;
An oxide layer formed on the floating gate electrode;
A control gate electrode formed on the semiconductor substrate such that an end of the control gate electrode extends over the oxide layer via a second gate insulating film;
Sidewall spacers respectively provided on the side walls of the control gate electrode and the floating gate electrode, and at least the lower region is vertically stood up,
A source layer formed in the semiconductor substrate on the floating gate electrode side,
A drain layer formed in the semiconductor substrate via a sidewall spacer on the control gate electrode side,
A non-volatile semiconductor memory device, comprising: a dug portion formed on a surface of the drain layer and the source layer. A first silicide layer formed on the drain layer;
3. The nonvolatile semiconductor memory device according to claim 2, further comprising a second silicide layer formed on said control gate electrode at a predetermined distance from an end of said control gate electrode on said oxide layer. 4. The nonvolatile semiconductor memory device according to claim 2, wherein the depth of the dug portion is in a range of 200 to 500 [deg.]. Forming a first gate insulating film on a semiconductor substrate;
Forming a floating gate electrode provided with an oxide layer on the first gate insulating film;
Forming a second gate insulating film on the semiconductor substrate;
Forming a control gate electrode having one end disposed on the oxide layer and the other end disposed on the semiconductor substrate via the second gate insulating film;
Forming a source layer in the semiconductor substrate on the floating gate electrode side;
Laminating an insulating film on the semiconductor substrate on which the source layer is formed,
Forming a sidewall spacer on a side wall of the control gate electrode and the floating gate electrode by etching the insulating film;
Forming a drain layer in the semiconductor substrate on the control gate electrode side,
Etching the surface of the semiconductor substrate under the condition that the selectivity of the insulating film to the semiconductor substrate is smaller than the etching of the insulating film. Forming a first gate insulating film on a semiconductor substrate;
Laminating a first polycrystalline silicon layer on the semiconductor substrate on which the first gate insulating film is formed;
Forming an antioxidant film on the first polycrystalline silicon layer;
Forming an opening in the antioxidant film;
Forming an oxide layer on the first polycrystalline silicon layer by thermally oxidizing the first polycrystalline silicon layer using the antioxidant film in which the opening is formed as a mask;
Removing the antioxidant film;
Forming a floating gate electrode having the oxide layer thereon by etching the first polysilicon layer using the oxide layer as a mask;
Forming a second gate insulating film on the semiconductor substrate;
Laminating a second polycrystalline silicon layer on the semiconductor substrate on which the second gate insulating film is formed;
Forming a control gate electrode having one end disposed on the oxide layer and the other end disposed on the semiconductor substrate via the second gate insulating film by patterning the second polycrystalline silicon layer; When,
Forming a first photoresist layer covering the semiconductor substrate on the control gate electrode side;
Forming a source layer in the semiconductor substrate on the floating gate electrode side by performing ion implantation using the first photoresist layer, the floating gate electrode, and the control gate electrode as a mask;
Laminating an insulating film on the semiconductor substrate on which the source layer is formed,
Forming a sidewall spacer on a side wall of the control gate electrode and the floating gate electrode by etching the insulating film;
Etching the surface of the semiconductor substrate under the condition that the selectivity of the insulating film to the semiconductor substrate is smaller than the etching of the insulating film;
Forming a second photoresist layer covering the semiconductor substrate on the floating gate electrode side;
Forming a drain layer in the semiconductor substrate on the control gate electrode side by performing ion implantation using the second photoresist layer, the floating gate electrode, the control gate electrode, and the sidewall spacer as a mask. A method for manufacturing a nonvolatile semiconductor memory device, comprising: Forming an oxide film covering the source layer such that an end of the oxide film covers the control gate electrode;
Forming a silicide-forming metal film on the semiconductor substrate on which the oxide film is formed;
Forming a silicide layer on the drain layer and the control gate electrode by reacting the silicide forming metal film with silicon. The method of claim 6, further comprising: Production method.

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