JP2004348857A - Semiconductor device - Google Patents

Abstract

A semiconductor device capable of simultaneously writing data to or reading data from a plurality of memory cells is provided.
Kind Code: A1 Two-port memory cells 2 to 5, bit lines BLa and BLb connected to two ports of memory cells 2 to 5, and a word line WLa1 connected to two ports of memory cells 2 to 5. To WLb4, switch circuits 11 to 23 disposed between the connection points of the memory cells 2 to 5 and the bit lines BLa and BLb, and control lines CLa1 to CLb3 connected to the control inputs of the switch circuits 11 to 23. , Control line driving circuits 31 to 36 for supplying signals to the control lines CLa1 to CLb3, word line driving circuits 41 to 48 for supplying signals to the word lines WLa1 to WLb4, and both ends of the bit lines BLa and BLb. Data read / write buffers 6-9.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device capable of simultaneously writing data to or reading data from a plurality of memory cells.
[0002]
[Prior art]
A conventional multiport memory will be described with reference to FIG. FIG. 4 shows four memory cells 61 to 64 among a plurality of memory cells arranged in a matrix. Each of the memory cells 61 to 64 has four ports, and these ports are connected to bit lines BLc to BLf and word lines WLc1 to WLc4, WLd1 to WLd4, WLe1 to WLe4, and WLf1 to WLf4. .
Data read / write buffers 65 to 68 are connected to the lower ends of the bit lines BLc to BLf in FIG. 4, respectively, and the word lines WLc1 to WLc4, WLd1 to WLd4, WLe1 to WLe4, WLf1 to WLf4 Word line drive circuits 69 to 84 are connected to the right ends in FIG.
[0003]
In FIG. 4, word line driving circuits 69 to 84 supply signals to word lines WLc1 to WLc4, WLd1 to WLd4, WLe1 to WLe4, WLf1 to WLf4, and data read / write buffers 65 to 68 connect to bit lines BLc to BLf. By supplying a data signal, writing of data to the memory cells 61 to 64 or reading of data from the memory cells 61 to 64 can be performed at the same time.
[0004]
However, in the conventional multiport memory shown in FIG. 4, each memory cell has four ports in order to simultaneously write data to memory cells 61 to 64 or read data from memory cells 61 to 64. And the number of elements in the memory cells 61 to 64 has increased. In addition, four (the same number as the number of ports of the memory cells 61 to 64) bit lines are required, and 16 (the product of the number of the ports of the memory cells 61 to 64 and the number of the memory cells 61 to 64) word lines are required. Was needed. Therefore, the chip area has become large.
[0005]
By the way, by reducing the number of bit lines per column or per port, the wiring space is reduced, the size of the entire memory is reduced, and a memory that realizes a high-density single-port memory or a multi-port memory is realized. A circuit is known (for example, see Patent Document 1).
However, the memory circuit disclosed in Patent Literature 1 includes a memory cell array including a plurality of memory cells each arranged in a matrix having at least one read port, and a memory cell including a plurality of memory cells. A word line commonly connected to the memory cells in the same row; and a bit line commonly connected to n (n ≧ 2) columns of memory cells in the same row among the plurality of memory cells. The current drive capability of the access transistors of the n memory cells that are present and share the bit line is 1: 2:. ^n-1 And requires a sense amplifier that can identify a plurality of levels of current values.
[0006]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 9-299799 (page 1, FIG. 1)
[0007]
[Problems to be solved by the invention]
In view of the above, the present invention reduces the number of elements in a memory cell and the number of word lines and bit lines, and eliminates the need for a sense amplifier capable of identifying a plurality of levels of current values. It is an object of the present invention to provide a semiconductor device capable of simultaneously writing data into or reading data from a memory cell.
[0008]
[Means for Solving the Problems]
In order to solve the above problem, a semiconductor device according to the present invention includes first to Jth (J is an integer of 2 or more) memory cells each having first to Ith (I is a natural number) ports. And the first to I-th bit lines connected to the first to I-th ports of the first to J-th memory cells, and the first to I-th ports of the first to J-th memory cells, respectively. (I × J) connected word lines and switch circuits of a first group to a first group, each group including (J−1) switch circuits, wherein a K-th group (K is 1 ), The input / output paths of the (J-1) switch circuits included on the K-th bit line are on the K-th bit line. The first to the first group of switch circuits respectively disposed between the connection points and the control inputs of the first to the first group of switch circuits are connected to the control inputs. A first group to a first group of control lines connected to each other, a first group to a first group of word line driving circuits for respectively supplying signals to (I × J) word lines at a predetermined timing, The first to Ith control line driving circuits for supplying signals to the first to Ith control lines at predetermined timings, respectively, are connected to both ends of the first to Ith bit lines, respectively. A first group and a second group of read / write circuits, each group supplying a data signal to a first to an I-th bit line at a predetermined timing; A first group and a second group of read / write circuits including I read / write circuits for reading data signals supplied to the first to I-th bit lines at a predetermined timing.
[0009]
In this semiconductor device, the word line drive circuits of the first to I-th groups are configured to output the first signal or the first to J-th memory cells instructing the sequential writing of data to the first to J-th memory cells. In response to the second signal instructing the sequential reading of the data, the signals are sequentially supplied to the (I × J) word lines, and the first group or the second group of read / write circuits A selection circuit that selects a data signal to be read and output from a memory cell according to a control signal and outputs the selected data signal to an external device, and outputs data input from the outside to first to I-th data according to a first or second signal. A signal instructing supply to the bit line or reading of data supplied to the first to I-th bit lines by the first to J-th memory cells is output to the first and second groups of read / write circuits. And a first group and a second group of read / write To transfer the data supplied to the first to I-th bit lines to the first to J-th memory cells, or to transfer the data output from the first to J-th memory cells to the first and second groups. A signal instructing transmission to the read / write circuit is output to the first to I-th group of switch circuits, and the first or second group of read / write circuits reads and outputs from the first to J-th memory cells. And a control circuit that outputs a control signal instructing selection of a data signal to be performed to the selection circuit.
[0010]
According to the above configuration, the number of elements in a memory cell and the number of word lines and bit lines can be reduced, and data to a plurality of memory cells can be stored without the need for a sense amplifier capable of identifying a plurality of levels of current values. Writing or data reading can be performed simultaneously.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the same components are denoted by the same reference numerals.
FIG. 1 is a diagram illustrating a part of a semiconductor device according to a first embodiment of the present invention. The semiconductor device 1 includes a plurality of memory cells each having two ports and arranged in a matrix. FIG. 1 shows four memory cells 2 to 5 among a plurality of memory cells.
[0012]
The bit lines BLa are connected to the data input / output terminals of the first ports of the memory cells 2 to 5, and the bit lines BLb are connected to the data input / output terminals of the second ports. The word lines WLa1 to WLa4 are connected to the control input terminals of the first ports of the memory cells 2 to 5, respectively, and the word lines WLb1 to WLb4 are connected to the control input terminals of the second ports, respectively. Have been.
On the bit line BLa, between four connection points between the first ports of the memory cells 2 to 5 and the bit line BLa, input / output paths of three switch circuits 11 to 13 are connected. I have. Similarly, on the bit line BLb, between the four connection points between the second ports of the memory cells 2 to 5 and the bit line BLb, the input / output paths of the three switch circuits 21 to 23 are connected. It is connected.
[0013]
Control lines CLa1 to CLa3 are connected to control inputs of the switch circuits 11 to 13, respectively, and control lines CLb1 to CLb3 are connected to control inputs of the switch circuits 21 to 23, respectively.
Control line driving circuits 31 to 33 for supplying signals for controlling the opening and closing of the switch circuits 11 to 13 to the control lines CLa1 to CLa3 are connected to the right ends of the control lines CLa1 to CLa3 in FIG. The control line driving circuits 31 to supply control signals to control lines CLb1 to CLb3 for controlling the opening and closing of the switch circuits 21 to 23 are provided at right ends of the control lines CLb1 to CLb3 in FIG. 33 are respectively connected.
[0014]
A data read / write buffer 6 for supplying a data signal to the bit line BLa or reading a data signal supplied to the bit line BLa by the memory cells 2 to 5 is connected to an upper end of the bit line BLa in FIG. Have been. Similarly, a data read / write buffer 8 is provided at the lower end of the bit line BLa in FIG. 1, and a data read / write buffer 7 is provided at the upper end of the bit line BLb in FIG. A data read / write buffer 9 is connected to the lower end of the center 1.
[0015]
At the right end of the word lines WLa1 to WLa4 in FIG. 1, writing of data to the first ports of the memory cells 2 to 5 or reading of data from the first ports of the memory cells 2 to 5 is performed. Word line drive circuits 41 to 44 for supplying signals to be controlled to the word lines WLa1 to WLa4 are connected, respectively. Similarly, data writing to the second ports of the memory cells 2 to 5 or data from the second ports of the memory cells 2 to 5 are provided at the right ends of the word lines WLb1 to WLb4 in FIG. Are connected to word line driving circuits 45 to 48 for supplying a signal for controlling the reading of data to word lines WLb1 to WLb4.
[0016]
Next, the operation of the semiconductor device 1 will be described.
First, an operation when data is simultaneously written to the memory cells 2 to 5 will be described. Here, the data output from the data read / write buffer 6 is stored in the memory cell 2, the data output from the data read / write buffer 7 is stored in the memory cell 3, the data output from the data read / write buffer 8 is read into the memory cell 4, and the data read from the memory cell 4 is read. It is assumed that the data output from the write buffer 9 is written into the memory cells 5 respectively.
[0017]
In this case, the control line drive circuit 31 turns off the switch circuit 11, the control line drive circuit 32 turns off the switch circuit 12, and the control line drive circuit 33 turns on the switch circuit 13. . Further, the control line drive circuit 34 turns on the switch circuit 21, the control line drive circuit 35 turns off the switch circuit 22, and the control line drive circuit 36 turns off the switch circuit 23.
Thereby, the bit lines BLa and BLb are electrically cut off in the vertical direction in FIG.
[0018]
Here, the word line driving circuit 41 supplies the word line WLa1, the word line driving circuit 46 supplies the word line WLb2, the word line driving circuit 43 supplies the word line WLa3, and the word line driving circuit 48 supplies the signal to the word line WLb4. At the same time, the data read / write buffer 6 sends a data signal to the bit line BLa, the data read / write buffer 7 sends a data signal to the bit line BLb, the data read / write buffer 8 sends a data signal to the bit line BLa, and the data read / write buffer 9 sends a data signal to the bit line BLb. Supply.
[0019]
At this time, the data signal supplied from the data read / write buffer 6 to the bit line BLa reaches the first port of the memory cell 2, but since the switch circuits 11 and 12 are off, the data signals of the memory cells 3 to 5 It does not reach the first port. Therefore, the data signal supplied from the data read / write buffer 6 to the bit line BLa is written only to the memory cell 2.
[0020]
The data signal supplied to the bit line BLb by the data read / write buffer 7 reaches the second port of the memory cells 2 and 3 because the switch circuit 21 is on, but the data signal supplied to the bit line BLb is off when the switch circuits 22 and 23 are off. Therefore, it does not reach the second ports of the memory cells 4 and 5. The word line driving circuit 46 supplies a signal to the word line WLb2, but the word line driving circuit 45 does not supply a signal to the word line WLb1. Therefore, the data signal supplied from the data read / write buffer 7 to the bit line BLb is written only to the memory cell 3.
[0021]
The data signal supplied from the data read / write buffer 8 to the bit line BLa reaches the first port of the memory cells 4 and 5 because the switch circuit 13 is on, but the data signal supplied to the bit line BLa is off when the switch circuits 11 and 12 are off. Therefore, the first ports of the memory cells 2 and 3 do not reach the first ports. The word line driving circuit 43 supplies a signal to the word line WLa3, but the word line driving circuit 44 does not supply a signal to the word line WLa4. Therefore, the data signal supplied from the data read / write buffer 8 to the bit line BLa is written only to the memory cell 4.
[0022]
The data signal supplied from the data read / write buffer 9 to the bit line BLb reaches the second port of the memory cell 5, but since the switch circuits 22 and 23 are off, the second signal of the memory cells 2 to 4 Does not reach the port. Therefore, the data signal supplied from the data read / write buffer 9 to the bit line BLb is written only to the memory cell 5.
[0023]
Here, the data output from the data read / write buffer 6 is stored in the memory cell 2, the data output from the data read / write buffer 7 is stored in the memory cell 3, the data output from the data read / write buffer 8 is stored in the memory cell 4, The data output from the data read / write buffer 9 is written in the memory cell 5. For example, the data output from the data read / write buffer 5 is written into the memory cell 3, and the data output from the data read / write buffer 6 is written into the memory cell 2. Alternatively, the data output from the data read / write buffer 7 can be written into the memory cell 5, and the data output from the data read / write buffer 8 can be written into the memory cell 4.
[0024]
Next, an operation when data is simultaneously read from the memory cells 2 to 5 will be described. Here, the read / write buffer 6 outputs data output from the memory cell 2, the read / write buffer 7 outputs data output from the memory cell 3, the read / write buffer 8 outputs data output from the memory cell 4, and the memory cell 5 outputs data. It is assumed that the read / write buffer 9 reads the data to be read.
[0025]
In this case, the control line drive circuit 31 turns off the switch circuit 11, the control line drive circuit 32 turns off the switch circuit 12, and the control line drive circuit 33 turns on the switch circuit 13. . Further, the control line drive circuit 34 turns on the switch circuit 21, the control line drive circuit 35 turns off the switch circuit 22, and the control line drive circuit 36 turns off the switch circuit 23.
Thereby, the bit lines BLa and BLb are electrically cut off in the vertical direction in FIG.
[0026]
Here, the word line driving circuit 41 supplies the word line WLa1, the word line driving circuit 46 supplies the word line WLb2, the word line driving circuit 43 supplies the word line WLa3, and the word line driving circuit 48 supplies the signal to the word line WLb4. Then, from the first port of the memory cell 2 to the bit line BLa, from the second port of the memory cell 3 to the bit line BLb, from the first port of the memory cell 4 to the bit line BLa, and Data signals are supplied to the bit lines BLb from the ports.
[0027]
At this time, the data signal supplied from the memory cell 2 to the bit line BLa reaches the data read / write buffer 6 but does not reach the data read / write buffer 8 because the switch circuits 11 and 12 are off. Therefore, the data signal supplied from the memory cell 2 to the bit line BLa is read only to the data read / write buffer 6.
[0028]
The data signal supplied from the memory cell 3 to the bit line BLb reaches the data read / write buffer 7 because the switch circuit 21 is on, but the data signal supplied to the bit line BLb because the switch circuits 22 and 23 are off. 9 is not reached. Therefore, the data signal supplied from the memory cell 3 to the bit line BLb is read only by the data read / write buffer 7.
[0029]
The data signal supplied from the memory cell 4 to the bit line BLa reaches the data read / write buffer 8 because the switch circuit 13 is on, but the data signal supplied to the bit line BLa because the switch circuits 11 and 12 are off. Do not reach 6. Therefore, the data signal supplied from the memory cell 4 to the bit line BLa is read only by the data read / write buffer 8.
[0030]
The data signal supplied from the memory cell 5 to the bit line BLb reaches the data read / write buffer 9 but does not reach the data read / write buffer 7 because the switch circuits 22 and 23 are off. Therefore, the data signal supplied from the memory cell 5 to the bit line BLb is read only by the data read / write buffer 9.
[0031]
Here, the data read / write buffer 6 outputs data output from the memory cell 2, the data read / write buffer 7 outputs data output from the memory cell 3, and the data read / write buffer 8 outputs data output from the memory cell 4. The data read / write buffer 9 reads data output from the memory cell 5. For example, the data read / write buffer 7 reads data output from the memory cell 2 and reads / writes data output from the memory cell 3. The data read from the memory cell 4 can be read by the data read / write buffer 9, and the data read from the memory cell 5 can be read from the data read / write buffer 8 by the buffer 6.
[0032]
As described above, according to the semiconductor device 1, data writing or data reading to the memory cells 2 to 5 can be simultaneously performed using the two-port memory cells 2 to 5 and the two bit lines BLa and BLb. it can.
[0033]
Next, a second embodiment of the present invention will be described. FIG. 2 is a diagram showing a first-in first-out (FIFO) memory according to a second embodiment of the present invention. As shown in FIG. 2, the FIFO memory 50 includes a memory cell array 51, a word line drive circuit group 52, a control line drive circuit group 53, a first data read / write buffer group 54, and a second data read / write buffer group. 55, a FIFO control circuit 56, and a selector 57.
[0034]
The memory cell array 51 has 2048 memory cells each having one port and arranged in a matrix of 256 rows × 8 columns, and can store 256 8-bit width data. It is. FIG. 2 shows eight memory cells MC11, MC12, MC21,... Of the 2048 memory cells.
The bit line BL1 is connected to the data input / output terminals of the memory cells MC11, MC21,..., And the bit line BL2 is connected to the data input / output terminals of the memory cells MC12, MC22,. The word line WL1 is connected to the control input terminals of the memory cells MC11, MC12,..., And the word line WL2 is connected to the control input terminals of the memory cells MC21, MC22,. The word line WL3 is connected to the control input terminals of MC31, MC32,..., And the word line WL4 is connected to the control input terminals of the memory cells MC41, MC42,.
[0035]
The upper ends of the bit lines BL1, BL2,... In FIG. 2 are supplied with data to the bit lines BL1, BL2,... Or supplied to the bit lines BL1, BL2,. A first data read / write buffer group 54 including eight data read / write buffers for reading the read data is connected. Similarly, a second data read / write buffer group 55 including eight data read / write buffers is connected to lower ends of the bit lines BL1, BL2,... In FIG.
Signals for controlling writing of data to the memory cells MC11, MC12,... Or reading of data from the memory cells MC11, MC12,... Are provided at the left ends of the word lines WL1, WL2,. A word line drive circuit group 52 including 256 word line drive circuits for supplying word lines WL1, WL2,... Is connected.
[0036]
On the bit line BL1, between the ports of the memory cells MC11, MC21,... And the 256 connection points with the bit line BL1, 255 input / output paths of the switch circuits SW11, SW21,. ing. Similarly, on the bit line BL2, between the 256 connection points between the ports of the memory cells MC12, MC22,... And the bit line BL2, the input / output paths of the 255 switch circuits SW12, SW22,. Is connected.
[0037]
A control line CL1 is connected to control inputs of the switch circuits SW11, SW12,..., And a control line CL2 is connected to control inputs of the switch circuits SW21, SW22,. Are connected to a control line CL3, and control inputs of the switch circuits SW41, SW42,... Are connected to a control line CL4.
At the right end of the control lines CL1, CL2,..., 255 controls for supplying signals for controlling the opening and closing of the switch circuits SW11, SW12,. A control line drive circuit group 53 including a line drive circuit is connected.
[0038]
A write strobe signal or a read strobe signal is externally supplied to the word line drive circuit group 52, and the word line drive circuit group 52 outputs a signal to the word lines WL1, WL2,... In response to the write strobe signal or the read strobe signal. Supply.
The write strobe signal and the read strobe signal are also supplied to a FIFO control circuit 56. The FIFO control circuit 56 controls the control line drive circuit group 53 and the first data read / write buffer group 54 according to the write strobe signal or the read strobe signal. , The second data read / write buffer group 55, and the selector 57.
[0039]
FIG. 3 is a timing chart showing the operation timing of the FIFO memory 50.
As shown in FIG. ₀ , When a write strobe signal is externally input to the FIFO memory 50, the word line drive circuit group 52 supplies a signal to the word line WL1. On the other hand, the FIFO control circuit 56 instructs the control line drive circuit group 53 to turn on all the switch circuits, instructs the first data read / write buffer group 54 not to operate, and inputs from the outside. Instruct the second data read / write buffer group 55 to supply data to the bit lines BL1, BL2,..., And instruct the selector 57 not to operate. The data supplied to the bit lines BL1, BL2,... Are written to the memory cells MC11, MC12,... In the first row in the memory cell array 51 because the signal is supplied to the word line WL1.
[0040]
After that, the word line drive circuit group 52 sequentially supplies signals to the word lines WL2, WL3,..., And the second data read / write buffer group 55 transmits data sequentially input from the outside to the bit lines BL1, BL2,. Supply. As a result, data input from the outside is sequentially stored in the memory cell array 51.
[0041]
Next, at time t ₁ When a read strobe signal is externally input to the FIFO memory 50, the word line drive circuit group 52 supplies a signal to the word lines WL57 and WL1. On the other hand, the FIFO control circuit 56 instructs the control line drive circuit group 53 to supply a signal for turning off the switch circuits SW11, SW12,... To the control line CL1, and outputs the signals from the bit lines BL1, BL2,. The first data read / write buffer group 54 is instructed to read data and supply the data to the selector 57, and the second data read / write buffer group is configured to supply externally input data to the bit lines BL1, BL2,. 55, and instruct the selector 57 to output the data supplied from the first data read / write buffer group 54 to the outside.
[0042]
The data supplied to the bit lines BL1, BL2,... By the second data read / write buffer group 55 reaches the memory cells in the second to 256th rows in the memory cell array 51, but the switch circuits SW11, Since the switches SW12,... Are in the off state, they do not reach the memory cells MC11, MC12,. Therefore, the data supplied to the bit lines BL1, BL2,... By the second data read / write buffer group 55 is written to the memory cells in the 57th row in the memory cell array 51.
[0043]
On the other hand, the memory cells MC11, MC12,... In the first row supply stored data to the bit lines BL1, BL2,. The data supplied to the bit lines BL1, BL2,... By the memory cells MC11, MC12,... In the first row reach the first data read / write buffer group 54, but the switch circuits SW11, SW12,. Since it is in the state, it does not reach the second data read / write buffer group 55. Therefore, the data supplied to the bit lines BL1, BL2,... By the memory cells MC11, MC12,... In the first row are read by the first data read / write buffer group 54 and output to the outside by the selector 57.
[0044]
After that, the word line drive circuit group 52 sequentially supplies signals to the word lines WL58 and WL2, WL59 and WL3,..., And the control line drive circuit group 53 sends a signal for turning off the switch circuit to the control line CL2. , CL3,..., The first data read / write buffer group 54 sequentially reads data from the bit lines BL1, BL2,. The sequentially input data is supplied to bit lines BL1, BL2,. As a result, data input from the outside is sequentially stored in the memory cell array 51, and data stored in the memory cell array 51 is sequentially output.
[0045]
Next, at time t ₂ When the storage of the data in the memory cell of the 256th row and the reading of the data stored in the memory cell of the 200th row in the memory cell array 51 are completed, the FIFO control circuit 56 switches the switch circuits SW11 and SW12. ,... Are supplied to the control line CL1 to instruct the control line drive circuit group 53 to supply input data input from the outside to the bit lines BL1, BL2,. , And instruct the second data read / write buffer group 55 to read data from the bit lines BL1, BL2,... And supply the data to the selector 57, and the second data read / write buffer group 55. The selector 57 is instructed to output the data supplied from the external device to the outside.
[0046]
The data supplied to the bit lines BL1, BL2,... By the first data read / write buffer group 54 reaches the memory cells in the first row in the memory cell array 51, but the switch circuits SW11, SW12,. In this state, the memory cells in the second to 256th rows and the second data read / write buffer group 55 do not reach. Therefore, the data supplied to the bit lines BL1, BL2,... By the first data read / write buffer group 54 is written to the memory cells in the first row in the memory cell array 51.
[0047]
On the other hand, the memory cells in the 201st row supply stored data to bit lines BL1, BL2,... In response to a signal supplied to word line WL201. The data supplied to the bit lines BL1, BL2,... By the memory cells in the 201st row reach the second data read / write buffer group 55, but the switch circuits SW11, SW12,. Therefore, it does not reach the first data read / write buffer group 54. Therefore, the data supplied to the bit lines BL1, BL2,... By the memory cells in the 201st row are read by the second data read / write buffer group 55 and output to the outside by the selector 57.
[0048]
After that, the word line drive circuit group 52 sequentially supplies signals to the word lines WL2 and WL202, WL3 and WL203,..., And the control line drive circuit group 53 sends a signal for turning off the switch circuit to the control line CL2. , CL3,..., The first data read / write buffer group 54 supplies data sequentially input from the outside to the bit lines BL1, BL2,. Data is read from BL1, BL2,... And sequentially supplied to the selector 57. As a result, data input from the outside is sequentially stored in the memory cell array 51, and data stored in the memory cell array 51 is sequentially output.
[0049]
Next, at time t ₃ When the reading of the data stored in the memory cell in the 256th row and the storing of the data in the memory cell in the 56th row in the memory cell array 51 are completed, the FIFO control circuit 56 ,... Are supplied to the control line CL1 to instruct the control line drive circuit group 53 to read data from the bit lines BL1, BL2,. , And instruct the second data read / write buffer group 55 to supply externally input data to the bit lines BL1, BL2,... The selector 57 is instructed to output the data supplied from the external device to the outside.
[0050]
The data supplied to the bit lines BL1, BL2,... By the second data read / write buffer group 55 reaches the memory cells in the 57th row in the memory cell array 51, but the switch circuits SW11, SW12,. Since the state is in the state, it does not reach the memory cells in the first row and the first data read / write buffer group 54. Therefore, the data supplied to the bit lines BL1, BL2,... By the second data read / write buffer group 55 is written to the memory cells in the 57th row in the memory cell array 51.
[0051]
On the other hand, the memory cells in the first row supply stored data to the bit lines BL1, BL2,... In response to the signal supplied to the word line WL1. The data supplied to the bit lines BL1, BL2,... By the memory cells in the first row reach the first data read / write buffer group 54, but the switch circuits SW11, SW12,. Therefore, it does not reach the second data read / write buffer group 55. Therefore, the data supplied to the bit lines BL1, BL2,... By the memory cells in the first row are read by the first data read / write buffer group 54 and output to the outside by the selector 57.
[0052]
After that, the word line drive circuit group 52 sequentially supplies signals to the word lines WL58 and WL2, WL59 and WL3,..., And the control line drive circuit group 53 sends a signal for turning off the switch circuit to the control line CL2. , CL3,..., The first data read / write buffer group 54 sequentially reads data from the bit lines BL1, BL2,. The sequentially input data is supplied to bit lines BL1, BL2,. As a result, data input from the outside is sequentially stored in the memory cell array 51, and data stored in the memory cell array 51 is sequentially output.
[0053]
As described above, according to the FIFO memory 50, data can be written to or read from the memory cells at the same time using the memory cells of one port.
[Brief description of the drawings]
FIG. 1 is a view showing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a FIFO memory according to a second embodiment of the present invention.
FIG. 3 is a timing chart of the FIFO memory of FIG. 2;
FIG. 4 is a diagram showing a conventional multiport memory.
[Explanation of symbols]
1 semiconductor device, 2-5, 61-64, MC11, MC12,... Memory cell, 6-9, 65-68 data read / write buffer, 11-13, 21-23, SW11, SW12,. 36 control line drive circuits, 41 to 48, 69 to 84 word line drive circuits, BLa to BLf, BL1, BL2,... Bit lines, WLa1 to WLa4, WLb1 to WLb4, WLc1 to WLc4, WLd1 to WLd4, WLe1 to WLe4 WLf1 to WLf4, WL1, WL2,... Word lines, CLa1 to CLa3, CLb1 to CLb3, CL1, CL2,... Control lines, 50 FIFO memories, 51 memory cell arrays, 52 word line drive circuit groups, 53 control line drive circuit groups, 54 first data read / write buffer group, 55 second data De write buffer group, 56 FIFO control circuit, 57 a selector,

Claims (2)

First to J-th (J is an integer of 2 or more) memory cells each having first to I-th (I is a natural number) ports;
First to I-th bit lines respectively connected to first to I-th ports of the first to J-th memory cells;
(I × J) word lines connected to the first to I-th ports of the first to J-th memory cells, respectively;
Each group is a first group to a first group of switch circuits including (J-1) switch circuits, and each group includes (J-1) switch circuits included in a K group (K is an integer of 1 to I). Wherein the input / output path of the switch circuit is on the K-th bit line and the first circuit is disposed between J connection points between the first to J-th memory cells and the K-th bit line. Group to group I switch circuits;
A first group to a first group of control lines respectively connected to control inputs of the first group to the first group of switch circuits;
A first group to a first group of word line driving circuits for respectively supplying signals to the (I × J) word lines at a predetermined timing;
A first group to a first group of control line driving circuits for supplying signals to the first group to the first group of control lines at a predetermined timing, respectively;
A first group and a second group of read / write circuits respectively connected to both ends of the first to I-th bit lines, wherein each group applies a data signal to the first to I-th bit lines. Or at least one read / write circuit that reads the data signals supplied to the first to I-th bit lines at a predetermined timing by any of the first to J-th memory cells. The first group and the second group of read / write circuits;
A semiconductor device comprising: The first group to the I-th group of word line driving circuits are provided with a first signal instructing sequential writing of data to the first to J-th memory cells or data from the first to J-th memory cells. Signals are sequentially supplied to the (I × J) word lines in response to a second signal instructing sequential reading of
A selection circuit that selects a data signal to be read and output from the first to Jth memory cells by the first or second group of read / write circuits according to a control signal, and outputs the data signal to the outside;
In response to the first or second signal, externally input data is supplied to the first to I-th bit lines, or the first to J-th memory cells are used to supply the first to I-th data. A signal instructing to read data supplied to the bit line is output to the first and second groups of read / write circuits, and the first to second groups of read / write circuits are output by the first and second groups of read / write circuits. Transmitting the data supplied to the first to the J-th memory cells or transmitting the data output from the first to the J-th memory cells to the first and second groups of read / write circuits. A signal instructing transmission is output to the first to I-th group of switch circuits, and the first or second group of read / write circuits reads and outputs from the first to J-th memory cells. Selecting a data signal A control circuit for outputting the control signal instructing the selection circuit,
The semiconductor device according to claim 1, further comprising:

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