JP2004347760A - Driver for field emission display panel and field emission display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driver for field emission display panel and a field emission display device capable of accurately correcting the irregularity of brightness between pixels of a FED panel without reducing the number of gradation of image data by using an inexpensive circuit constitution. <P>SOLUTION: A cathode driving circuit 6 modulates the pulse width on the basis of a timing signal V1 and an image data signal VB, changes the driving voltage at every pixel on the basis of voltage data V5 at every pixel read from a frame memory 5 in accordance with the timing signal V1 and, thereby, produces the data pulse V6 obtained as the driving signal of column electrode of the FED panel 2. Therein, ROM can be used as a frame memory 5. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
According to the present invention, a field emission display (hereinafter, referred to as FED) panel including a plurality of electron-emitting devices arranged in a matrix and a light-emitting surface having a phosphor formed on an anode electrode is line-scanned. The present invention relates to a driving technique when driving and driving by a pulse width modulation method.
[0002]
In the present invention, a display provided with an FED panel and its driving circuit is referred to as an “FED device”.
[0003]
[Prior art]
The drive circuit in the conventional FED device includes a cathode drive circuit, a gate drive circuit, and a pulse signal converter, and uses an ammeter for measuring an anode current to correct the luminance variation, and a measurement based on the measured value of the ammeter. And a frame memory for storing the obtained anode current value of each pixel. Then, the pulse signal converter corrects the output to the cathode drive circuit based on the current value stored in the frame memory (for example, see Patent Document 1).
[0004]
[Patent Document 1]
JP-A-2001-209352 (pages 3 to 5, FIG. 1)
[0005]
[Problems to be solved by the invention]
The drive circuit of the conventional FED device corrects the output to the cathode drive circuit based on the anode current value when correcting the luminance variation of each pixel, and thus requires a pulse signal converter. In such a case, there is a problem that, depending on the type of correction, there is a trade-off between the cost of the correction circuit and the correction accuracy, or the number of gradations of the video signal decreases.
[0006]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned concerns, and its main object is to reduce the number of gradations of a video signal and to provide an inexpensive circuit configuration for an FED panel. It is an object of the present invention to provide a driving technique capable of correcting luminance variation between pixels with high accuracy. Further, a secondary object of the present invention is to provide a driving technique capable of acquiring correction data necessary for correcting luminance variation at high speed.
[0007]
[Means for Solving the Problems]
An FED panel driving device according to the present invention includes a frame memory in which a driving voltage value of each pixel is set, and a driving voltage of a cathode driving waveform pulse width modulated by video data for each pixel based on the setting value. And a cathode drive circuit for changing the value.
[0008]
Hereinafter, the present invention will be specifically described with reference to the drawings illustrating the embodiments.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
FIG. 1 is a block diagram schematically showing a configuration of the FED device according to the present embodiment. In FIG. 1, the FED device is roughly divided into an FED panel 2 and a driving device (or driving circuit) thereof.
[0010]
Among them, the FED panel 2 includes (1) a rear panel and (2) a front panel opposed to each other. One back panel (1) of the FED panel 2 includes a plurality of electron-emitting devices arranged in a matrix, a plurality of gate electrodes as row electrodes, and a plurality of cathodes as column electrodes three-dimensionally intersecting each gate electrode. An electrode is provided on the glass substrate. On the other hand, the front panel of (2) has an anode electrode formed on the rear panel side surface of the glass substrate, and R (red), G (green), and B formed on the anode electrode for each pixel. (Blue) phosphor, and the surface of the glass substrate facing the rear panel side surface forms a light emitting surface.
[0011]
On the other hand, the FED panel drive device includes a control circuit 1, an anode power supply 3, a gate drive circuit 4, a frame memory 5, and a cathode drive circuit 6. Among these components, the control circuit 1 arranged on the side of the external input terminal processes input video data VB and video signals such as a synchronization signal VS (consisting of a vertical synchronization signal and a horizontal synchronization signal). More specifically, the circuit 1 generates a timing signal based on the synchronization signal VS (the start of the timing signal is generated in synchronization with the vertical synchronization signal, and the subsequent pulses are generated in synchronization with the horizontal synchronization signal). Generate and output V1. The anode power supply 3 is a power supply for applying a high voltage to the anode electrode of the FED panel 2. Further, the gate drive circuit 4 drives the FED panel 2 according to the timing signal V1 output from the control circuit 1 (applies a scan pulse V4 to each gate electrode or each row electrode).
[0012]
On the other hand, the frame memory 5 and the cathode drive circuit 6 are the core parts which are the characteristic parts of the present drive device, and among them, the frame memory 5 stores the optimal drive voltage value data of each pixel set in advance. This is a storage device for storing, and receives a timing signal V1 output from the control circuit 1 as a read address signal. Further, the cathode drive circuit 6 outputs the timing signal V1 and the video data signal VB output from the control circuit 1, and the voltage value data (cathode drive voltage) for each pixel read from the frame memory 5 in accordance with the timing of the timing signal V1. 3.) V5 is received as an input signal, and the FED panel 2 is driven based on these input signals V1, VB, V5 (data pulse V6 is applied to each cathode electrode or each column electrode). More specifically, the cathode drive circuit 6 supplies, for each pixel, a drive voltage (low-level VL described later) of a cathode drive waveform (data pulse) V6 pulse-width-modulated by the video data VB corresponding to the pixel. The value is changed based on the voltage value data V5 corresponding to the pixel.
[0013]
Next, the operation of the driving device of FIG. 1 will be described. First, the control circuit 1 generates a timing signal V1 based on the input synchronization signal VS so that all of the gate drive circuit 4, the frame memory 5, and the cathode drive circuit 6 operate in synchronization with each other. I do.
[0014]
In response to the input of the timing signal V1, the gate drive circuit 4 generates a scan pulse for driving a row electrode of the FED panel 2 based on the timing signal V1.
[0015]
Further, the frame memory 5 sequentially stores the voltage value data (cathode drive voltage) V5 of each pixel belonging to the scan line corresponding to a certain row electrode of the FED panel 2 from its address area according to the input timing of the timing signal V1. Output to
[0016]
On the other hand, the cathode drive circuit 6 generates a data pulse (having a predetermined pulse width and a predetermined drive voltage value before modulation) for driving each column electrode of the FED panel 2 for each pixel. On the other hand, (1) the pulse width modulation drive is performed based on the timing signal V1 and the video data signal VB of the pixel corresponding to the column electrode, and (2) the voltage value data V5 of the pixel read from the frame memory 5 is applied. The driving voltage is changed based on this, and the resulting signal is generated as a data pulse V6.
[0017]
Here, the respective drive waveforms of the scan pulse V4 applied to each row electrode and the data pulse V6 applied to each column electrode are shown in the timing chart of FIG. As shown in FIG. 2, a scan pulse having a constant width and a constant voltage (high level VG) is sequentially applied to all the row electrodes, and the image data of the corresponding pixel is applied to each column electrode. A data pulse whose pulse width is modulated by VB (variable in pulse width ΔT) and whose voltage (low level VL: positive or negative potential) is varied by voltage value data V6 of the corresponding pixel is applied. In this case, as the pulse width ΔT of the data pulse applied to the column electrode on the low level VL side increases, and as the voltage value of the low level VL decreases (in other words, as the potential difference VG−VL increases, the potential difference VG−VL increases). 2), the corresponding pixel defined by the intersection of the column electrode and the corresponding row electrode becomes brighter.
[0018]
Next, the voltage value data (cathode drive voltage) V5 set in the frame memory 5 will be described. Therefore, the relationship between the driving voltage (= gate voltage VG−cathode voltage VL) and luminance is shown by the curve in FIG. As shown in FIG. 3, generally, the luminance increases exponentially with respect to the drive voltage. Here, that the luminance of each pixel varies means that the curve shown in FIG. 3 varies in each pixel as shown in FIG. However, even if the driving voltage-luminance characteristics of each pixel vary, each pixel always has a driving voltage value exhibiting the same luminance value. For example, as for the pixels A and B illustrated in FIG. 4, if the pixels A and B are driven by the driving voltages VA and VB, the luminances of the two pixels A and B can be set to the same value. . As described above, the value of the cathode drive voltage VL such that the brightness of each pixel becomes the same value is set in the frame memory 5 for each pixel.
[0019]
Moreover, in this embodiment, a low-cost ROM (Read Only Memory) can be used for the frame memory 5. That is, in general, the price of a RAM having a function of continuously storing data even when the power of the apparatus is turned off is higher than that of a ROM. Therefore, in the present embodiment, data of the cathode drive voltage (VL) for correcting the luminance variation of each pixel of the FED panel 2 is previously written in the ROM, and is used as the frame memory 5.
[0020]
Note that, in the case of the present embodiment, it is not possible to correct luminance variation due to aging. However, in the case where the FED device according to the present embodiment is used as a display for displaying a moving image such as a TV, each pixel is uniformly deteriorated, so that it is not particularly necessary to correct the luminance variation with the lapse of time.
[0021]
As described above, according to the present embodiment, the data of the drive voltage value for each pixel is set in the frame memory 5 in advance so that the luminance of each pixel in one frame is the same level. The data pulse V6 is generated by varying the cathode drive voltage on the cathode drive circuit 6 side according to the set data. For this reason, since the video data VB is only used for pulse width modulation of the data pulse V6, there is no occurrence that the number of gradations of the video data VB is reduced at the time of luminance correction, and high accuracy is achieved. The luminance variation of each pixel of the FED panel 2 can be corrected.
[0022]
In addition, in the present embodiment, when a ROM is used as the frame memory 5, there is an advantage that a circuit configuration for correcting luminance variation can be realized at low cost.
[0023]
(Embodiment 2)
A main object of the present embodiment is to provide an FED panel drive device for obtaining cathode drive voltage value data for each pixel to be set in frame memory 5 according to the first embodiment. Therefore, the driving device according to the present embodiment is used in a stage before manufacturing the FED device according to the first embodiment. Hereinafter, the features of the present embodiment will be described with reference to the drawings.
[0024]
FIG. 5 is a block diagram schematically showing a configuration of the FED device according to the present embodiment. In FIG. 5, the same circuit components as those in FIG. 1 have the same reference numerals. Therefore, as for the description of those components, the corresponding description in Embodiment 1 is cited.
[0025]
As is clear from the comparison between FIG. 1 and FIG. 5, the characteristic circuit components of this device are a controller (a circuit exhibiting a function as a CPU) 7, a resistance element 8 forming a circuit for measuring the anode current IA, and a frame. The recording device 9 sequentially stores the cathode drive voltage value data for each pixel to be set in the memory 5. In particular, the core here lies in the operation or function of the controller 7.
[0026]
In FIG. 5, a resistor 8 is inserted between the negative side of the anode power supply 3 and GND (ground terminal) in order to measure the anode current IA, and the controller 7 controls each pixel of the FED panel 2 sequentially. The gate drive voltage and the cathode drive voltage generated by the gate drive circuit 4 and the cathode drive circuit 6 are controlled so as to turn on, and the cathode drive voltage is varied based on the measured value of the anode current IA. The recording device 9 is a storage device that records data transmitted from the controller 7 (cathode drive voltage value data for each pixel that can make the luminance of each pixel the same).
[0027]
Next, a point of view for obtaining cathode drive voltage value data for each pixel will be described, and then a schematic operation of the present device will be described.
[0028]
FIG. 6 shows the relationship between the anode current and the luminance for describing the point of interest. As shown in the drawing, there is a proportional relationship between the anode current and the luminance when one pixel is turned on. Therefore, the fact that the luminance of each pixel varies means that the anode current value varies. Therefore, if each pixel is driven with a drive voltage having the same anode current value, it is possible to correct luminance variations with high accuracy. For example, as illustrated in FIG. 6, when the luminance cd1 of a certain pixel is smaller than the target luminance cd0, the anode current IA1 flowing when the pixel is turned on is reduced to the target anode current corresponding to the target luminance cd0. The drive voltage applied to the pixel may be increased until the value matches the value IA0. That is, the cathode drive voltage VL illustrated in FIG. 2 may be reset to a lower level. Conversely, when the luminance cd2 of a certain pixel is higher than the target luminance cd0, the anode current IA2 flowing when the pixel is turned on is matched with the target anode current value IA0 corresponding to the target luminance cd0. The driving voltage applied to the pixel may be reduced. That is, the cathode drive voltage VL illustrated in FIG. 2 may be reset to a higher level.
[0029]
Based on such a viewpoint, the data acquisition operation executed in the present apparatus is as follows.
[0030]
First, in response to the first and second control signals V71 and V72 from the controller 7, the gate drive circuit 4 and the cathode drive circuit 6 respectively connect one row electrode corresponding to one pixel in the FED panel 2 to one row electrode. A gate drive voltage VG and a cathode drive voltage VL having a drive waveform such that only one pixel is turned on are generated and applied to the column electrodes (three column electrodes for R, G, and B) (drive voltage). = Gate drive voltage VG-cathode drive voltage VL). In this embodiment, the pulse width modulation by the video data is not performed.
[0031]
Then, the controller 7 holds the level of the anode current IA flowing during the period in which the one pixel is lit, with the measurement data of the voltage drop value of the resistor 8 inserted on the minus side of the anode power supply 3 and already stored internally. It is calculated on the basis of the resistance value data of the resistor 8 which is set.
[0032]
Next, the controller 7 compares the calculated anode current value with the reference set value data of the anode current held therein, and as a result, (A) when both match, the cathode drive voltage at that time is determined. VL is stored in the recording device 9 as an optimum value. On the other hand, (B) when there is a difference between the two, the second control signal is again applied so that the anode current value measured by the resistor 8 matches the reference set value. V72 is output to vary the cathode drive voltage VL. The controller 7 repeats the above-described series of operations for the one pixel until the two values match each other, and finally sets the cathode drive voltage when the anode current value matches the reference set value (hereinafter, this voltage is referred to as the cathode drive voltage). The value of VL (referred to as an optimum drive voltage) is transmitted to the recording device 9 as data to be acquired.
[0033]
Then, the controller 7 performs such an operation for all the pixels in the FED panel 2 to obtain data of the optimum cathode drive voltage VL for each pixel, and stores the data in the recording device 9. Can be stored.
[0034]
As described above, by determining the drive voltage when the anode current flowing when each pixel is turned on has the same value (= reference set value), it is possible to accurately correct the luminance variation. The optimum cathode drive voltage data to be set in the memory 5 can be obtained.
[0035]
Hereinafter, based on the above-described operation outline, a procedure when the device in FIG. 5 (mainly, the controller 7) obtains the optimum cathode drive voltage VL for all pixels will be described in detail with reference to the flowchart in FIG.
[0036]
First, in step {circle around (1)}, the controller 7 drives an arbitrary pixel with a specific drive voltage (hereinafter, this voltage is referred to as an “initial drive voltage”) according to a command of the second control signal V72. I do. Note that the applied voltage VG of the row electrode controlled by the first control signal V71 is always a fixed value.
[0037]
In the next step {circle around (2)}, the controller 7 measures the value of the anode current IA flowing when the one pixel is turned on, based on the voltage value across the resistor 8.
[0038]
In the next step (3), the controller 7 compares the anode current IA with a reference set value. At this time, if there is a difference between the two values, the controller 7 issues a command of the second control signal V72 so that the anode current IA matches the reference set value, and the cathode drive at the initial drive voltage Vary the voltage. The data of the cathode drive voltage value VL after the change is temporarily held in a data storage unit (for example, a register) in the controller 7.
[0039]
Thereafter, the controller 7 repeats steps (2) to (4), and in step (5), the cathode drive voltage (optimal drive voltage) when the measured / calculated anode current value IA matches the reference set value. The VL data is transmitted from the data storage unit in the controller 7 to the recording device 9, and the data is recorded in the recording device 9.
[0040]
Thereafter, the controller 7 proceeds to steps (6) and (7) and repeats the above steps (1) to (5) for each of the remaining pixels, thereby obtaining the optimum cathode drive voltage VL data for all the pixels. Is recorded in the recording device 9.
[0041]
Here, the order of lighting each pixel is not particularly defined. For example, each pixel may be turned on sequentially in the row direction or the column direction, or each pixel may be turned on randomly.
[0042]
In addition, when the processing time of the comparison / variable steps (3) and (4) becomes long and there is a fear that the phosphor is burned, the lit pixels are turned off once, and then the values are obtained in step (4). The driving may be performed again with the changed driving voltage.
[0043]
As a method of varying the drive voltage when there is a difference between the reference set value and the measured value, the drive voltage may be varied step by step with the minimum resolution of the drive voltage, or the difference is relatively large. In some cases, the drive voltage may be largely varied by predictive control.
[0044]
As a method of determining whether or not the reference set value and the measured value match in step (3), if the measured value is within a predetermined range, the controller 7 regards that both values match. You may do.
[0045]
The data sent to the recording device 9 is finally written in the ROM used in the frame memory 5 according to the first embodiment. In this case, the recording device 9 itself may be a ROM, or data in the recording device 9 may be written to the ROM through another recording medium.
[0046]
Further, generally, the above operation for finding the optimum drive voltage is performed after the initial aging of the FED panel 2 is completed and the characteristics of each pixel have settled down to some extent.
[0047]
As described above, by lighting an arbitrary pixel one by one, it is possible to accurately obtain optimum cathode drive voltage VL data for correcting luminance variation for all pixels.
[0048]
<Modification 1 of Embodiment 2>
In the second embodiment, when obtaining the optimum cathode drive voltage, the controller 7 sets the initial drive voltage of each pixel for each pixel.
[0049]
However, the apparatus shown in FIG. 5 is not limited to such an initial drive voltage setting method. Instead, for example, the optimal drive voltage value data may be used for other FED panels for which optimum cathode drive voltage value data has already been acquired. The average value of the cathode drive voltage value data may be used as the initial cathode drive voltage in the present FED panel to be measured. Alternatively, the drive voltage set as the design target may be used as the initial cathode drive voltage.
[0050]
By performing such a modification of the initial drive voltage setting method (the point at which the initial drive voltage of each pixel is set to a value common to all pixels), the reference set value and the measured value match faster, Optimal cathode drive voltage value data can be obtained in a short time.
[0051]
As described above, according to the present modification, by driving and lighting each pixel from the same initial drive voltage, it is possible to obtain an optimal drive voltage for all pixels in a short time.
[0052]
<Modification 2 of Embodiment 2>
In the present modification, when determining the optimum drive voltage for each pixel, the controller 7 calculates the initial cathode drive voltage of each pixel as the average of the optimum cathode drive voltage value data obtained for the previous pixels in the same panel. Set to a value. The flowchart is shown in FIG. The flow of steps (1) to (6) in FIG. 8 is the same as that of the second embodiment (FIG. 7).
[0053]
On the other hand, in step (7) of FIG. 8, the controller 7 sets the initial cathode drive voltage of the pixel to a pixel previously obtained in the same panel (here, the target pixel is Is also set to the average value of the optimum cathode drive voltage value data (data temporarily stored in the controller 7) of all the pixels measured previously or some of the pixels.
[0054]
For example, if the initial cathode drive voltage of the pixel is set based on the average value of the optimum cathode drive voltages of all the pixels measured before the pixel, the initial cathode drive voltage of the n-th pixel is obtained. Is expressed by a relational expression of initial cathode drive voltage = (Vk1 + Vk2 +... + Vkn-1) / (n-1). Here, Vkm is an optimal drive voltage for the m-th pixel. In this case, the first pixel (m = n = 1) is driven by an arbitrary driving voltage.
[0055]
As described above, according to this modification, the initial cathode drive voltage of each pixel is set to the average value of the optimal drive voltages obtained before, so that even if the optimal drive voltage varies between panels, it can be achieved in a short time. An optimum drive voltage can be obtained for all pixels.
[0056]
<Variation 3 of Embodiment 2>
A feature of the present modification is that, when obtaining an optimum drive voltage for each pixel, the initial cathode drive voltage of each pixel is set to the same value as the optimum drive voltage obtained for the immediately preceding adjacent pixel. It is in. However, for the first pixel, an appropriate value is set as the initial cathode drive voltage.
[0057]
In this case, the controller 7 controls the gate drive circuit 4 and the cathode drive circuit 6 so that adjacent pixels are sequentially turned on as the order of lighting the pixels.
[0058]
Normally, the characteristics of adjacent pixels are very similar. By setting in this way, the difference between the reference set value and the measured value can be constantly reduced, making it even more optimal in a shorter time. A high driving voltage can be obtained.
[0059]
As described above, according to the present modification, the adjacent pixels are sequentially turned on, and the initial cathode drive voltage of each pixel is set to be the same as the optimal drive voltage obtained for the immediately preceding adjacent pixel, thereby further improving the drive voltage. An optimum drive voltage can be obtained for all pixels in a short time.
[0060]
<Modification 4 of Embodiment 2>
This modification relates to a common modification technique for each of the second embodiment and the first to third modifications. The feature of the modification is that information to be compared with the reference set value by the controller 7 is replaced by an anode current. This is in terms of the light emission luminance of each pixel.
[0061]
FIG. 9 is a block diagram of the FED device according to the present modification. In the drive circuit of FIG. 9, the anode power supply 3, the gate drive circuit 4, the cathode drive circuit 6, the controller 7, and the recording device 9 are the same as the corresponding components in the second embodiment (FIG. 5). Therefore, the only component different from FIG. 5 is the luminance meter 10 that measures the luminance of each pixel each time the pixel is turned on.
[0062]
Next, the operation of the present apparatus will be described. However, the basic operation is the same as the operation described in the second embodiment.
[0063]
First, in response to the control signals V71 and V72 from the controller 7, the gate drive circuit 4 and the cathode drive circuit 6 generate a drive waveform for turning on one pixel in the FED panel 2. Accordingly, the one pixel is turned on, and during the lighting period, the luminance meter 10 measures the luminance of the one pixel and inputs the measured data to the controller 7.
[0064]
Next, the controller 7 compares the measured luminance value with a reference set value relating to the luminance held in advance therein, and if there is no difference, determines the cathode drive voltage at that time as an optimal cathode drive voltage value. Then, the data of the optimum cathode drive voltage value is transmitted and stored in the recording device 9. On the other hand, if there is a difference, the controller 7 varies the cathode drive voltage at that time so that the two luminance values match each other. Then, the controller 7 repeats the above operation to transmit the cathode drive voltage (hereinafter, this voltage is referred to as an optimum drive voltage A) when the measured luminance value matches the reference set value to the recording device 9. Store.
[0065]
In general, the brightness and the anode current are in a proportional relationship, but depending on the manufacturing accuracy of the panel, the electrons emitted from the electron source may not reach the phosphor in the same way in each pixel, so that the brightness and the anode current may be different. The proportional relationship with the current may be slightly shifted. However, even in such a case, the luminance variation can be accurately corrected by directly measuring the luminance of each pixel and obtaining the optimum drive voltage A as in the present modification.
[0066]
The procedure for obtaining the optimum drive voltage A for all pixels corresponds to the procedure in Embodiment 2 in which the anode current value is replaced with a measured luminance value.
[0067]
Further, the procedure for obtaining the optimum drive voltage A for all the pixels in a shorter time corresponds to the procedure in which the anode current value in each of Modifications 1 to 3 of the second embodiment is replaced with a measured luminance value.
[0068]
As described above, since the optimum drive voltage A is obtained after directly measuring the brightness of each pixel, according to this modification, the optimum cathode drive voltage value for correcting the brightness variation with higher accuracy. Data can be obtained.
[0069]
(Embodiment 3)
The feature of the present embodiment is that the driving device is configured by combining the FED panel driving device according to the first embodiment and the FED panel driving device according to the second embodiment or the first to fourth modifications thereof. On the point.
[0070]
FIG. 10 is a block diagram of the FED device according to the present embodiment. As shown in FIG. 10, this device has the circuit described in the second embodiment or its modified examples 1 to 3 in addition to the circuit described in the first embodiment. Further, the frame memory 5 has the function as the recording device 9 described in the second embodiment or the first to third modifications thereof.
[0071]
Here, the gate control signal switch 11 switches between the control signal (timing signal) V1 from the control circuit 1 and the first control signal V71 from the controller 7, and the cathode control signal switch 12 switches the control signal 1 from the control circuit 1. The control signal V1 (timing signal), VB (video data), the voltage value data V5 from the frame memory 5, and the second control signal V72 from the controller 7 are switched in synchronization with the gate control signal switch 11. The control circuit 1 or the controller 7 or a control unit (not shown) generates and outputs a switching clock (not shown) for synchronously controlling the switching operation (switching operation) of the switching units 11 and 12. Clock generation unit).
[0072]
Next, the operation of the present apparatus will be described. First, the gate control signal switching device 11 and the cathode control signal switching device 12 respectively control the drive circuits 4 and 4 corresponding to the control signals V71 and V72 from the controller 7 according to the input timing of the switching clock at the first level. The controller 7 and the corresponding drive circuits 4 and 6 are connected to each other so as to be transmitted to the controller 6. By this connection, the controller 7 performs the operation described in the second embodiment or the first to third modifications thereof to obtain the optimum cathode drive voltage for each pixel in the FED panel 2 for each pixel. Then, the optimum cathode drive voltage value data is sequentially written directly to the frame memory 5.
[0073]
After the acquisition mode of the optimum cathode drive voltage value data for all pixels is completed, the present apparatus corrects the luminance variation of each pixel using the above-described optimum cathode drive voltage value data set in the frame memory 5. Transition to the mode to perform. That is, according to the input timing of the switching clock switched from the first level to the second level, the gate control signal switch 11 and the cathode control signal switch 12 respectively control the control signal and the frame from the control circuit 1. The control circuit 1 and the gate drive circuit 4 and the control circuit 1, the frame memory 5 and the cathode drive circuit 6 are connected to each other so that the voltage value data from the memory 5 is transmitted to each of the drive circuits 4 and 5. Connecting. By this connection switching, the mode is changed, and as a result, the device corrects the luminance variation and displays the video data by the operation described in the first embodiment.
[0074]
Here, the above-mentioned operation mode for obtaining the optimum drive voltage of each pixel is performed at the time of initial luminance variation correction after the initial aging of the FED panel 2 is completed, and at the same time, in order to correct the luminance variation due to aging. (For example, the switching clock generator periodically performs the switching control according to the time counted by a timer (not shown) inside the apparatus). Alternatively, in place of the latter regular execution, for example, when the user presses a switch provided in the present apparatus at any time, the switching clock generation unit performs the switching control in conjunction with the switching clock generation unit. The user may be allowed to execute the optimum drive voltage value data acquisition operation mode at any time. When the optimal drive voltage value data acquisition operation mode is periodically performed, a small number of pixels are set every time the power switch of the FED device is turned on so that the user does not care about the video interruption time. , The above operations are preferably performed.
[0075]
As a matter of course, in the present embodiment, an electrically rewritable memory is used as the memory used for the frame memory 5.
[0076]
The FED panel driving device according to the present embodiment can exhibit its effectiveness when the FED device is mainly used as a display for displaying a still image. However, it is not prohibited to apply the driving apparatus of FIG. 10 to a display for displaying a moving image.
[0077]
In view of the description in the fourth modification of the second embodiment, the luminance meter 10 in FIG. 9 can be applied to the device in FIG. 10 instead of the resistor 8 in FIG.
[0078]
In this way, by combining the luminance variation correction circuit and the circuit for obtaining the optimum cathode drive voltage value data, it is possible to correct the luminance variation due to aging with high accuracy.
[0079]
(Note)
As described above, the embodiments of the present invention have been disclosed and described in detail. However, the above description exemplifies applicable aspects of the present invention, and the present invention is not limited thereto. That is, various modifications and variations to the described aspects can be considered without departing from the scope of the present invention.
[0080]
For example, the controller 7 according to the second embodiment and its modifications may be realized by a computer. In this case, when all the desired cathode drive voltage data is stored in the recording device (a hard disk inside the computer or an external storage medium (disk or the like)) 9 via a driver, the computer and each of the circuits 4 and 6 are stored. , And then the FED device of FIG. 1 may be constructed.
[0081]
【The invention's effect】
The subject of the present invention is that the cathode drive circuit changes the cathode drive voltage for each pixel according to the set value in the frame memory, and only uses the video data for the pulse width modulation drive of the data pulse. Therefore, there is an effect that the luminance variation can be corrected with high accuracy without reducing the number of gradations of the video data.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an FED device according to Embodiment 1 of the present invention.
FIG. 2 is a timing chart showing driving waveforms in the FED device according to the first embodiment.
FIG. 3 is a diagram showing a driving voltage-luminance characteristic of each pixel in the FED panel.
FIG. 4 is a diagram showing driving voltage-luminance characteristics of a plurality of pixels in an FED panel.
FIG. 5 is a block diagram showing a configuration of an FED device according to Embodiment 2 of the present invention.
FIG. 6 is a diagram showing an anode current-luminance characteristic of each pixel in the FED panel.
FIG. 7 is a flowchart illustrating an operation procedure of the FED device according to the second embodiment.
FIG. 8 is a flowchart illustrating an operation procedure of an FED device according to a second modification of the second embodiment.
FIG. 9 is a block diagram showing a configuration of an FED device according to a fourth modification of the second embodiment.
FIG. 10 is a block diagram showing a configuration of an FED device according to Embodiment 3 of the present invention.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 control circuit, 2 FED panel, 3 anode power supply, 4 gate drive circuit, 5 frame memory, 6 cathode drive circuit, 7 controller, 8 resistor, 9 recording device, 10 luminance meter, 11 gate control signal switch, 12 cathode control Signal switch.

Claims (11)

A back panel having a plurality of electron-emitting devices arranged in a matrix, a plurality of gate electrodes as row electrodes, and a plurality of cathode electrodes as column electrodes that three-dimensionally intersect each gate electrode, and an anode electrode and on the anode electrode A driving device for driving a field emission display panel in which a front panel having a formed phosphor and forming a light emitting surface is opposed to each other,
A control circuit that generates a timing signal based on the synchronization signal, and outputs the timing signal and video data for each pixel;
A gate drive circuit that generates a scan pulse based on the timing signal output from the control circuit and applies the scan pulse to a corresponding gate electrode;
The cathode drive voltage value data for each pixel that is set in advance is stored, and the cathode of the pixel corresponding to each cathode electrode that intersects the corresponding gate electrode according to the timing signal output from the control circuit. A frame memory for sequentially outputting drive voltage value data,
Based on the timing signal and the video data output from the control circuit, modulate the pulse width of the data pulse of the pixel related to the video data, and based on the cathode drive voltage value data of the pixel output from the frame memory A cathode drive circuit for changing a cathode drive voltage of the data pulse of the pixel, and applying a modulated / changed data pulse to a cathode electrode corresponding to the pixel.
Drive device for field emission display panel. The driving device for a field emission display panel according to claim 1, wherein
The frame memory comprises a ROM,
Drive device for field emission display panel. A back panel having a plurality of electron-emitting devices arranged in a matrix, a plurality of gate electrodes as row electrodes, and a plurality of cathode electrodes as column electrodes that three-dimensionally intersect each gate electrode, and an anode electrode and on the anode electrode A driving device for driving a field emission display panel in which a front panel having a formed phosphor and forming a light emitting surface is opposed to each other,
A gate drive circuit that applies a gate drive voltage corresponding to each of the plurality of gate electrodes;
A cathode drive circuit that applies a cathode drive voltage corresponding to each of the plurality of cathode electrodes;
An anode power supply for applying a constant voltage to the anode electrode;
A resistor connected between the negative terminal of the anode power supply and ground,
The gate drive circuit, the cathode drive circuit and connected to the anode power supply side terminal of the resistor, and outputs a first control signal for instructing the value of the gate drive voltage to the gate drive circuit, and A controller for controlling lighting of one pixel in the field emission display panel by outputting a second control signal for instructing a value of the cathode drive voltage to a cathode drive circuit;
A recording device that stores optimal cathode drive voltage value data at the time of lighting of the one pixel transmitted from the controller,
The controller is
(1) The first control signal and the second control signal for instructing the setting of the initial cathode drive voltage are issued to light the one pixel, and then the measured value of the anode current flowing through the anode electrode at that time is calculated. Calculated based on the measured voltage drop of the resistor,
(2) comparing the measured anode current value with a previously set reference value of the anode current,
(3) When the measured anode current value matches the reference set value, the cathode drive voltage value at that time is determined as the optimum cathode drive voltage value data, and the optimum cathode drive voltage value data is stored in the recording device. While sending to
(4) When there is a difference between the measured anode current value and the reference set value, the cathode drive voltage value at that time is variably controlled so that the measured anode current value matches the reference set value. Then, the measurement of the anode current and the subsequent comparison process are executed again,
(5) When the anode current measurement value obtained by the re-measurement matches the reference set value, the above step (3) is executed, while the anode current measurement value obtained by the re-measurement becomes the reference set value. If the values do not match, the above step (4) is repeated until the values match.
Drive device for field emission display panel. The driving device for a field emission display panel according to claim 3, wherein
The controller is
By illuminating all the pixels in the field emission display panel one by one and performing the above steps (1) to (5) for the illumination of each pixel, the optimum cathode drive voltage value data for each pixel is obtained. Is recorded in the recording device,
Drive device for field emission display panel. The driving device for a field emission display panel according to claim 4, wherein
The controller is
The initial cathode drive voltage of each pixel is set to a value common to all pixels,
Drive device for field emission display panel. The driving device for a field emission display panel according to claim 4, wherein
The controller is
Setting the initial cathode drive voltage of each pixel to the average value of the optimum cathode drive voltage value data of the pixel obtained before the pixel in the same panel,
Drive device for field emission display panel. The driving device for a field emission display panel according to claim 4, wherein
The controller is
Adjacent pixels are sequentially lit, and the initial cathode drive voltage of each pixel is set to an optimal cathode drive voltage of a pixel adjacent to the previously lit pixel.
Drive device for field emission display panel. The driving device for a field emission display panel according to claim 3, wherein:
In place of the resistor, a luminance meter is provided for directly measuring the luminance of a single lit pixel,
The controller is
Instead of the comparison process between the anode current measurement value and the reference set value, a comparison process is performed between a luminance measurement value obtained by the luminance meter and a reference setting value of luminance held in advance, and the luminance measurement value and the luminance Until the reference set value is matched, variably control the cathode drive voltage value for the pixel,
Drive device for field emission display panel. The driving device for a field emission display panel according to claim 1, wherein
The controller according to any one of claims 3 to 7,
4. The resistor of claim 3,
The anode power supply according to claim 3,
A gate control signal switch that switches between the timing signal output from the control circuit and the first control signal output from the controller;
A cathode control signal switch for switching between the timing signal and the video data output from the control circuit, the cathode drive voltage value data output from the frame memory, and the second control signal output from the controller; Is further provided,
The frame memory also serves as the recording device according to claim 3.
Drive device for field emission display panel. The driving device for a field emission display panel according to claim 1, wherein
The controller according to claim 8,
The luminance meter according to claim 8,
A gate control signal switch that switches between the timing signal output from the control circuit and the first control signal output from the controller;
A cathode control signal switch for switching between the timing signal and the video data output from the control circuit, the cathode drive voltage value data output from the frame memory, and the second control signal output from the controller; Is further provided,
The frame memory also serves as the recording device according to claim 3.
Drive device for field emission display panel. The drive device according to any one of claims 1, 2, 9, and 10,
A field emission display panel driven by the driving device,
Field emission display device.

Images