JP2004343426A - Dither current control circuit for solenoid - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a dither current control circuit which exactly detects current passing through a solenoid with low-cost and simple circuit constitution when dither current control is done. <P>SOLUTION: An OR gate 48 ORs a 100 Hz signal (a) for conducting the dither current control and a 10 kHz signal d having ON width narrower than the signal b and outputs a resulting signal e to an AND gate 47. The AND gate 47 ANDs a signal e outputted from the OR gate 48 and the 10 kHz signal b for controlling the current passing through the solenoid 41 and outputted from a CPU 49, and outputs a resulting signal f to the gates of MOS transistors 42, 44. The CPU 49 calculates a ratio of the duty of the signal b to the duty of the signal d from a measured current value and a command current value, and calculates the duty of the signal (a) from power source voltage V, the measured current value and the command current value. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a dither current control circuit for a solenoid.
[0002]
[Prior art]
As a current detection circuit of a semiconductor switch that controls a current supplied to an inductive load, for example, Japanese Patent No. 2776980 discloses a sample / hold circuit that detects a voltage proportional to a current flowing through an inductive load. It describes that a voltage held in a capacitor is discharged using an oscillator.
[0003]
As a solenoid drive circuit, a half bridge circuit as shown in FIG. 8 is known.
8 includes a MOS transistor 12 for controlling a current supplied to a solenoid 11, a MOS transistor 13 for releasing energy stored in a coil of the solenoid 11 when the MOS transistor 12 is off, and a MOS transistor A driver 14 for turning on and off the transistors 12, 13; a current detection resistor 15 for detecting a current flowing through the solenoid 11; a capacitor 16 and a resistor 17 for holding a voltage across the current detection resistor 15; And a CPU 18 for outputting a control signal to the CPU 14 and detecting the voltage of the capacitor 16.
[0004]
According to the half-bridge circuit described above, the voltage at both ends of the current detection resistor 15 is held in the capacitor 16, and the current flowing through the solenoid 11 is calculated from the voltage, whereby the current of the solenoid 11 can be appropriately controlled.
However, the half-bridge circuit described above requires the use of two large-current MOS transistors for controlling the current of the solenoid 11, which increases the component cost.
[0005]
Therefore, as shown in FIG. 9, a circuit comprising one MOS transistor 21, a diode 24 connected in parallel with the solenoid 11, a driver 22, and a CPU 23 for outputting a control signal to the driver 22 has been proposed. . This circuit requires only one MOS transistor, but has a problem that the current flowing through the solenoid 11 cannot be detected.
[0006]
In the current control of the solenoid 11, dither current control for supplying a pulsating current to the solenoid 11 is performed to shorten the response time of the solenoid 11. FIG. 10 shows an example of the dither current control circuit.
The dither current control circuit shown in FIG. 10 includes a solenoid 11, a MOS transistor 31 for controlling the current of the solenoid 11, a current detection resistor 32, and a MOS transistor 33 for holding a voltage across the current detection resistor 32 by a capacitor 34. And a diode 35 connected in parallel with the solenoid 11, an AND gate 36 for supplying a control signal to the MOS transistors 31 and 33, and a control signal for detecting a voltage of the capacitor 34 and controlling a current flowing through the solenoid 11 are output. And a CPU 37 for performing the operation.
[0007]
The CPU 37 outputs a 100 Hz signal a and a 10 kHz signal b for performing dither current control to the AND gate 36. From the output terminal of the AND gate 36, a signal c which is the logical product of the two is output to the gates of the MOS transistors 31 and 33. The MOS transistors 31 and 33 are turned on and off by the signal c, and a pulsating current is supplied to the solenoid 11 at a cycle of 100 Hz, so that dither current control is performed.
[0008]
FIG. 11 is a waveform diagram of the control signals a to c output from the CPU 37, and FIG. 12 is a waveform diagram showing the current flowing through the solenoid 11 and the voltage of the capacitor.
The signal a is a 100 Hz signal, and the signal b is a 10 kHz signal. In FIG. 11, the vertical axis represents the voltage V, and the horizontal axis represents m second.
[0009]
While the signal a of 100 Hz is on (high level), the signal b of 10 kHz is output as it is from the AND gate 36 as it is, and the signal c remains at low level while the signal of 100 Hz is off (low level). Become.
Next, the operation of the circuit of FIG. 10 will be described with reference to the waveform diagram of FIG. During the ON period of the signal a at 100 Hz, the current of the solenoid increases with a time constant corresponding to the ON width of the signal b and the value of the inductance of the solenoid 11, and a voltage proportional to the current flowing through the solenoid 11 across the current detection resistor 32. Occurs.
[0010]
Therefore, the current of the solenoid 11 and the voltage of the capacitor 34 increase at a constant slope as shown in FIG. The jaggedness of the current and voltage waveforms in FIG. 12 is due to switching at a frequency of 10 kHz.
The CPU 37 calculates the current flowing through the solenoid 11 from the voltage value of the capacitor 34 and controls the current flowing through the solenoid 11 by changing the ON width of the 10 kHz signal b output to the AND gate 36 based on the calculated current value. .
[0011]
While the 100 Hz signal is at the low level, the control signal c output from the AND gate 36 remains at the low level, so that no current is supplied to the solenoid 11. At this time, the current stored in the coil of the solenoid 11 is gradually released through the diode 35, and the current flowing through the solenoid 11 decreases. However, at this time, since the MOS transistor 33 is off, the voltage of the capacitor 34 is not discharged and maintains a constant value.
[0012]
[Patent Document 1]
Japanese Patent No. 2776980 (3 pages, FIG. 1)
[0013]
[Problems to be solved by the invention]
In the dither current control circuit described above, even when the MOS transistors 31 and 33 are turned off and the current flowing through the solenoid 11 is decreasing, the voltage of the capacitor 34 does not change and the current value calculated from the voltage of the capacitor 34 However, there is a problem that the current value does not match the current value flowing through the solenoid 11.
[0014]
In the dither current control circuit described above, an overcurrent detection circuit or the like is usually provided as a protection circuit for preventing an overcurrent from flowing through the solenoid 11, and the current value of the current flowing through the solenoid 11 exceeds a certain threshold. Then, the current flowing through the solenoid 11 is stopped. In such a dither current control circuit in which a protection circuit such as an overcurrent detection circuit is provided, the maximum value of the current flowing through the solenoid 11 due to some influence is set to a threshold value even though the current is normally supplied to the solenoid 11. In order to prevent the over-current detection circuit from erroneously detecting the threshold value, the threshold value needs to be set to a somewhat high value. Therefore, it is necessary to configure the overcurrent detection circuit with an expensive element that can withstand a somewhat high voltage, resulting in a problem that the cost of the entire circuit increases.
[0015]
Therefore, in the present invention, a dither current control circuit capable of accurately detecting a current flowing through a solenoid with a low-cost and simple circuit when performing dither current control in consideration of the above problem. The purpose is to provide.
[0016]
[Means for Solving the Problems]
In order to solve the above problems, the present invention employs the following configuration.
That is, the dither current control circuit of the present invention includes a semiconductor element for controlling a current supplied to a solenoid, a first signal for supplying a pulsating current to the solenoid, and a solenoid having a higher frequency than the first signal. A signal generating circuit for generating a second signal for controlling a current supplied to the first signal and a third signal having a higher ON frequency than the first signal and a narrower ON width than the second signal; During a first period of a first signal, the second signal is supplied to the semiconductor element, and during a second period of the first signal, the third signal is supplied to the semiconductor element. A control circuit for controlling on / off of the semiconductor element, wherein the control circuit varies the duty of the second signal and the duty of the third signal, so that an amplitude value of a waveform of a current flowing through the solenoid is provided. Control the said By varying the sum of the duty of the first signal of duty and said the duty of the second signal a third signal, and controlling the average value of the current flowing through the solenoid.
[0017]
According to this invention, the second period of the first signal for performing the dither current control also turns on and off the semiconductor element by the third signal, so that a smaller amount of current flows through the solenoid than in the normal operation. It is possible to accurately detect the current flowing through the solenoid.
[0018]
Further, according to the present invention, the amplitude value and the current average value of the current waveform of the solenoid can be controlled, so that the maximum current value of the solenoid is reduced while the average value of the current waveform of the solenoid is kept constant. Can be. As a result, the threshold value of the overcurrent detection circuit can be lowered while maintaining the performance of the solenoid, so that the maximum current flowing in the overcurrent detection circuit is reduced, so that the overcurrent detection circuit can be configured with inexpensive elements. It becomes possible, and the cost can be reduced accordingly.
[0019]
Further, a dither current control circuit for a solenoid according to the present invention includes a first semiconductor element for controlling a current supplied to the solenoid, a current detection resistor for detecting a current flowing to the solenoid, and one end connected to a high potential side of the current detection resistor. Is connected, the other end is connected to a capacitor, a first signal for supplying a pulsating current to the solenoid, and a current supplied to the solenoid at a higher frequency than the first signal. A signal generating circuit for generating a second signal for controlling the first signal, a third signal having a higher ON frequency than the first signal, and having a smaller ON width than the second signal, and the first signal During the first period, the second signal is supplied to the first and second semiconductor elements. During the second period of the first signal, the third signal is supplied to the first and second semiconductor elements. To the first and second semiconductor elements. And a control circuit that controls on and off of the semiconductor element of (a), wherein the control circuit varies the duty of the second signal and the duty of the third signal, thereby controlling the amplitude of the waveform of the current flowing through the solenoid. Controlling the average value of the current flowing through the solenoid by controlling the sum of the duty of the first signal, the duty of the second signal, and the duty of the third signal. It is characterized by.
[0020]
According to the present invention, the current flows through the solenoid also during the second period of the first signal for performing the dither current control, so that the current of the solenoid can be detected by the current detection resistor.
In the above invention, the control circuit includes an OR circuit that outputs a logical sum of the first signal and the third signal, and an AND that outputs a logical product of an output signal of the OR circuit and the second signal. And a circuit.
[0021]
With this configuration, the current of the solenoid can be detected by using the OR circuit and the AND circuit.
In the above invention, the second signal and the third signal are signals having the same frequency.
[0022]
With this configuration, the signal generation circuit only needs to generate signals of two kinds of frequencies, the first signal and the second signal.
In the above invention, the first period is an ON period of the first signal, and the second period is an OFF period of the first signal.
[0023]
For example, the first signal of claim 1 corresponds to a signal a of 100 Hz, the second signal corresponds to a signal b of 10 kHz, and the third signal corresponds to a signal d of 10 kHz, which has a narrower ON width than the second signal. . The semiconductor element corresponds to the MOS transistor 42, and the signal generation circuit and the control circuit correspond to the CPU 49.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram of a dither current control circuit of a solenoid 41 used for a lift device of a forklift according to an embodiment of the present invention.
[0025]
The dither current control circuit shown in FIG. 1 includes a solenoid 41, a MOS transistor 42 for controlling a current flowing through the solenoid 41, a current detection resistor 43, a source connected to the high potential side of the current detection resistor 43, and a drain connected to a capacitor 45. , A MOS transistor 44 for holding the voltage across the current detection resistor 43 by the capacitor 45, a diode 46 connected in parallel with the solenoid 41, the cathode side of which is connected to the power supply, and MOS transistors 42 and 44. It comprises an AND gate 47 for supplying a control signal to the gate, an OR gate 48 for outputting a control signal to the AND gate 47, and a CPU 49 for outputting control signals a, b and d for controlling the MOS transistors 42 and 44.
[0026]
The CPU 49 outputs a signal b of 10 kHz for controlling the current flowing through the solenoid 41 to the AND gate 47, a signal a of 100 Hz for performing dither current control, and a signal having an ON width narrower than the signal b at 10 kHz. d is output to the OR gate 48.
[0027]
The OR gate 48 takes the logical sum of the signal a and the signal d and outputs the resulting signal e to the AND gate 47. The AND gate 47 takes the logical product of the signal e output from the OR gate 48 and the signal b output from the CPU 49, and outputs the resulting signal f to the gates of the MOS transistors 42 and 44.
[0028]
The CPU 49 calculates the current flowing through the solenoid 11 from the voltage value of the capacitor 45, and controls the current flowing through the solenoid 41 by changing the ON width of the 10 kHz signal b output to the AND gate 47 according to the calculated current value. .
FIG. 2 is a waveform diagram of the control signals a, b, and d output from the CPU 49, the signal e output from the OR gate 48, and the signal f output from the AND gate 47.
[0029]
From the OR gate 48, the signal e obtained by calculating the logical sum of the signal a and the signal d, that is, the signal a of 100 Hz is at a high level while the signal a is at a high level, and the signal a is at a low level during a period of a low level. , A signal e of 10 kHz is output.
The AND gate 47 outputs a signal f, which is the logical product of the signal e and the signal b. As the signal f, while the 100 Hz signal a is at the high level, a PWM (pulse width modulation) 10 kHz signal b for controlling the current flowing through the solenoid 41 is output, and the 100 Hz signal a is at the low level. Outputs a 10 kHz signal d having a narrower ON width than the signal b.
[0030]
FIG. 3 is a waveform diagram of a current flowing through the solenoid 41 and a voltage of the capacitor 45.
During the ON period (high-level period) of the signal a of 100 Hz, a signal b of 10 kHz is output as the output signal f of the AND gate 47. The PWM control of the MOS transistors 42 and 44 is performed by the signal b, and the current of the solenoid 41 increases with a time constant according to the ON width of the signal b and the inductance value of the solenoid 41. At this time, a voltage proportional to the current flowing through the solenoid 41 is generated at both ends of the current detection resistor 43. The voltage at both ends of the current detection resistor 43 is held by the capacitor 45, and the current flowing through the solenoid 41 is controlled by the CPU 49 according to the voltage.
[0031]
Accordingly, during the ON period of the signal a of 100 Hz, the current waveform of the solenoid 41 and the voltage waveform of the capacitor 45 increase with substantially the same slope as shown in the waveform diagram of FIG.
During the off period (low-level period) of the 100 Hz signal, the output signal f of the AND gate 47 is a 10 kHz signal d whose on width is narrower than the signal b. The MOS transistors 42 and 44 are turned on and off by the signal d.
[0032]
Since the ON width of the signal d is set to such a value that a small amount of current flows through the solenoid 41, as shown in FIG. 3, the current waveform of the solenoid 41 and the voltage waveform of the capacitor 45 are the ON width of the signal d. And the slope determined by the value of the inductance of the solenoid 41.
[0033]
The diode 46 in FIG. 1 releases the energy of the solenoid 41 during the off period of the signal f in FIG. 2 regardless of whether the 100 Hz signal is on or off. Since the ON period of the signal of 100 Hz is long during the ON period of the signal of 100 Hz, the energy from the power supply is large and the current gradually increases while slightly releasing the energy of the solenoid 41. In the off period of the signal of 100 Hz, the off period of the signal of 10 kHz is long, so that the time for releasing the energy of the solenoid 41 is long, and the current gradually decreases. Therefore, a 100 kHz current waveform has jaggies of 10 kHz.
[0034]
That is, in the off period of the signal a of 100 Hz, the signal d having a narrower ON width than the signal b of 10 kHz supplied in the ON period is supplied to the MOS transistor 42 to supply a small current to the solenoid 41, so that the current detection resistance is reduced. A voltage proportional to the current of the solenoid 41 can be generated at both ends of the solenoid 43. Also, by supplying the same signal d to the gate of the MOS transistor 44 at the same time, a voltage proportional to the current flowing through the solenoid 41 can be held as the voltage of the capacitor 45. Can be accurately calculated.
[0035]
According to the above-described embodiment, the current flowing through the solenoid 41 is held by the capacitor 45 by slightly flowing the current even during the off period of the 100 Hz signal for performing the dither current control, and the voltage of the capacitor 45 is maintained. Thus, the current flowing through the solenoid 41 can be accurately calculated. As a result, there is no need to provide a discharge circuit or the like for the capacitor 45, and the current of the solenoid 41 can be accurately detected with a simple circuit.
[0036]
Next, control of the current flowing through the solenoid 41 will be described.
FIG. 4 is a flowchart for explaining the operation of the CPU 49 when controlling the current flowing through the solenoid 41.
After the initial setting process, the CPU 49 sets the power supply voltage V (this power supply voltage V fluctuates by a driving device other than the solenoid 41), a command current value (a desired average value of a predetermined current flowing through the solenoid 41), and a capacitor. The duty of each of the signals a, b, and d is determined based on the voltage value detected by 45 (this voltage value fluctuates due to a change in the resistance value according to the type of the solenoid 41 and a temperature change). .
[0037]
First, in step S1, the CPU 49 calculates the total value of the duty of the signal b and the duty of the signal d based on the power supply voltage V. Here, for example, when the power supply voltage V is converted to a voltage equivalent to 15 V and the detected power supply voltage V is 48 V, the total value of the duty of the signal b and the duty of the signal d is (15 V / 48 V). ) × 100 ≒ 31%.
[0038]
Next, in step S2, the CPU 49 calculates a ratio between the duty of the signal b and the duty of the signal d based on the command current value and the actually measured current value corresponding to the voltage value detected by the capacitor 45.
Here, FIG. 5 shows the signals a, b, and d output from the CPU 49 when the ratio between the duty of the signal b and the duty of the signal d in FIG. FIG. 5 is a waveform diagram of a signal f output from an AND gate 47. FIG. 6 is a current waveform diagram of the solenoid 41 in a state where a certain time has elapsed and the current waveform is stable in the dither current control of FIG. FIG. 7 is a diagram showing a waveform of a current flowing through the solenoid 41 controlled by the signal f in FIG. Note that the current waveform shown in FIG. 7 is in a state where a certain time has elapsed and the current waveform is stabilized.
[0039]
For example, when the command current value is larger than the measured current value, the duty of the signal d is increased to make the measured current value closer to the command current value (for example, the duty of the signal d in FIG. d is 10%). Accordingly, the duty of the signal b is reduced (for example, the duty of the signal b in FIG. 2 is set to 26%, and the duty of the signal b in FIG. 5 is set to 21%. At this time, in both cases of FIGS. 2 and 5) The total value of the duty of the signal b and the duty of the signal d is 31%). Thus, the slope of the current waveform when the current flowing through the solenoid 41 increases decreases, and the slope of the current waveform when the current flowing through the solenoid 41 decreases decreases. Therefore, the amplitude of the current waveform of the solenoid 41 can be reduced.
[0040]
Next, in step S3, the CPU 49 calculates the duty of the signal a based on the voltage value detected by the capacitor 45. Here, for example, when the resistance value of the solenoid 41 calculated based on the voltage value of the capacitor 45 is 10Ω and the command current value is 1A, and the power supply voltage V converted by the signal b and the signal d is 15 V In this case, the target voltage value applied to the solenoid 41 is 10 V, and the duty of the signal a is calculated as (10 V / 15 V) × 100 ≒ 67%.
[0041]
Then, in step S4, the CPU 49 outputs the signals a, b, and d calculated in steps S2 and S3 to the AND gate 47 and the OR gate 48.
As described above, the average value of the current flowing through the solenoid 41 can be controlled by varying the sum of the duty of the signal b and the duty of the signal d and the duty of the signal a. Further, the amplitude value of the waveform of the current flowing through the solenoid 41 (the maximum value of the current flowing through the solenoid 41) can be controlled by varying the ratio between the duty of the signal b and the duty of the signal d. That is, as shown in FIGS. 6 and 7, the amplitude value of the current waveform can be reduced while the current flowing through the solenoid 41 is kept constant.
[0042]
Accordingly, when the overcurrent detection circuit is provided in the solenoid 41, the maximum value of the current flowing through the solenoid 41 can be reduced without lowering the average value of the current flowing through the solenoid 41, and the performance of the solenoid is maintained. Since the threshold value of the overcurrent detection circuit can be reduced, the maximum current flowing through the overcurrent detection circuit is reduced, so that a current detection resistor 43 that is a part of the overcurrent detection circuit, and a MOS transistor 42 that controls the current, , And the diode 46 can also be composed of inexpensive elements, and the cost can be reduced accordingly.
[0043]
The present invention is not limited to the above embodiment, but may be configured as follows.
(Other embodiments)
(A) In the above embodiment, the signal b for controlling the MOS transistors 42 and 44 during the ON period of the signal a and the signal d for controlling the OFF period of the signal a are signals having the same frequency. There may be.
(B) The dither current control circuit is not limited to the circuit including the current detection resistor 43, the capacitor 45, the OR gate 48, and the like described in the embodiment, and a circuit having another configuration may be used.
(C) The semiconductor element for controlling the current of the solenoid 41 is not limited to the MOS transistor, but may be another semiconductor switch element such as a bipolar transistor or a GTO.
(D) The present invention is not limited to the solenoid 41 used in the lifting device of the forklift, and can be applied to a control circuit of a solenoid used in another device.
(E) In the above embodiment, the signal a is set to 100 kHz, and the signal b and the signal d are set to 10 kHz. However, the frequencies of the signals a, b, and d may be changed according to the inductance of the solenoid 41.
(F) In the above embodiment, the present invention is applied to the dither current control. However, by reducing the amplitude of the waveform of the current flowing through the solenoid 41, a solenoid solenoid valve driven by an ON / OFF control signal that does not need to control the dither current is used. Also applicable to
[0044]
【The invention's effect】
According to the present invention, the current of the solenoid can be detected by a simple circuit by constantly turning on and off the semiconductor element and slightly flowing the current to the solenoid.
Also, since the maximum value of the current flowing through the solenoid can be reduced without lowering the average value of the current flowing through the solenoid, the threshold value of the overcurrent detection circuit can be reduced while maintaining the performance of the solenoid. Since the maximum current flowing in the overcurrent detection circuit is reduced, the overcurrent detection circuit can be configured with inexpensive elements, and the cost can be reduced accordingly.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a dither current control circuit according to an embodiment.
FIG. 2 is a waveform diagram of a control signal.
FIG. 3 is a waveform diagram of a solenoid current and a capacitor voltage.
FIG. 4 is a flowchart illustrating an operation of a CPU.
FIG. 5 is a waveform diagram of a control signal.
FIG. 6 is a waveform diagram of a current of a solenoid.
FIG. 7 is a waveform diagram of a current of a solenoid.
FIG. 8 is a circuit diagram of a half-bridge type circuit.
FIG. 9 is a circuit diagram of a current control circuit using one MOS transistor.
FIG. 10 is a circuit diagram of a conventional dither current control circuit.
FIG. 11 is a waveform diagram of a control signal.
FIG. 12 is a waveform diagram of a solenoid current and a capacitor voltage.
[Explanation of symbols]
41 Solenoids 42 and 44 MOS transistor 43 Current detection resistor 45 Capacitor 47 AND gate 48 OR gate 49 CPU

Claims (5)

A semiconductor element for controlling a current supplied to the solenoid,
A first signal for supplying a pulsating current to the solenoid, a second signal for controlling the current supplied to the solenoid at a higher frequency than the first signal, and a frequency higher than the first signal; A signal generation circuit for generating a third signal having a narrower ON width than the second signal;
In the first period of the first signal, the second signal is supplied to the semiconductor element, and in the second period of the first signal, the third signal is supplied to the semiconductor element. A control circuit for controlling on / off of the semiconductor element;
With
The control circuit controls the amplitude value of the waveform of the current flowing through the solenoid by varying the duty of the second signal and the duty of the third signal, and controls the duty of the first signal and the duty of the first signal. A dither current control circuit for a solenoid, wherein an average value of a current flowing through the solenoid is controlled by varying a total value of a duty of the second signal and a duty of the third signal. A first semiconductor element for controlling a current supplied to the solenoid,
A current detection resistor for detecting a current flowing through the solenoid,
A second semiconductor element having one end connected to the high potential side of the current detection resistor and the other end connected to a capacitor;
A first signal for supplying a pulsating current to the solenoid, a second signal for controlling the current supplied to the solenoid at a higher frequency than the first signal, and a frequency higher than the first signal; A signal generation circuit for generating a third signal having a narrower ON width than the second signal;
In a first period of the first signal, the second signal is supplied to the first and second semiconductor elements, and in a second period of the first signal, the third signal is supplied to the first and second semiconductor elements. A control circuit for supplying to the first and second semiconductor elements to control on and off of the first and second semiconductor elements;
With
The control circuit controls the amplitude value of the waveform of the current flowing through the solenoid by varying the duty of the second signal and the duty of the third signal, and controls the duty of the first signal and the duty of the first signal. A dither current control circuit for a solenoid, wherein an average value of a current flowing through the solenoid is controlled by varying a total value of a duty of the second signal and a duty of the third signal. The control circuit includes an OR circuit that outputs a logical sum of the first signal and the third signal, and an AND circuit that outputs a logical product of an output signal of the OR circuit and the second signal. Item 3. A dither current control circuit for a solenoid according to item 1 or 2. 4. The dither current control circuit for a solenoid according to claim 1, wherein said second signal and said third signal are signals having the same frequency. 5. The dither current control circuit for a solenoid according to claim 1, wherein said first period is an on period of said first signal, and said second period is an off period of said first signal. .

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