JP2004342960A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device provided with grooved element separation capable of easing the compression stress of a buried insulating film independently of the aperture width of the groove and having uniform and effective element performance, and to provide a method for manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device is provided with a semiconductor substrate 3 having grooves 5 on the surface side, insulating films 7 filled in the grooves 5, and contraction films 9 formed on the inwalls of the grooves 5 in a state that tensile stress is applied between the inwall of the groove 5 and the insulating film 7. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device having a trench type element isolation and a method of manufacturing the same.
[0002]
[Prior art]
As the element structure of a semiconductor device becomes finer and the design rule (minimum design line width) becomes 90 nm or less, the compressive stress of a buried insulating film of a shallow trench isolation (STI) greatly affects the element performance. It comes to exert. For example, in an NMON transistor, the compressive stress from a buried insulating film made of silicon oxide gives a strain to a silicon structure in an active region and lowers carrier mobility of electrons, so that the performance of the transistor deteriorates. Since the manner in which the compressive stress is applied changes depending on the width of the trench and the size of the active region, this is a factor that causes the performance of individual transistors to vary.
[0003]
Therefore, there has been proposed a semiconductor device having a configuration in which a space is provided inside a buried insulating film, and the compressive stress of the buried insulating film is relaxed in the space. In a semiconductor device having such a configuration, a groove having a width of an upper opening smaller than that of a lower portion is formed on the front surface side of the semiconductor substrate, and when an insulating film is formed on the semiconductor substrate so as to fill the groove, By closing the upper opening of the groove with an insulating film before is embedded with an insulating film, a space portion located at the center of the groove is provided inside the buried insulating film (see Patent Document 1 described below).
[0004]
[Patent Document 1]
JP 2000-183149 A [0005]
[Problems to be solved by the invention]
However, in the above-described configuration, it is difficult to form a space inside the groove depending on the width and depth of the groove. That is, when the width of the groove is twice or more the depth, the upper opening of the groove cannot be closed with the insulating film before the inside of the groove is filled with the insulating film in the process of forming the insulating film. A space cannot be formed in the film. In this case, even if a space is formed, the space cannot be located in the groove.
[0006]
Therefore, in a trench type element isolation (STI) in which a large width causes a particularly large compressive stress, the compressive stress cannot be reduced, and the effect when applied to an actual semiconductor device is small. Further, in an actual semiconductor device having element isolations with various opening widths, it is not possible to provide a space in all STIs to alleviate the compressive stress of the buried insulating film, and therefore, the performance of the element such as a MOS transistor varies. There is no effect of suppressing.
[0007]
Accordingly, the present invention provides a semiconductor device having a groove-type element isolation capable of relaxing the compressive stress of a buried insulating film irrespective of the opening width of the groove, thereby providing a uniform and good element performance, and a method of manufacturing the same. The purpose is to:
[0008]
[Means for Solving the Problems]
A semiconductor device according to the present invention for achieving the above object relates to a semiconductor device in which an insulating film is filled in a groove formed on a front surface side of a semiconductor substrate. A contraction film is provided on the inner wall of the groove in a state where a tensile stress is applied to the insulating film.
[0009]
In the first semiconductor device having such a configuration, the compressive stress of the insulating film is alleviated by the tensile stress of the contracting film by the contracting film provided between the insulating film filled in the groove and the inner wall of the groove. You. Therefore, it is possible to prevent the semiconductor substrate from being distorted due to the compressive stress of the insulating film being applied to the semiconductor substrate.
[0010]
Further, the second semiconductor device is characterized in that the insulating film is filled with the space maintained at a position along the inner wall below the groove of the semiconductor substrate.
[0011]
In the second semiconductor device having such a configuration, the compressive stress of the insulating film filled in the groove is absorbed by the space maintained at a position along the lower inner wall of the groove of the semiconductor substrate. Therefore, it is possible to prevent the semiconductor substrate from being distorted due to the compressive stress of the insulating film being applied to the semiconductor substrate.
[0012]
The present invention is also the first method for manufacturing a semiconductor device described above. First, in a first step, a material film which contracts by heating is formed along an inner wall of a groove formed on a front surface side of a semiconductor substrate, In the next second step, an insulating film is buried in the groove via the material film, and in the subsequent third step, the material film is contracted by heating.
[0013]
In such a manufacturing method, after the insulating film is filled in the groove via the material film, the material film on the inner wall of the groove is contracted by heating. Therefore, between the insulating film and the inner wall of the groove, regardless of the shape of the groove, a material film contracted by heating is provided as a contracted film to which a tensile stress is applied between the inner wall of the groove and the insulating film. Can be In addition, as a material film, porous silica, hydrosilissiquioxane, or methylsilisisquioxane is used.
[0014]
The present invention is also the above-described second semiconductor device manufacturing method. First, in the first step, a material film which is vaporized by heating is formed in a state of covering the inner wall of the groove formed on the front surface side of the semiconductor substrate. Then, the material film is etched back to leave the material film only on the lower inner wall of the groove. Next, in a second step, an insulating film is buried in the groove via the material film left in the groove, and in a subsequent third step, the material film component vaporized by heating is filled in the groove via the insulating film. And a space is formed at a position along the lower inner wall of the groove.
[0015]
In such a manufacturing method, after the insulating film is filled in the groove via the material film formed on the lower inner wall of the groove, the material film is removed from the inside of the groove by being vaporized by heating. Therefore, a space from which the material film has been removed is formed between the insulating film and the lower inner wall of the groove regardless of the shape of the groove.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the configuration of the semiconductor device of the present invention will be described in detail with reference to the drawings.
[0017]
<First embodiment>
FIG. 1 is a sectional view of a main part of the semiconductor device of the first embodiment. The semiconductor device shown in FIG. These groove-type element isolations 1 are formed in grooves 5 having respective opening widths formed in a surface layer of a semiconductor substrate 3 made of, for example, single crystal silicon. The inner walls of these grooves 5 are covered with a thin oxide film (insulating film) not shown here, and the inside thereof is filled with an insulating film 7 using silicon oxide. Further, between the inner wall of the groove 5 and the insulating film 7, a shrink film 9 in a state where a tensile stress is applied between the inner wall of the groove 5 and the insulating film 7 is provided.
[0018]
The shrink film 9 is provided in close contact with the oxide film and the insulating film 7 constituting the inner wall of the groove 5, and a tensile stress is applied by being pulled from both sides of the oxide film and the insulating film 7. Such a shrink film 9 is obtained, for example, by shrinking a material film made of porous silica, hydrosilissiquioxane, or methylsilishisquioxane by heating.
[0019]
Then, for example, a MOS type semiconductor element 15 having a gate electrode 13 is provided in the active region 11 on the front surface side of the semiconductor substrate 3 separated by the groove type element isolation 1 having such a configuration. The semiconductor element 15 includes a side wall provided on the side wall of the gate electrode 13 and a source / drain diffusion layer on the surface side of the semiconductor substrate 3.
[0020]
In the semiconductor device having such a configuration, the compressive stress of the insulating film 7 filled in the groove 5 is caused by the contraction film 7 provided between the insulating film 7 filled in the groove 5 and the inner wall of the groove 5. Is alleviated by the tensile stress of the shrink film 7. Therefore, it is possible to prevent the semiconductor substrate 3 from being distorted due to the compressive stress of the insulating film 7 being applied to the semiconductor substrate 3. Thus, the performance of the transistor of the semiconductor element 15 formed in the active region 11 of the semiconductor substrate 3 can be maintained.
[0021]
Next, a method of manufacturing the semiconductor device described with reference to FIG. 1 will be described with reference to FIG.
[0022]
First, as shown in FIG. 2A, a groove 5 is formed in a region where element isolation is to be formed on a semiconductor substrate 3 made of, for example, P-type single crystal silicon. At this time, although not shown here, a silicon nitride film is formed on the semiconductor substrate 3 via a thin oxide film by a CVD method, and a silicon oxide film is formed on the silicon nitride film by the CVD method. The silicon oxide film may be doped with an impurity such as boron so as to be easily removed in the later etching. Next, a resist pattern is formed on the silicon oxide film by a lithography method, and the silicon oxide film and the silicon nitride film are sequentially etched using the resist pattern as a mask, thereby forming a silicon oxide film and a silicon nitride film. An inorganic mask is formed. Thereafter, a groove 5 is formed in the semiconductor substrate 3 by etching from above the inorganic mask.
[0023]
After the groove 5 is formed, the inorganic mask is removed by etching, and the inner wall of the groove 5 is oxidized.
[0024]
Next, a material film 21 made of a material that contracts by heating is formed while covering the inner wall of the groove 5. This material film 21 is made of, for example, porous silica (porous silicon oxide), HSQ (hydrosilsisquioxane), and MSQ (methylsilsisquioxane). Thereafter, the material film 21 is etched back by an etching technique using a CxFy-based gas as an etching gas, and the material film 21 on the surface of the semiconductor substrate 3 is removed. At this time, the material film 21 may remain at the bottom of all the grooves 5 as illustrated. Further, the material film 21 may be left only at the bottom of the groove 5 having a narrow opening width. For example, in the case of the rule having a minimum line width of 90 nm, the material film 21 is formed at the bottom of the groove 5 having a width of 50 nm or less. Is left.
[0025]
After the above, as shown in FIG. 2B, an insulating film 7 made of silicon oxide is formed above the semiconductor substrate 3 so as to fill the trench 5 with the material film 21 interposed therebetween. At this time, the insulating film 7 made of silicon oxide is formed by a film formation method having good embedding characteristics such as a coating method or a high-density plasma CVD method. After that, the surface of the insulating film 7 is flattened by the CMP method, and the insulating film 7 is removed from the surface of the semiconductor substrate 3.
[0026]
Next, the material film 21 is contracted by performing an annealing process using a normal heat treatment furnace. At this time, the annealing temperature is set in the range of 700 ° C. to 900 ° C. By setting the annealing temperature to 700 ° C. or higher, which is equivalent to the glass transition temperature, the insulating film 7 made of silicon oxide formed by the high-density plasma CVD method is rearranged and densified, and the material film 21 is sufficiently formed. To shrink. For example, when the material film 21 is made of porous silica (porous silicon oxide), HSQ (hydrosilsisquioxane), and MSQ (methylsilsisquioxane), each of these materials causes voids to disappear, When the methyl group dissociates and evaporates, it is rearranged and contracted. Further, by setting the annealing temperature to 900 ° C. or lower, the oxidation of the semiconductor substrate 3 made of single crystal silicon is suppressed.
[0027]
As described above, as shown in FIG. 1, the groove-type element isolation 1 in which the contraction film 9 obtained by contracting the material film (21) is provided between the insulating film 7 and the inner wall of the groove 5 is formed. The contraction film 9 is made of silicon oxide, and is in close contact with a thin oxide film (silicon oxide film) covering the inner wall of the groove 5 and the insulating film 7 made of silicon oxide embedded in the groove 5 via the material film 21. In this state, tensile stress is applied between the inner wall of the groove 5 and the insulating film 7.
[0028]
Then, after forming these groove-type element isolations 1, MOS-type semiconductor elements 15 are formed in the active region 11 separated by these groove-type element isolations 1 by a general method.
[0029]
In the manufacturing method of the first embodiment, as described with reference to FIG. 2B, after the insulating film 7 is filled in the groove 5 via the material film 21, the material film 21 contracts by heating. Let it. For this reason, regardless of the shape of the groove 5, the material film 7 contracted by heating has a tensile stress between the insulating film 7 and the inner wall of the groove 5 in a state where the material film 7 is in close contact with the inner wall of the groove 5 and the insulating film 7. Is provided as the shrink film 9 to which the film is added.
[0030]
Therefore, regardless of the opening width of the groove, it becomes possible to form the groove-type element isolation 1 which can relieve the compressive stress of the insulating film 7 buried therein, thereby forming all the active regions 11. A semiconductor device in which the semiconductor element 15 is maintained at a uniform and excellent element performance can be obtained.
[0031]
Also, in particular, in the process described with reference to FIG. 2B, by leaving the material film 21 at the bottom of the groove 5, the amount of the shrink film 9 corresponding to the opening width is provided in the groove 5. For this reason, in the groove-type element isolation 1 in which a larger compressive stress is generated as the opening width is wider, it is possible to provide the contraction film 9 in the groove 5 in an amount corresponding to the magnitude of the compressive stress. It is possible to obtain the groove-type element isolation 1 capable of sufficiently relaxing the compressive stress of the insulating film 7 embedded therein. Moreover, the amount of the shrink film 9 in the groove 5 can be adjusted by the thickness of the material film 1 left at the bottom of the groove 5.
[0032]
In the manufacturing method of the first embodiment, as described with reference to FIG. 2B, the insulating film 7 is subjected to the CMP polishing, and then the annealing process for contracting the material film 21 is performed. However, this annealing process may be performed in any step after forming the insulating film 7 and before forming the semiconductor element 15.
[0033]
<Second embodiment>
FIG. 3 is a cross-sectional view of a main part of the semiconductor device of the second embodiment. The semiconductor device shown in this figure includes a groove type element isolation 31. Where these groove-type element isolations 31 are different from the groove-type element isolation of the first embodiment described with reference to FIG. 1, the contraction film provided for the groove-type element isolation of the first embodiment is used. , A space portion a is provided.
[0034]
That is, these groove-type element isolations 31 are formed in the grooves 5 having the respective opening widths formed in the surface layer of the semiconductor substrate 3 made of, for example, single crystal silicon. The inner walls of these grooves 5 are covered with a thin oxide film (insulating film) not shown here, and the inside thereof is filled with an insulating film 7 using silicon oxide. Further, a space a is provided between the inner wall of the groove 5 and the insulating film 7.
[0035]
The space a is provided at a position along the lower inner wall of the groove 5, and the insulating film 7 is in close contact with the inner wall of the groove 5 above the groove 5. Such a space a is obtained by removing the material film by vaporizing it by heating.
[0036]
The MOS type semiconductor element 15 similar to that of the first embodiment is provided in the active region 11 on the front surface side of the semiconductor substrate 3 separated by the groove type element isolation 31 having such a configuration.
[0037]
In the semiconductor device having such a configuration, the compressive stress of the insulating film 7 filled in the groove 5 is reduced by the space a provided between the insulating film 7 filled in the groove 5 and the inner wall of the groove 5. Is absorbed in the space a. Therefore, it is possible to prevent the semiconductor substrate 3 from being distorted due to the compressive stress of the insulating film 7 being applied to the semiconductor substrate 3. Thereby, similarly to the semiconductor device of the first embodiment, it is possible to maintain the transistor performance of the MOS semiconductor element 15 formed in the active region 11 of the conductor substrate 3.
[0038]
Next, a method of manufacturing the semiconductor device described with reference to FIG. 3 will be described with reference to FIG.
[0039]
First, as shown in FIG. 4A, a groove 5 is formed in a region where a device isolation is to be formed on a semiconductor substrate 3 made of, for example, P-type single-crystal silicon in the same manner as in the first embodiment, and an inner wall is formed. Oxidize.
[0040]
Next, a material film 33 that is vaporized by heating is formed while covering the inner wall of the groove 5. The material film 33 is made of, for example, polyaryl ether, amorphous carbon, parylene, fluororesin, or the like formed by a CVD method. Among them, it is preferable to use a material having a low vaporization temperature. The material film 33 has at least heat resistance to the temperature at which the next insulating film is formed.
[0041]
Thereafter, the material film 33 is etched back by an etching technique using a mixed gas such as N ₂ , NH ₃ , or O _{2 as} an etching gas, and the material film 33 on the surface of the semiconductor substrate 3 is removed. At this time, the material film 33 is left only in the lower portion of the groove 5, and more preferably, the material film 33 is formed only on the lower side wall of the groove 5 in consideration of the adhesion between the insulating film to be formed next and the inner wall of the groove 5. Leave.
[0042]
After that, as shown in FIG. 4B, the insulating film 7 is formed above the semiconductor substrate 3 so as to fill the trench 5 with the material film 33 interposed therebetween, as in the first embodiment. Then, the insulating film 7 is removed from the surface of the semiconductor substrate 3 by the CMP method.
[0043]
Next, by performing an annealing process using a normal heat treatment furnace, the material film 33 is thermally decomposed and vaporized, and the components of the vaporized material film 33 are removed by passing through the insulating film 7. At this time, as in the first embodiment, the annealing temperature is set in the range of 700 ° C. to 900 ° C. or higher than the decomposition vaporization temperature of the material film 33 component. This annealing treatment is performed in a vacuum atmosphere, or even in the air, by controlling the rate of temperature rise, the vaporized material film component can be removed without affecting the insulating film 7. Adjust so that it can pass through 7. Incidentally, when an oxidizing gas such as oxygen is contained in a vacuum atmosphere or the atmosphere, it is not preferable because the silicon substrate may be oxidized. Can be efficiently vaporized (oxidized), and the processing time can be reduced.
[0044]
As described above, as shown in FIG. 3, the element isolation 31 in which the space portion a in which the material film (33) is removed by vaporization is provided between the insulating film 7 and the inner wall of the groove 5 is formed.
[0045]
After the formation of the element isolation 31, the MOS type semiconductor element 15 is formed by a general method in the active region 11 separated by the element isolation 31.
[0046]
In such a manufacturing method, as described with reference to FIG. 4B, after the insulating film 7 is filled in the groove via the material film 33 formed on the lower inner wall of the groove 5, the material film 33 is heated. Is vaporized and removed. Therefore, a space a from which the material film 33 is removed by heating is formed between the insulating film 7 and the inner wall below the groove 5 irrespective of the shape of the groove 5.
[0047]
Therefore, similarly to the manufacturing method described in the first embodiment, it is possible to form the groove-type element isolation 31 that can relieve the compressive stress of the insulating film 7 embedded therein regardless of the opening width of the groove 5. As a result, it is possible to obtain a semiconductor device in which the semiconductor elements 15 formed in all the active regions 11 are maintained at uniform and excellent element performance.
[0048]
In the manufacturing method according to the second embodiment, in the process described with reference to FIG. 4A, the material film is formed only on the lower side wall of the groove 5 in consideration of the adhesion between the insulating film 7 and the inner wall of the groove 5. It was considered preferable to leave 33. However, if the adhesion between the inner wall of the groove 5 and the insulating film 7 is good, the material film 33 may be left at the bottom of the groove 5. In such a case, the space portion a is also provided at the bottom of the groove 5, and the space portion a having a size corresponding to the opening width of the groove 5 is provided in each groove 5. For this reason, in the groove-type element isolation 31 in which a larger compressive stress is generated as the opening width is larger, it is possible to provide a space portion a having a size corresponding to the magnitude of the compressive stress in the groove 5. The groove-type element isolation 31 capable of sufficiently relaxing the compressive stress of the insulating film 7 embedded in the inside 5 can be obtained. In addition, the size of the space a in the groove 5 can be adjusted by the thickness of the material film 33 left at the bottom of the groove 5.
[0049]
Further, in the manufacturing method according to the second embodiment, as described with reference to FIG. 4B, after the insulating film 7 is subjected to the CMP polishing, an annealing process for vaporizing the material film 33 is performed. However, this annealing process may be performed in any step after forming the insulating film 7 and before forming the semiconductor element 15.
[0050]
【The invention's effect】
As described above, according to the semiconductor device of the present invention, between the inner wall of the groove and the insulating film filled therein, a contraction film to which a tensile stress is applied is provided between the inner wall and the space. By doing so, it is possible to prevent the semiconductor substrate from being distorted due to the compressive stress of the insulating film inside the trench. This makes it possible to suppress a decrease in the electron mobility in the semiconductor substrate and to maintain the performance of the semiconductor element formed on the front surface side of the semiconductor substrate.
According to the method of manufacturing a semiconductor device of the present invention, after filling the insulating film in the groove in which the material film is formed along the inner wall, the material film is contracted by heating or the material film component is vaporized. By removing, it becomes possible to form a contraction film and a space along the inner wall of the groove, irrespective of the shape (opening width) of the groove. As a result, it becomes possible to form a groove-type element isolation capable of relieving the compressive stress of the insulating film buried in the groove of any shape, thereby making it possible to form a uniform and good semiconductor element in all active regions. A semiconductor device which maintains element performance can be obtained.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to a first embodiment.
FIG. 2 is a manufacturing process diagram of the semiconductor device of the first embodiment.
FIG. 3 is a cross-sectional view illustrating a configuration of a semiconductor device according to a second embodiment.
FIG. 4 is a manufacturing process diagram of the semiconductor device of the second embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Groove, 3 ... Semiconductor substrate, 7 ... Insulating film, 9 ... Shrink film, 21, 33 ... Material film, a ... Space part

Claims (6)

A semiconductor substrate having a groove on the surface side,
An insulating film filled in the groove;
A semiconductor device comprising: a shrink film provided on an inner wall of the groove in a state where a tensile stress is applied between the inner wall of the groove and the insulating film. The semiconductor device according to claim 1,
The semiconductor device, wherein the shrink film is provided on an inner wall of the groove including a bottom of the groove. A semiconductor substrate having a groove for element isolation,
A semiconductor device provided with an insulating film filled in the groove while maintaining a space at a position along a lower inner wall of the groove of the semiconductor substrate. A first step of forming a material film that shrinks by heating along the inner wall of the groove formed on the surface side of the semiconductor substrate;
A second step of burying an insulating film in the groove via the material film;
And a third step of contracting the material film by heating after the second step. The method for manufacturing a semiconductor device according to claim 4,
The method for manufacturing a semiconductor device according to claim 1, wherein the material film is made of porous silica, hydrosilixisoxane, or methylsilixioxane. A first step of forming a material film that is vaporized by heating while covering the inner wall of the groove formed on the front surface side of the semiconductor substrate, etching back the material film, and leaving the material film only on the inner wall below the groove; ,
A second step of burying an insulating film in the groove via the material film left in the groove;
After the second step, a third step of removing the material film component vaporized by heating from the inside of the groove through the insulating film to form a space at a position along an inner wall below the groove. A method of manufacturing a semiconductor device.

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