JP2004335873A - Pattern formation method - Google Patents

Abstract

An object of the present invention is to provide a fine pattern method for forming a pattern in a photolithography technique and using the mask as a mask to accurately process a lower layer material.
A resist is patterned on a layer to be processed on a semiconductor substrate to form a first pattern layer. After forming the resist pattern, the first pattern layer 14a is reduced in size by an additional process. Next, a buried film 15 is formed between the first pattern layers 14a using a material having relatively high etching resistance, and after performing a flattening process, the first pattern layers 14a are removed. Thereby, the second pattern layer 15a remains. Using this second pattern layer, the underlying layer to be processed 13 is etched. Further, for example, the Al film 12 is etched using the underlying processing layer 13 as a mask.
[Selection] Figure 2

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a pattern forming method in an optical lithography technique used for manufacturing a semiconductor device.
[0002]
[Prior art]
2. Description of the Related Art A fine pattern forming technology plays a central role in a semiconductor device manufacturing technology in which miniaturization progresses. Also in the fine pattern forming technology, the light lithography technology using light has been miniaturized and the wavelength of the light source has been shortened, and the technology of 0.1 μm level has already been put into practical use. Furthermore, lithography techniques using X-rays, electron beams and the like have been pursued as a method of breaking through the limit of light in order to advance miniaturization, but there are many problems such as technical difficulties and suitability for mass production. For this reason, in the photolithography technology, a method of forming a fine pattern exceeding the resolution limit by wavelength has been developed. As one of the methods, a method called slimming has been proposed in which a resist for forming a pattern is subjected to additional processing after exposure and development.
[0003]
In this method, for example, a resist pattern formed by a photolithography technique is further reduced to, for example, a thinner shape by performing etching or the like, and using the mask as a mask, the material thereunder is patterned by dry etching or the like. When a narrow space or a hole is required between the patterns, a method of making the formed resist pattern larger, for example, thicker, is adopted. For example, Patent Literature 1 discloses a method capable of both reducing and increasing the size of a resist pattern by using an electron beam and changing the irradiation conditions of the electron beam on the resist pattern after development. I have.
[0004]
[Patent Document 1]
JP-A-2002-217170 (page 6, FIG. 1)
[0005]
[Problems to be solved by the invention]
By using the additional processing such as the slimming technique described above, a fine pattern forming method and the like obtained in the photolithography technique can be realized. However, this method has the following problems. That is, when dry-etching the lower layer material using the resist as a mask, the resist must have etching resistance. However, when the above-described additional processing such as slimming is performed, the thickness of the remaining resist pattern also decreases. Therefore, phenomena such as the processed lower layer material deviating from a desired size or shape are likely to occur. If the thickness of the resist is increased in order to avoid this, a phenomenon such as a fall of the resist or a reduction in the processing accuracy of the resist dimensions and shapes due to development during patterning of the resist and subsequent dry etching is observed.
[0006]
The present invention has been made in view of such circumstances, and an object thereof is to perform an additional process after forming a resist pattern in an optical lithography technique, form a fine pattern, and use the pattern to accurately determine the material of the lower layer. An object of the present invention is to provide a pattern forming method that can be processed well.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a step of forming a layer to be processed on a semiconductor substrate, a step of forming a resist layer on the layer to be processed, Forming a patterning layer, adding the semiconductor substrate on which the first patterning layer is formed, and embedding a second patterning layer in a gap between patterns in the first patterning layer, Patterning the layer to be processed using the second patterning layer as a mask.
[0008]
According to the present invention, in a photolithography technique, after forming a resist pattern and performing an additional process, the pattern is inverted, a pattern having etching resistance is formed, and the lower layer material is formed by using the pattern as a mask. It is possible to provide a pattern forming method for processing with high accuracy.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0010]
(First Embodiment)
1A to 3H are cross-sectional views showing a first embodiment of the present invention in the order of steps.
[0011]
First, a P-type silicon substrate 10 is prepared as a semiconductor substrate, and a silicon oxide film 11 having a thickness of about 200 nm is formed thereon by a CVD method. Subsequently, an Al film 12, which is a metal for wiring, is formed on the silicon oxide film 11 to a thickness of about 500 nm by a sputtering method. Further, a polyacenaphthylene-based material having a thickness of about 300 nm is formed on the Al film 12 by using a spin coating method as the layer to be processed 13 which is an etching mask of the Al film 12.
[0012]
Further, a resist film 14 for a positive type DUV is formed as a photosensitive agent for ArF laser light by using a spin coating method on the processing target layer 13 to a thickness of about 100 nm, and then at 100 to 200 ° C. for about 1 to 2 minutes. Perform a baking process.
[0013]
Next, the silicon substrate 10 coated with the resist layer 14 is set in an ArF excimer laser exposure apparatus, and after performing positioning and the like, the resist layer 14 on the silicon substrate 10 is irradiated with ArF laser light for a certain period of time through a mask. . Subsequently, a first patterning layer 14a is formed on the silicon substrate 10, as shown in FIG. 1B, by performing a baking process and a developing process at 100 to 200 ° C. for about 1 to 2 minutes. The dimensions at this time are, for example, 0.11 μm for both line and space widths.
[0014]
Next, as shown in FIG. 1C, the surface of the silicon substrate 10 on which the first patterning layer 14a is formed is treated with about 10 ppm of ozone water to reduce the size of the pattern. At this time, the width of the line is reduced to 0.05 μm.
[0015]
Further, on the first patterning layer 14a formed on the silicon substrate 10, as shown in FIG. 2D, a water-soluble silicone as the buried film 15 is formed to a thickness of about 300 nm by spin coating. Subsequently, as shown in FIG. 2E, a recess process is performed by a CMP method so that the water-soluble silicone of the second patterning layer 15a remains only in the concave portions existing between the first patterning layers 14a. . Of course, it is also possible to terminate the processing by the CMP method before the upper portion of the first patterning layer 14a is exposed, and to process the remaining water-soluble silicone by dry etching.
[0016]
Next, as shown in FIG. 2F, a treatment with a solvent is performed so as to remove the first patterning layer 14a while leaving the second patterning layer 15 embedded therein. As another method, the first patterning layer 14a can be collectively removed in the subsequent etching of the layer to be processed.
[0017]
Through the above steps, the basic pattern formation is completed, and then the pattern is transferred to the lower layer film using the patterned second patterning layer 15a. First, the lower layer to be processed 13 is etched by a dry etching method, and pattern transfer is performed as shown in FIG. Next, the Al film 12 is etched by a dry etching method using the layer to be processed 13 as a mask, and pattern transfer is further performed as shown in FIG. As described above, an Al wiring layer having a narrow space interval width is formed.
[0018]
In this embodiment, an example in which a silicon oxide film is formed on a silicon substrate and then an Al wiring layer is formed thereon has been described. However, in the process of manufacturing a semiconductor device such as an LSI, a transistor and a capacitor are formed on a silicon substrate. Is formed, a silicon oxide film is formed thereon as an interlayer insulating film, and further, an Al wiring layer is formed. Of course, the present method can be applied to these.
[0019]
According to this embodiment, the dimensions of the pattern formed by the photolithography method are reduced by the ozone water treatment method, which is a chemical treatment, and further, the step of inverting the pattern is performed to increase the etching resistance and to reduce the size. A highly accurate space pattern can be formed.
[0020]
Further, the surface of the substrate is treated by the ozone water treatment method, and the adhesion between the buried film and the base can be further improved. As a result, a recess process in which the embedded film is unlikely to be peeled off or the like can be performed. Further, in the present embodiment, a method using ozone water as the chemical treatment has been exemplified. As another chemical treatment method, the same effect can be obtained by using so-called functional water in which a hydrogen peroxide solution, radical oxygen or the like is dissolved.
[0021]
(Modification of First Embodiment)
This modification is an example in which the basic process is the same as that of the first embodiment, and only the additional processing is changed. The steps up to the formation of the first patterning layer shown in FIGS. 1A and 1B are the same as those of the first embodiment.
[0022]
Next, as shown in FIG. 1C, the dimensions of the first patterning layer 14a are reduced by dry etching using a mixed gas of CF ₄ , HBr, and O ₂ . At this time, the width of the line is reduced to 0.05 μm. Subsequently, the surface of the silicon substrate 10 on which the narrowed first patterning layer 14a is formed is treated with a silane coupling agent. This process is for improving the adhesion to the base when the buried film is formed in the next step.
[0023]
The subsequent steps of forming a buried film are the same as those shown in FIGS. 2D to 3H shown in the first embodiment.
[0024]
According to this modification, the dimensions of the pattern formed by the optical lithography method are reduced by dry etching, and furthermore, the step of inverting the pattern is performed to improve the etching resistance, and the fine and highly accurate space is provided. A pattern can be formed.
[0025]
In addition, by performing surface treatment by a silane coupling agent treatment method that enhances adhesion by a coupling effect, the adhesion between the base material, which is an inorganic material, and the buried film, which is an organic material, can be improved. As a result, a recess process in which the embedded film is unlikely to be peeled off or the like can be performed.
[0026]
Further, as the above-described surface treatment method, a photocatalyst is used in which water in which a metal oxide such as titanium dioxide, zinc oxide or tungsten trioxide is dispersed is applied to the surface of a silicon substrate, and the surface is irradiated with light to activate the underlying surface. The same treatment can be performed by using water treatment.
[0027]
(Second embodiment)
4 and 5 are plan views showing a second embodiment of the present invention in the order of steps.
[0028]
In the first embodiment, an ozone water treatment method, which is a chemical treatment, is used as a method of thinning the first patterning layer. In the present embodiment, an example in which an argon ion laser beam is used as an energy beam will be described. In this embodiment, a laser beam irradiation step is used instead of the ozone water treatment step in FIG. 1C in the first embodiment, and all other steps are the same as those in the first embodiment. Therefore, detailed description is omitted.
[0029]
Steps before the P-type silicon substrate 10 shown in FIG. 4A is prepared and the pattern is narrowed are the same as the steps of FIGS. 1A and 1B shown in the first embodiment. It is. FIG. 4A is a plan view of the silicon substrate 10 in which the first patterning layer 14a is formed on the layer 13 to be processed. As shown in FIG. 4B, a laser beam 16 shaped by an optical system (not shown) is scanned on the silicon substrate 10 in an arrow direction so as to overlap the first patterning layer 14a. As a result, the first patterning layer 14a in the laser beam scanning area 16a reacts with oxygen in the atmosphere and is oxidized by the heat treatment, and the pattern size is reduced.
[0030]
The laser beam is linearly scanned, for example, from the end of the silicon substrate to the end on the opposite side, and then, as shown in FIG. Then, the laser beam 16 is scanned in the same direction as the previous laser beam scanning area 16a. In this manner, the laser beam is sequentially irradiated, and the width of the first patterning layer 14a is similarly reduced over the entire surface of the wafer (not shown). At this time, by omitting laser irradiation in a part of the region where the first patterning layer 14a does not exist, the process can be shortened.
[0031]
Steps after the dimensions of the first patterning layer 14a shown in FIG. 4B are reduced are the same as the steps of FIGS. 2D to 3H shown in the first embodiment. FIG. 5 shows a plan view of the silicon substrate after the Al film 12 formed on the silicon oxide film 11 is patterned. As in the first embodiment, an Al wiring layer having a narrow space interval width is formed. Further, similarly to the first embodiment, the processing by the CMP method may be completed before the upper portion of the first patterning layer 14a is exposed, and the remaining water-soluble silicone may be processed by dry etching.
[0032]
According to the present embodiment, the dimension of the pattern formed by the photolithography method is reduced by the energy beam irradiation method, and further, the step of inverting the pattern is performed, so that the etching resistance is improved, and the precision of miniaturization is improved. It is possible to form a space pattern having a high height. Further, according to the present embodiment, it is possible to perform laser irradiation only on the region where the resist mask is formed without irradiating the entire surface of the silicon substrate with laser, and thus it is possible to increase efficiency in a manufacturing process.
[0033]
As a laser beam, any of an excimer laser, a carbon dioxide gas laser, a neodymium yag laser, and the like may be used other than the argon ion laser. Further, as the energy beam, an electron beam, an X-ray beam, or the like may be used instead of the laser beam.
[0034]
(Third embodiment)
FIGS. 6A to 8H are sectional views showing a third embodiment of the present invention in the order of steps.
[0035]
First, as shown in FIG. 6A, a P-type silicon substrate 20 is prepared as a semiconductor substrate, and a silicon oxide film 21 is formed thereon with a thickness of about 200 nm by a CVD method. Subsequently, a polycrystalline silicon film 22 for a gate electrode is formed on the silicon oxide film 21 to a thickness of about 500 nm by a CVD method. Further, a novolak-based material having a thickness of about 300 nm is formed on the polycrystalline silicon film 22 by a spin coating method as a layer to be processed 23 which is an etching mask of the polycrystalline silicon film 22.
[0036]
Furthermore, after forming a resist layer 24 for positive type DUV as a photosensitive agent to the KrF laser beam by using a spin coating method on the processing target layer 23 to a film thickness of about 300 nm, a temperature of 100 to 200 ° C. and about 1 to 2 minutes is applied. Perform a baking process.
[0037]
Next, the silicon substrate 20 coated with the resist layer 24 is set in a KrF excimer laser exposure apparatus, and after performing alignment and the like, the resist layer 24 on the silicon substrate 20 is irradiated with KrF laser light for a certain period of time through a mask. I do. Subsequently, a first patterning layer 24a is formed on the silicon substrate 20, as shown in FIG. 6B, by performing a baking process and a development process at 100 to 200 ° C. for about 1 to 2 minutes. The dimensions at this time are, for example, 0.11 μm for both line and space widths.
[0038]
Next, as shown in FIG. 6C, the first patterning layer 24a is heated at a temperature of 100 ° C. to 200 ° C. for 1 to 2 minutes to soften and fluidize the first patterning layer 24a. Thus, the pattern size is increased. Thereby, the width of the space was reduced to 0.06 μm.
[0039]
Further, on the first patterning layer 24a formed on the silicon substrate 20, as shown in FIG. 7D, a water-soluble silicone as the buried film 25 is formed to a thickness of about 300 nm by a spin coating method. Subsequently, as shown in FIG. 7E, a recess process is performed by dry etching so that the water-soluble silicon remains only in the concave portions between the first patterning layers 24a, thereby forming the second patterning layer 25a. I do. Next, as shown in FIG. 7F, a treatment with a solvent is performed so as to remove the first patterning layer 24a while leaving the buried second patterning layer 25a. As another method, the first patterning layer 24a can be collectively removed in the subsequent etching of the layer to be processed.
[0040]
Through the above steps, the basic pattern formation is completed, and then the pattern is transferred to the underlying film using the patterned second patterning layer 25a. First, the lower layer to be processed 23 is etched by a dry etching method, and pattern transfer is performed as shown in FIG. Next, as shown in FIG. 8H, pattern transfer is further performed on the polycrystalline silicon film 22 by dry etching using the layer to be processed 23 as a mask. As described above, the polycrystalline silicon film 22 having a narrow line width is formed and can be used as a gate electrode and the like.
[0041]
In this embodiment, an example is described in which a polycrystalline silicon film is formed on a silicon oxide film on a silicon substrate. However, in a semiconductor device such as an LSI, a gate oxide film or the like is formed on a silicon substrate and a gate oxide film or the like is formed thereon. A method of forming a polycrystalline silicon film as a gate electrode is employed. Of course, the present method can be applied to these.
[0042]
According to the present embodiment, the pattern formed by the photolithography method is enlarged by heat treatment, and furthermore, the etching resistance is increased by performing a step of inverting the pattern, and the fine pattern with high precision that has been miniaturized. The formation becomes possible.
[0043]
(Fourth embodiment)
9 and 10 are plan views showing a fourth embodiment of the present invention in the order of steps.
[0044]
In the third embodiment, a relatively low-temperature heat treatment is used as a method for enlarging the first patterning layer. In this embodiment, an example in which an electron beam is used as an energy beam will be described. In this embodiment, an electron beam irradiation step is used instead of the heat treatment step in FIG. 6C in the third embodiment, and the other steps are the same as those in the third embodiment. Description is omitted.
[0045]
The steps from the preparation of the P-type silicon substrate 20 shown in FIG. 9A to the step before enlarging the pattern are the same as the steps shown in FIGS. 6A and 6B shown in the third embodiment. is there. FIG. 9A is a plan view of the silicon substrate 20 in which the first pattern layer 24a is formed on the layer 23 to be processed. As shown in FIG. 9B, the silicon substrate 20 is irradiated with an electron beam 26 shaped by an electron optical system (not shown) so as to overlap the portion where the processing target layer 23 is exposed. At this time, a pulse oscillation type electron beam 26 is used, and while the electron beam 26 and the silicon substrate 20 are relatively moved, processing is performed mainly on the region where the first pattern layer 24a to be subjected to the heat treatment exists. Since the first pattern layer 24a in the region irradiated with the electron beam expands due to softening and fluidization, the width of the space is reduced to 0.06 μm.
[0046]
The steps after the enlargement of the first pattern layer 24a shown in FIG. 9B are basically the same as the steps shown in the third embodiment. Here, a silicon oxide film having a thickness of about 250 nm is formed as a buried film by a spin coating method. After the application of the silicon oxide film, the process is the same as the process of FIGS. 7 (e) to 8 (h). FIG. 10 shows the silicon substrate 20 after the polycrystalline silicon film 22 formed on the silicon oxide film 21 is patterned. As in the third embodiment, a polycrystalline silicon film 22 with a narrow line width is formed.
[0047]
According to the present embodiment, the pattern formed by the photolithography method is enlarged by the energy beam irradiation method, and further, the step of inverting the pattern is performed, and the etching resistance is increased, so that the precision of miniaturization is improved. A high line pattern can be formed. Further, according to the present embodiment, it is possible to irradiate the entire area of the silicon substrate with the electron beam without irradiating the entire surface of the silicon substrate with the electron beam, thereby performing the processing efficiently.
[0048]
As an energy beam, a laser beam, an X-ray beam, or the like may be used instead of the electron beam. Further, as a laser beam, any of an excimer laser, a carbon dioxide laser, a neodymium yag laser, and the like may be used other than the argon ion laser.
[0049]
The present invention is not limited to the above-described embodiment at all, and can be implemented with various modifications without departing from the gist of the present invention. For example, it can be used at any stage in pattern formation in the manufacturing process of a semiconductor device.
[0050]
Reducing the size of the patterning layer also includes, for example, reducing the dimensions of the line pattern. Increasing the size of the patterning layer includes, for example, increasing the size of the line pattern. For example, a thin film to be patterned using an inversion mask is not limited to Al and polycrystalline silicon, and is used in semiconductor devices. It can be applied to any of metals, semiconductors and insulating films. In addition, it is a very effective technique as one of the methods of forming a fine pattern exceeding the resolution limit by wavelength in the photolithography technology, and it can be used even when the resolution limit is not exceeded. is there.
[0051]
In addition, ozone water treatment, silane coupling agent treatment, photocatalytic water treatment, and the like, which are chemical treatments, do not require pattern slimming treatment, etc. Can be used as an additional treatment for improving the adhesion of the slab.
[0052]
【The invention's effect】
According to the present invention, an additional process is performed after a pattern is formed, and further, a step of inverting the pattern is performed, and then the lower layer material is patterned using a mask having improved etching resistance, so that an accurate pattern is formed. It is possible to provide a forming method.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 2 is a sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 3 is a sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 4 is a plan view showing a second embodiment of the method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 5 is a plan view showing a second embodiment of the method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 6 is a sectional view showing a third embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 7 is a sectional view showing a third embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 8 is a sectional view showing a third embodiment of the method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 9 is a plan view showing a fourth embodiment of the method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 10 is a plan view showing a fourth embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
[Explanation of symbols]
10, 20 Silicon substrate 11, 21 Silicon oxide film 12 Al film 13, 23 Processed layer 14, 24 Resist layer 14a, 24a First patterning layer 15, 25 Embedded film 15a, 25a Second patterning layer 16 Laser beam 16a Laser beam scanning area 22 Polycrystalline silicon film 26 Laser beam irradiation area

Claims (7)

Forming a layer to be processed on the semiconductor substrate;
Forming a resist layer on the layer to be processed,
Patterning the resist layer to form a first patterned layer;
Performing an additional treatment on the semiconductor substrate on which the first patterning layer is formed;
Embedding a second patterning layer in a gap between patterns in the first patterning layer;
Patterning the layer to be processed using the second patterning layer as a mask. The pattern forming method according to claim 1, wherein the additional processing includes at least one of dry etching processing, heat treatment, chemical processing, and energy beam irradiation processing. The method according to claim 1, wherein the additional process includes a dry etching process, and the dry etching process is performed in an atmosphere including at least one of CF ₄ , HBr, and O ₂ gases. The pattern forming method according to the above. The additional treatment includes a chemical treatment, and the chemical treatment includes at least one of an ozone water treatment, a hydrogen peroxide solution treatment, a silane coupling agent treatment, and a photocatalytic water treatment. Item 4. The pattern forming method according to Item 1. The method according to claim 1, wherein the additional process includes an energy beam irradiation process, and the energy beam irradiation process is at least one of an electron beam irradiation, a laser beam irradiation, and an ultraviolet light irradiation. 2. The pattern forming method according to 1. 6. The pattern forming method according to claim 5, wherein in the step of the energy beam irradiation treatment, at least a partial region of the semiconductor substrate including the first patterning layer is irradiated. 7. The pattern forming method according to claim 1, further comprising a step of patterning a material formed thereunder using the patterned layer to be processed as a mask. .

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