JP2004335697A - Junction type field effect transistor, method of manufacturing the same, and semiconductor device - Google Patents

Abstract

An object of the present invention is to provide a JFET that hardly generates electric field concentration and improves withstand voltage performance, a method of manufacturing the same, and a semiconductor device.
A first conductivity type source region, a first conductivity type channel layer, and a gate layer positioned in contact with the channel layer are provided. And a channel limiting layer 5 of the second conductivity type, which is located between the channel layer and the channel layer, and has a predetermined impurity concentration of the second conductivity type. And a lower channel limiting layer 5b having a second conductivity type impurity concentration lower than a predetermined second conductivity type impurity concentration.
[Selection diagram] Fig. 1

Description

【００５０】
表１によれば、Ｂを注入する際は加速電圧をＡｌの注入の際よりも高め、深い位置まで到達するようにする。ＢはＡｌに比べて小さい元素であるので、上記の高い加速電圧に加速されてＡｌよりも深い位置に届きやすい。図６は、ＡｌおよびＢを合わせたｐ型不純物濃度の深さ方向分布を示す図である。図６の表面からの距離の小さい左側の高い不純物濃度分布は、上部チャネル限定層５ａに対応する層であり、深い位置の不純物濃度分布は下部チャネル限定層５ｂに対応している。いずれのチャネル限定層もすそを引いていることが分る。
【００５１】
上記のようなすその広がりは横方向にも生じる。すなわち、不純物濃度分布は、また横方向にもすそを引き、広がるので、マスク４１の幅Ｄｎの場合、ｎ型通路はそれより狭い間隔となる。このイオン注入の際におけるイオン種の横方向への広がりのために狭くされ、最終的に形成された通路の間隔を実効間隔Ｄｅと呼ぶ。
【００５２】
表１の注入条件で注入したとき、図５に示すように、上部チャネル限定層５ａはαだけマスク端部からマスクの下へと内側に広がり、また、下部チャネル限定層５ｂはさらにそれから内側に０．２μｍだけ広がる。このため、マスクの幅Ｄｎと実効間隔Ｄｅとの間には、Ｄｎ＝Ｄｅ＋２×０．２＋２α（単位：μｍ）の関係が成り立つ。実効間隔Ｄｅは４μｍ以下とするのがよく、より望ましくは２μｍ以下とするのがよい。
【００５３】
上記のように、チャネル限定層を２層構造にして、下部チャネル限定層の不純物濃度を低くすることにより、電界集中を抑制して耐圧性能を向上させることができる。電界集中を緩和する具体例については、実施例において説明する。
【００５４】
（実施の形態２）
本発明の実施の形態２では、実施の形態１で説明したＪＦＥＴ１０が、１つのＳｉＣ基板に複数個、配置された半導体装置５０について説明する。図７は本実施の形態における半導体装置の平面図である。ＪＦＥＴ１０は必ずしも規則正しく周期的に配列されていなくてもよい。図８は図７におけるＶＩＩＩ−ＶＩＩＩ線に沿う断面図である（耐圧基本構造）。半導体装置の端面は、図８に示すように平滑ではなく不完全性を有している可能性がある。この不完全性としては、たとえば、端面における凹凸の可能性を挙げることができる。この凹凸は、半導体基板の切断にともなって生じる可能性があるもので、実質上平滑とみなせる場合もあるが、そうでない場合もある。
【００５５】
図８は耐圧基本構造のみを示しているが、チャネル限定層の右側上方にはソース領域が位置しており、このソース領域とドレイン電極との間に電圧が印加される。ソース／ドレイン間に高電圧を印加したとき、半導体装置の端部において、何らかの不完全点を起点として絶縁破壊が生じ、アバランシェ電流の経路が形成されやすい。これを防止するため、ＳｉＣ基板の上に形成されたＳｉＣ層の端面５０ｂを含む端部にｐ型不純物領域、すなわち端縁領域５０ｓを配置する。この端縁領域５０ｓの配置により、端面の凹凸を起点とする絶縁破壊を抑制することができる。この端縁領域は、ＳｉＣ基板より上のＳｉＣ層に形成されるが、ＳｉＣ基板まで延びていてもよい。
【００５６】
また、下部チャネル限定層を基板の端面側に延在させて、端面５０ｂとＪＦＥＴとの間において、ｎ−型ＳｉＣ層３をその表層部に配置させないようにする。このような下部チャネル限定層の外側への延在によるｐ−型ＳｉＣ層の周囲領域５ｅの配置によっても、複数のＪＦＥＴのうちの外側の端に位置するソース領域からドレインに至る部分の絶縁破壊を防止することができる。図８に示すこの周囲領域５ｅの幅Ｄｂは、３μｍ以上がよく、さらに望ましくは５μｍ以上がよく、より一層確実性を追求するために望ましくは１０μｍ以上とする。
【００５７】
上記の説明において、ＳｉＣ基板というとき、ＳｉＣ基板１のみならず、その上に形成されるＳｉＣ層を含み、さらに、耐圧基本構造だけでなくその上のＳｉＣ層を含むものとする。ＳｉＣ基板の端面５０ｂも、ＳｉＣ基板１から上方のＳｉＣ層まで含む層の端面を指すこととする。端縁領域５０ｓも、耐圧基本構造のＳｉＣ層の端面にのみ形成されておらず、その上のソース領域が形成される層を含むＳｉＣ層の端部に形成される。
【００５８】
（実施の形態３）
本発明の実施の形態３では、半導体基板に形成される半導体装置の種類は問わず、その端部に端縁領域または周囲領域を配置した点に特徴がある。１つの半導体基板に形成される半導体装置は単複は問わず、またトランジスタでもよいしダイオードでもよい。図９は、上述の半導体装置６０を示す平面図である。四周を半導体基板の端面６０ｂで囲まれている。この半導体基板の端面というときの範囲は、上述のように端面５０ｂと同様に半導体層も含むように広く解釈する。
【００５９】
図１０および図１１は、図９に示す半導体装置の端部を含む断面図である。図１０では、電流ｉが半導体基板に向って縦方向に流れる部分３を有する半導体装置の端部に端縁領域６０ｓが設けられている。この端縁領域が耐圧性能を高める理由は、実施の形態２における端縁領域５０ｓと同様である。
【００６０】
図１１は、実施の形態２におけるチャネル限定層の有無に関わらず、電流が縦方向に流れる部分３を有する半導体装置が形成されている半導体基板の端部に、その半導体装置を囲むように、ｐ−型の周囲領域２６を配置する。この周囲領域を配置する理由は、上述のとおり、外側の端の表層部に位置する電極と、この電極に対向する電極が配置された半導体基板との間の部分の絶縁破壊を防止するためである。このｐ−型の周囲領域２６の幅Ｄｇは、半導体がＳｉＣである場合は、３μｍ以上あればよいが、より望ましくは５μｍ以上あるのがよく、さらに一層確実性を追求するために望ましくは１０μｍ以上あるのが望ましい。
【００６１】
【実施例】
次に、上述の半導体装置やＪＦＥＴについて各層および各領域に所定の不純物濃度を形成して、電界分布および電位分布をシミュレーション計算した結果について説明する。
【００６２】
（実施例１）
図１２に本発明の実施例１のＪＦＥＴの断面図（耐圧基本構造）を示す。このＪＦＥＴにおいて、耐圧性能に及ぼす実効間隔Ｄｅの影響を調べた。全幅は１０μｍ一定である。上部チャネル限定層５ａおよび下部チャネル限定層５ｂの不純物濃度は、それぞれ１×１０^１８／ｃｍ^３および１×１０^１７／ｃｍ^３である。このＪＦＥＴでは、ドリフト層を３ａおよび３ｂの２層にして下層３ｂを高濃度層とし、上層３ａを低濃度層としている。ここには詳しく説明しないが、別の調査において、ドリフト層を２層構造にすることのメリットはそれほど大きくないことを確認している。したがって、ドリフト層３ａ一層で構成した場合、本実施例と同様の結果を得ることができる。
【００６３】
図１３に実効間隔を３．２μｍ〜０．４μｍの範囲に変化させた場合のドレイン電圧と、最大電界強度との関係を示す。経験上、最大電界強度が２．３×１０^６Ｖ／ｃｍ以上で絶縁破壊が生じるので、その電界強度を絶縁破壊の基準としている。図１３によれば、実効間隔が２．０μｍの試験体Ｃ７において、ドレイン電圧が１０００Ｖを超えても最大電界強度が２．３×１０^６Ｖ／ｃｍ未満となっている。また、実効間隔がそれ以下の試験体Ｃ３〜Ｃ６においては、Ｃ７よりもさらに優れた耐圧性能を示している。
【００６４】
図１４は、ドレイン／ゲート間電圧５００Ｖおよび１０００Ｖの場合について、最大電界強度に及ぼす実効間隔の影響を示す。ドレイン／ゲート間電圧が５００Ｖの場合、最大電界強度が２．３×１０^６Ｖ／ｃｍ以上になることはないが、ドレイン／ゲート間電圧が１０００Ｖになると実効間隔Ｄｅが２μｍを超えると最大電界強度が２．３×１０^６Ｖ／ｃｍ以上になる。これらより、たとえば耐圧１０００Ｖを得たい場合には、実効間隔を２．０μｍ以下とすればよいことが分る。
【００６５】
図１５は、図１２に示すＪＦＥＴの実効間隔Ｄｅを２．０μｍとした場合の電界分布を示す図である。計算の便宜上、アノード３１を上端の左右に、カソード３２をＳｉＣ基板底部に配置して、アノード／カソード間に電圧を印加した。図１５によれば、電界強度の最大値はチャネル限定層５ａ，５ｂの端の部分ではなく、少なくともそれより少し間隔を隔てた内側に分布する。これは、チャネル限定層を２層構造にして下部チャネル限定層の不純物濃度を下げたことに起因して電界強度がチャネル限定層において緩和されているからである。すなわち、チャネル限定層の直近の周囲に電界強度１×１０^５Ｖ／ｃｍの等電界強度線があり、その外側に小さいが間隙３０をおいて電界強度１×１０^６Ｖ／ｃｍの等電界強度線が位置している。この間隙３０はチャネル限定層近傍で電界集中が緩和された領域ということができる。したがって、最大電界強度は通路に面するチャネル限定層の端部のコーナー部などに位置することなく、ドリフト層内に位置している。このため、異常に高い電界強度が局所的に形成されることが解消されている。
【００６６】
上記の実施例１から、チャネル限定層を２層構造にして下部チャネル限定層の不純物濃度を低下させることにより、電界緩和がなされることが分った。この電界緩和により、通路に面するチャネル限定層のコーナー部などに接して局所的に異常に大きい電界強度が分布することを解消することができる。また、通路の実効間隔を２．０μｍ以下とすることによりゲート／ドレイン間電圧を１０００Ｖとしたとき、最大電界強度を２．３×１０^６未満とすることができる。上述のように、オフ状態を維持するゲート電圧においては空乏層がチャネル層を遮断している。実効間隔が狭い場合、両側から張り出す空乏層が合体しやすく、ソースやドレインから見て一体的な空乏層が形成されているように見え、最大電界強度の位置は通路に面するチャネル限定層のコーナー部から大きくドリフト層に入った位置になると考えられる。この結果、より一層、上記コーナー部の影響が減じられた電界強度分布になり、最大電界強度が低下する。
【００６７】
（実施例２）
本発明の実施例２では、ＪＦＥＴを配置した半導体装置のＳｉＣ基板の端部に向けて、低不純物濃度の下部チャネル限定層を延在させた周囲領域５ｅの効果について説明する。図１６は、用いた半導体装置の構造を示す図である。図１６に示す半導体装置では、ドリフト層は２層構造であるが、本実施例で調べた４試験体のうち、３体は図１６に示す２層のドリフト層を有するものであるが、１体は１層のドリフト層からなるものとした。
【００６８】
図１７に示すように、周囲領域の幅Ｄｂは９．８μｍ程度あれば、非常に優れた耐圧性能を示すことが分る。また、ドリフト層を単層とするか複層とするかで、最大電界強度は大きな相違はないので、ドリフト層の層数はあまり耐圧性能に影響しないことが分る。また、周囲領域の幅Ｄｂが９．８μｍあれば、最大電界強度は最大でも２．３×１０^６Ｖ／ｃｍに届いていない。
【００６９】
図１８に電界分布を示す。本実施例ではＪＦＥＴは基板の端部に位置するものを問題とするので、アノード３１は図１８に示す位置となる。この電界分布によれば、最大電界強度は上部チャネル限定層のコーナー部に生じている。しかし、図１７において説明したように、チャネル限定層の端部に最大電界強度が生じてもその最大の電界強度は２．３×１０^６Ｖ／ｃｍに達していない。これは、図１８に示すように、周囲領域の幅Ｄｂを１０μｍ程度とることにより、１×１０^６Ｖ／ｃｍの等高線を表層部からドリフト層側に押し下げたためである。この結果、最大電界強度は２．３×１０^６Ｖ／ｃｍを超えるほどの高い値にならない。領域３０は、チャネル限定層近傍で電界集中が緩和された領域ということができる。
【００７０】
上記において、本発明の実施の形態について説明を行ったが、上記に開示された本発明の実施の形態は、あくまで例示であって、本発明の範囲はこれら発明の実施の形態に限定されない。本発明の範囲は、特許請求の範囲の記載によって示され、さらに特許請求の範囲の記載と均等の意味および範囲内でのすべての変更を含むものである。
【００７１】
【発明の効果】
本発明のＪＦＥＴおよび半導体装置は、局所的な電界集中を生じにくいように構成されており、優れた耐圧性能を有する。また、本発明のＪＦＥＴの製造方法は、イオン注入法により容易に２層構造からなるチャネル限定層を形成することができる。
【図面の簡単な説明】
【図１】本発明の実施の形態１におけるＪＦＥＴを示す図である。
【図２】本発明の実施の形態１における別のＪＦＥＴを示す図である。
【図３】本発明の実施の形態１におけるさらに別のＪＦＥＴを示す図である。
【図４】図４（ａ）〜（ｃ）は本発明の実施の形態１における上記以外のＪＦＥＴを示す図であり、（ａ）は平面図、（ｂ）は（ａ）のＩＶＢ−ＩＶＢ線に沿う断面図、（ｃ）は（ａ）のＩＶＣ−ＩＶＣ線に沿う断面図である。
【図５】図１のＪＦＥＴの製造においてチャネル限定層にイオン注入を行なった断面図である。
【図６】図５のイオン注入後の不純物濃度の深さ分布を示す図である。
【図７】本発明の実施の形態２における半導体装置を示す図である。
【図８】図７のＶＩＩＩ−ＶＩＩＩ線に沿う断面図である。
【図９】本発明の実施の形態３における半導体装置を示す図である。
【図１０】図９の半導体装置の半導体基板の端部における断面図である。
【図１１】本発明の実施の形態３における別の半導体装置の半導体基板端部における断面図である。
【図１２】本発明の実施例１におけるＪＦＥＴである。
【図１３】ドレイン電圧と最大電界強度との関係を示す図である。
【図１４】実効間隔Ｄｅと最大電界強度との関係を示す図である。
【図１５】実効間隔２．０μｍの場合の電界分布を示す図である。
【図１６】本発明の実施例２における半導体装置である。
【図１７】各周囲領域の幅ごとに、ドレイン電圧と最大電界強度との関係を示す図である。
【図１８】周囲領域の幅９．８μｍの場合の電界分布を示す図である。
【符号の説明】
１ ＳｉＣ基板、３，３ａ，３ｂ ドリフト層、４ 通路、５ チャネル限定層、５ａ 上部チャネル限定層、５ｂ 下部チャネル限定層、５ｅ 半導体装置の端部に延在する下部チャネル限定層、６ チャネル層、７，７ａ，７ｂ ゲート領域、７ｃ ｐ＋型領域（接続領域）、８ ドレイン領域、９ 絶縁層、１０ＪＦＥＴ、１８ ｐ＋型コンタクト、２６ 周囲領域、３０，４０ チャネル限定層近傍の緩和された電界領域、３１ シミュレーション計算上の正極、３２シミュレーション計算上の負極、５０，６０ 半導体装置、５０ｂ，６０ｂ 半導体装置の端面、Ｄｂ 基板端面、Ｄｅ 実効間隔、Ｄｇ 周囲領域の幅、Ｄ ドレイン、Ｇ ゲート、Ｓ ソース。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a junction field-effect transistor, a method of manufacturing the same, and a semiconductor device, and more specifically, to a junction field-effect transistor (JFET: Joint Field Effect Transistor) with improved withstand voltage performance, a method of manufacturing the same, and a semiconductor device. It is.
[0002]
[Prior art]
Silicon carbide (SiC) is a semiconductor having excellent characteristics such as a higher breakdown electric field strength and a higher saturated electron velocity than silicon (Si). For this reason, application to a power transistor, such as using a field effect transistor using SiC for a power switching device, has been attempted. Even when SiC is used for the semiconductor, it is still a major problem in the power transistor to improve the breakdown voltage performance.
[0003]
For this reason, in an electrostatic induction transistor using a 4H-SiC substrate, a proposal has been made to improve the blocking characteristics by shortening the gate interval and improve the withstand voltage performance of the device (Non-Patent Document 1).
[0004]
Further, in a JFET using a 4H-SiC substrate, a proposal has been made to make a buried diffusion layer, that is, a channel limitation layer facing a gate region into a two-layer structure (Non-Patent Document 2). In this proposal, the high-concentration layer of the two layers is used as the lower layer, the end is made longer, the upper low-concentration layer is made shorter, and a step is provided between the two layers to improve the breakdown voltage performance of the device.
[0005]
[Non-patent document 1]
T. Iwasaki, T .; Ono, Y .; Sugawara and T.S. Yatsuo; Material Science Forum Vols. 264-268, pp108-1088, "Electrical Characteristics of a Novel Gate Structure" 4-H SiC Power Static Induction Transistor "
[0006]
[Non-patent document 2]
P. Friedrichs, H.C. See Milehner, R.A. Schhorner, R .; Kaltschmidt, K .; O. Dohnke and D, Stephani; SiCED GmbH and Co. KG, a Siemens Company and Siemens AG, MEDSPE, "Influence of the buried p-layer on the blocking behavior of vertical JFETs in 4H-SiC.
[0007]
[Problems to be solved by the invention]
However, even if the above-mentioned improvement is performed, the improvement of the withstand voltage performance is often not as designed. For example, even if the device structure such as the impurity concentration and the size of the impurity region is designed so that the breakdown voltage performance of the device is 1 kV, the breakdown voltage performance of the actually obtained device is lower than the target. It is considered that the reason is that the electric field strength locally increases at the end portion of the impurity diffusion layer and the like, causing the breakdown voltage to deteriorate.
[0008]
In particular, when the current path is a direction along the surface of the semiconductor substrate (lateral direction) at the channel portion and a direction (vertical direction) crossing the surface of the semiconductor substrate at the drift layer after passing through the channel portion, Tends to cause electric field concentration at a portion where the width changes from horizontal to vertical. For this reason, even when the breakdown voltage of the device is less than half the design value, a semiconductor device in which local electric field concentration hardly occurs has been desired.
[0009]
SUMMARY OF THE INVENTION An object of the present invention is to provide a JFET in which local electric field concentration is unlikely to occur and improve withstand voltage performance, a method of manufacturing the same, and a semiconductor device.
[0010]
[Means for Solving the Problems]
The JFET of the present invention is a transistor including a semiconductor substrate of a first conductivity type and a semiconductor layer stacked on and in contact with the semiconductor substrate. This JFET has a first conductivity type source region located in a surface layer portion of a stacked semiconductor layer, and a first conductivity type located in contact with the source region and extending from below the source region to below the surface layer portion. The semiconductor device includes a conductive type channel layer and a gate layer located in contact with the channel layer. A first conductive type drift layer which is located in contact with the semiconductor substrate and communicates with the drain region; and a first conductive type which is located between the drift layer and the channel layer from above and below and which communicates with the drift layer from the channel layer. A channel limiting layer of the second conductivity type positioned to surround the channel of the mold. A channel limiting layer positioned below and in contact with the channel layer, an upper channel limiting layer having a predetermined second conductivity type impurity concentration, and a channel in contact with and below the upper channel limiting layer; A lower channel limiting layer having a second conductivity type impurity concentration lower than the conductivity type impurity concentration.
[0011]
With this configuration, it is possible to avoid electric field concentration in a portion of the horizontal channel vertical JFET that enters the drift region from the channel layer. In particular, the electric field concentration at the tip of the channel limiting layer protruding into the drift region can be suppressed in the portion that enters the drift region. This is because the lower channel limitation layer has a lower second conductivity type impurity concentration than the upper channel limitation layer.
[0012]
A gate region may be provided in a surface layer portion above the channel layer, and the gate region may have a structure sandwiching the channel limiting layer and the source region.
With this structure, the channel can be reliably shut off and opened, and the reliability of the semiconductor element can be improved.
[0013]
Further, different from the above structure, a structure in which the above channel limitation layer is used as a gate region to conduct with a gate electrode may be employed.
[0014]
On / off control can be performed even with such a simple structure.
The lower channel limiting layer covers the side of the upper channel limiting layer and extends between the upper channel limiting layer and the first conductivity type passage.
[0015]
With this configuration, local electric field concentration can be prevented more reliably.
[0016]
The channel limiting layer may be electrically connected to the source region. With this configuration, on / off control of the current can be performed only by the depletion layer extending from the gate region to the channel layer and reaching the channel limitation layer. As a result, even if the channel-limited layer has a two-layer structure with different impurity concentrations, the current flowing in the channel layer in the lateral direction can be controlled in the same manner as the single-layer channel-limited layer.
[0017]
At the edge of the semiconductor substrate of the first conductivity type, an edge region of the second conductivity type may be provided at the edge of the semiconductor layer.
[0018]
With this configuration, in the horizontal channel vertical JFET, electric field concentration caused by fine irregularities on the end surface of the semiconductor substrate caused when the semiconductor substrate is cut can be avoided. As a result, in the horizontal channel vertical JFET, it is possible to prevent the withstand voltage performance from deteriorating at the end face of the semiconductor substrate. Since the above-mentioned edge region is provided at the end of the semiconductor substrate, the crossing edge region prevents a decrease in withstand voltage performance even at a corner portion.
[0019]
A plurality of the above JFETs are arranged over the semiconductor substrate. In the JFET located at the edge of the semiconductor substrate, the lower channel limiting layer covers the outer side of the upper channel limiting layer at the edge of the semiconductor substrate. It may extend between the edge and the upper channel limiting layer.
[0020]
With this configuration, it is possible to suppress the occurrence of dielectric breakdown at a portion from the source region located at the outer peripheral end of the JFET to the drain. As a result, it is possible to prevent the withstand voltage performance from deteriorating due to the electric field concentration at the outer peripheral end. The semiconductor layer of the second conductivity type disposed along such an outer periphery is referred to as a peripheral region.
[0021]
The semiconductor substrate and the semiconductor layer may be made of SiC, the main component of the impurity in the lower channel limiting layer may be boron, and the main component of the impurity in the upper channel limiting layer may be aluminum and boron.
[0022]
With this configuration, the channel limiting layer of the SiC semiconductor JFET having excellent withstand voltage performance can be easily formed by self-alignment using ion implantation.
[0023]
The first conductive type passage may have an effective spacing of 4 μm or less.
In the case of a JFET using SiC that secures a withstand voltage of about 1 kV, by setting the effective interval of the passage to 4 μm or less, when a predetermined gate voltage is applied at the time of off to cut off a current, the depletion layer becomes the above-described depletion layer. It is formed so as to easily block the one conductivity type passage. In order to ensure that the depletion layer closes the first conductivity type passage, it is more desirable that the above-mentioned effective distance be 2 μm or less. As a result, it is possible to prevent the adverse effect on the pressure resistance performance of the passage of the first conductivity type from occurring.
[0024]
The above-mentioned effective interval indicates an average diameter when the cross section of the passage is circular, and indicates an interval when the cross section is a gap between straight lines.
[0025]
The width of the lower channel limiting layer extending between the edge of the semiconductor layer and the upper channel limiting layer may be 3 μm or more.
[0026]
In the case of a JFET using SiC that secures a withstand voltage of about 1 kV, by lowering the width of the lower channel limitation layer to 3 μm or more at the end, it is possible to sufficiently prevent deterioration of the withstand voltage performance due to electric field concentration at the end. Can be. More preferably, the thickness is 5 μm or more. In order to surely avoid electric field concentration at the end, the width of the lower channel limiting layer extending between the edge of the semiconductor layer and the upper channel limiting layer is desirably 10 μm or more.
[0027]
A method of manufacturing a JFET according to the present invention includes a semiconductor substrate of a first conductivity type and a semiconductor layer stacked on and in contact with the first conductivity type, and a current flows through a channel layer in a direction along a surface of the semiconductor substrate. A method of manufacturing a transistor that flows through a drift layer in a direction intersecting a surface of a semiconductor substrate. This JFET manufacturing method includes a step of forming a first conductivity type semiconductor layer including a drift layer on a semiconductor substrate, and a step of forming two types of second conductivity type impurity concentrations on the drift layer and below the channel layer. In forming the two layers, ions of different ion species are implanted into the semiconductor layer of the first conductivity type.
[0028]
With this method, the channel limiting layer of the JFET can be easily formed in a self-aligned manner.
[0029]
The semiconductor is SiC, and when forming two layers of the second conductivity type impurity concentration, first, boron is ion-implanted using a mask to form a lower p-type low concentration layer, and then aluminum is formed. Ion implantation may be performed to form a p-type high-concentration layer located above and having a higher concentration than the p-type high-concentration layer.
[0030]
By this method, boron having a large penetration depth is implanted into a deep position to form a lower channel limiting layer, and an aluminum having a smaller penetration depth and the upper skirt portion of the boron easily form the upper channel limiting layer. Can be formed. The formation of these layers is self-alignment, and can be formed at a predetermined position with high accuracy without causing a displacement or the like.
[0031]
The semiconductor device of the present invention is a semiconductor device formed by a semiconductor substrate and a semiconductor layer formed thereon. The semiconductor device includes a semiconductor layer of a first conductivity type in which a current flows in a direction crossing a surface of a semiconductor substrate, and an edge region of a second conductivity type located at an edge of the semiconductor layer.
[0032]
In any semiconductor device such as a diode, not limited to a transistor, such as a diode, in which a current flows vertically, an electric field concentration occurs at some imperfect point on an end face of a semiconductor substrate, which causes deterioration of withstand voltage performance. For example, the end face of the semiconductor substrate may be regarded as smooth, but may have some irregularities. With the above configuration, it is possible to prevent a reduction in withstand voltage performance due to electric field concentration regardless of the presence or absence of any imperfect point on the end face.
[0033]
Another semiconductor device of the present invention is a semiconductor device formed by a semiconductor substrate and a semiconductor layer formed thereon. This semiconductor device has a first conductivity type semiconductor layer in which a current flows in a direction intersecting a surface of the semiconductor substrate, and a second conductivity type peripheral layer located between an end face of the semiconductor substrate and the first conductivity type semiconductor layer. Region.
[0034]
The second conductive type peripheral region suppresses the occurrence of dielectric breakdown from the electrode contact region located on the outer surface side of the semiconductor layer to the semiconductor substrate at the outer peripheral end of the semiconductor device. Can be. As a result, it is possible to prevent the withstand voltage performance from deteriorating due to the electric field concentration at the outer peripheral end.
[0035]
For example, in the edge region or the peripheral region, in a semiconductor device in which a plurality of unit semiconductor devices are periodically arranged on a semiconductor substrate, the electric field concentration at the end portion is prevented, thereby deteriorating the withstand voltage performance. Can be prevented. Further, the edge region or the peripheral region can prevent electric field concentration on the end surface of one semiconductor device integrated and assembled on the semiconductor substrate regardless of the surface properties of the end surface of the semiconductor substrate.
[0036]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0037]
(Embodiment 1)
FIG. 1 is a diagram showing a JFET according to the first embodiment of the present invention. In the JFET 10 of the present embodiment, an n − -type drift layer 3 is formed on an n + -type SiC substrate 1, and a passage 4 communicating with the drift layer 3 is formed of two upper and lower layers that define a channel layer 6 from below. Channel limiting layers 5a and 5b. The channel limiting layer 5 is formed of a p + type upper channel limiting layer 5a and a p− type lower channel limiting layer 5b having a high impurity concentration.
[0038]
A p + type gate region 7 is formed in a surface layer portion above the channel limiting layer 5, and an n + type source region 8 is formed in a surface layer portion outside the p + type gate region 7. The n + type source region 8 is in ohmic contact with the source electrode S, and the upper channel limiting layer 5a is in ohmic contact with the source electrode S through the high concentration p + type contact 18, and the n + type source region 8 is in ohmic contact with the upper channel limiting layer 5a. Are the same potential. The effective space De is determined based on the space between the lower channel limiting layers 5b having a low impurity concentration, as described later. The effective interval is set to 4 μm or less when SiC is used as a semiconductor, but is more preferably set to 2 μm or less.
[0039]
Next, the operation of the above JFET will be described. In the ON state, a predetermined voltage is applied between the source and the drain, and electrons flow laterally from the source region 8 through the channel layer 6 to reach the passage 4 surrounded by the channel limiting layers 5a and 5b. When flowing from the channel layer 6 to the passage 4, the direction of the current is changed from the horizontal direction to the vertical direction, flows in the drift region 3 in the vertical direction, and reaches the drain electrode D.
[0040]
When turning off, a reverse bias voltage is applied to the pn junction between the channel layer 6 and the gate region 7. Since the p-type impurity concentration in gate region 7 is several orders of magnitude higher than the n-type impurity concentration in channel layer 6, the depletion layer extends over the channel layer. Then, as the reverse bias voltage rises, it reaches the upper channel limitation layer 5a in proportion to the (1/2) power of the reverse bias voltage, cuts off the channel layer 6, and turns off the current. By setting the absolute value of the reverse bias voltage to be sufficiently high, the off state can be surely achieved.
[0041]
In this off state, when the forward voltage was increased between the source and the drain, one of the insulating portions was destroyed, and a low-resistance path from the source region to the drain was found. It begins to flow in a state. The withstand voltage performance can be determined from the forward voltage at this time, and the higher the forward voltage, the higher the withstand voltage performance. There is a tendency that the breakdown of any of the above-mentioned insulating portions is more likely to occur at the electric field concentrated portion where the electric field becomes larger.
[0042]
In the above-mentioned JFET, electric field concentration is likely to occur at the end X surrounding the passage 4 of the channel limiting layer 5. As in the JFET of the present embodiment, when the channel limiting layer 5 is composed of the upper channel limiting layer 5a having a high impurity concentration and the lower channel limiting layer 5b having a low impurity concentration, the lower channel limiting layer having a low impurity concentration has: Functions as an electric field relaxation layer. Therefore, electric field concentration at the end X of the channel limiting layer facing the passage 4 can be avoided, and the withstand voltage performance can be improved.
[0043]
The portion below the upper end of the passage 4 of the JFET shown in FIG. 1 may be used in the following description as the basic structure of the breakdown voltage.
[0044]
The configuration in which the channel limiting layer has a two-layer structure as described above is not limited to the JFET shown in FIG. 1, and the gate region 7 and the channel limiting layer are shared by the same region as shown in FIG. May be arranged below the channel layer to form a single-layer channel structure. In this case, the function of gate region 7 is performed by upper channel limiting layer 5a, and lower channel limiting layer 5b functions as an electric field relaxation layer. FIG. 2 shows only the left half of the bisector (plane) of the effective interval.
[0045]
In addition, as shown in FIG. 3, the two channel limiting layers in the present embodiment are such that the gate region 7 is disposed on the channel layer 6 and the gate region 7 and the channel limiting layer 5 form the channel layer 6. Can also be used for JFETs sandwiching. The JFET shown in FIG. 3 also shows only the left half of the bisector (plane) of the effective interval. In FIG. 3, the channel limiting layer 5a is electrically connected to the source electrode S via the p + type region 18. However, the p + -type region 18 may be electrically connected to the gate electrode G located below the source electrode S with the insulating layer 9 interposed therebetween. That is, the channel limiting layer 5a may be electrically connected to the gate electrode G.
[0046]
FIG. 5 is a diagram showing an arrangement of a plurality of gate layers in the stacked channel structure shown in FIGS. 4 (a) to 4 (c). FIG. 4A is a plan view showing the arrangement of a plurality of gates in the stacked channel structure. FIG. 4B is a cross-sectional view along the line IVB-IVB, and FIG. 4C is a cross-sectional view along the line IVC-IVC. In this JFET, as shown in these figures, a plurality of channel layers 6 extend rightward from a source region 8, and a plurality of gate regions 7a and 7b connected by ap + type region 7c form a plurality of channel layers. 6 and are alternately arranged. The above-mentioned two channel limiting layers can also be used in the JFET having the above structure. In any case, the low concentration layer of the two channel limiting layers functions as an electric field relaxation layer. 4B and 4C also show only the left half of the bisector (plane) of the effective interval.
[0047]
Next, a method for manufacturing the JFET shown in FIG. 1, particularly a method for forming a channel limiting layer having a two-layer structure will be described. After forming a drift layer 3, that is, an n − -type SiC layer 3 on an n + -type SiC substrate 1, channel limiting layers 5 a and 5 b made of two layers having different p-type impurity concentrations are formed on the surface of the n − -type SiC layer. To form At this time, a mask 41 having a width of Dn is arranged on the n − -type SiC layer 3 so as not to introduce a p-type impurity into a portion corresponding to the passage, and ion implantation is performed. The high concentration upper layer 5a of the channel limiting layer mainly contains p-type impurities Al and B, and the low concentration lower layer 5b mainly contains B.
[0048]
The above-described ion implantation is performed by a plurality of times of ion implantation as shown in Table 1. During the plurality of ion implantations, the same mask may be kept as the mask 41.
[0049]
[Table 1]

[0050]
According to Table 1, when B is implanted, the accelerating voltage is set higher than that when Al is implanted, and reaches a deep position. Since B is an element smaller than Al, it is accelerated by the high acceleration voltage and easily reaches a position deeper than Al. FIG. 6 is a diagram showing the distribution of the p-type impurity concentration in the depth direction in which Al and B are combined. The high impurity concentration distribution on the left side with a small distance from the surface in FIG. 6 corresponds to the upper channel limited layer 5a, and the impurity concentration distribution at a deep position corresponds to the lower channel limited layer 5b. It can be seen that all the channel limiting layers are trailing.
[0051]
The above-mentioned spread also occurs in the lateral direction. In other words, since the impurity concentration distribution also extends in the lateral direction and spreads, in the case of the width Dn of the mask 41, the distance between the n-type passages is smaller. The distance between the passages that are narrowed due to the lateral spread of the ion species during the ion implantation and are finally formed is called an effective distance De.
[0052]
When implanted under the implantation conditions in Table 1, as shown in FIG. 5, the upper channel limiting layer 5a extends inward from the mask end to the bottom of the mask by α, and the lower channel limiting layer 5b further extends inward therefrom. Spread by 0.2 μm. Therefore, a relationship of Dn = De + 2 × 0.2 + 2α (unit: μm) is established between the mask width Dn and the effective interval De. The effective distance De is preferably 4 μm or less, and more preferably 2 μm or less.
[0053]
As described above, by forming the channel limitation layer into a two-layer structure and lowering the impurity concentration of the lower channel limitation layer, electric field concentration can be suppressed and the withstand voltage performance can be improved. A specific example of alleviating the electric field concentration will be described in an embodiment.
[0054]
(Embodiment 2)
In a second embodiment of the present invention, a semiconductor device 50 in which a plurality of JFETs 10 described in the first embodiment are arranged on one SiC substrate will be described. FIG. 7 is a plan view of the semiconductor device according to the present embodiment. The JFETs 10 need not necessarily be regularly and periodically arranged. FIG. 8 is a sectional view taken along line VIII-VIII in FIG. 7 (basic structure withstand voltage). The end face of the semiconductor device may not be smooth as shown in FIG. 8 and may have imperfections. The imperfections include, for example, the possibility of unevenness on the end face. This unevenness may be caused by the cutting of the semiconductor substrate, and may be regarded as substantially smooth in some cases, but not in other cases.
[0055]
FIG. 8 shows only the basic structure withstand voltage, but the source region is located on the upper right side of the channel limiting layer, and a voltage is applied between the source region and the drain electrode. When a high voltage is applied between the source and the drain, dielectric breakdown occurs at an end of the semiconductor device starting from an incomplete point, and an avalanche current path is likely to be formed. In order to prevent this, a p-type impurity region, that is, an edge region 50s is arranged at an end portion including the end surface 50b of the SiC layer formed on the SiC substrate. With the arrangement of the edge region 50s, it is possible to suppress dielectric breakdown starting from the unevenness of the end surface. This edge region is formed in the SiC layer above the SiC substrate, but may extend to the SiC substrate.
[0056]
Further, the lower channel limiting layer is extended to the end face side of the substrate so that the n − -type SiC layer 3 is not arranged in the surface layer portion between the end face 50b and the JFET. Due to the arrangement of the peripheral region 5e of the p − -type SiC layer due to the extension to the outside of the lower channel limiting layer, the dielectric breakdown of the portion from the source region located at the outer end of the plurality of JFETs to the drain is also possible. Can be prevented. The width Db of the peripheral region 5e shown in FIG. 8 is preferably 3 μm or more, more preferably 5 μm or more, and preferably 10 μm or more in order to pursue further certainty.
[0057]
In the above description, the SiC substrate includes not only the SiC substrate 1 but also the SiC layer formed thereon, and further includes not only the basic breakdown voltage structure but also the SiC layer thereon. The end face 50b of the SiC substrate also refers to the end face of a layer including from the SiC substrate 1 to the upper SiC layer. The edge region 50s is not formed only on the end surface of the SiC layer having the basic breakdown voltage structure, but is formed at the end of the SiC layer including the layer on which the source region is formed.
[0058]
(Embodiment 3)
The third embodiment of the present invention is characterized in that an edge region or a peripheral region is arranged at an end thereof regardless of the type of a semiconductor device formed on a semiconductor substrate. The semiconductor device formed on one semiconductor substrate is not limited to a single device, and may be a transistor or a diode. FIG. 9 is a plan view showing the semiconductor device 60 described above. The four circumferences are surrounded by the end face 60b of the semiconductor substrate. The range of the end face of the semiconductor substrate is widely interpreted to include the semiconductor layer as well as the end face 50b as described above.
[0059]
10 and 11 are cross-sectional views including the end of the semiconductor device shown in FIG. In FIG. 10, an edge region 60s is provided at an end of the semiconductor device having the portion 3 in which the current i flows in the vertical direction toward the semiconductor substrate. The reason that the edge region enhances the withstand voltage performance is the same as that of the edge region 50s in the second embodiment.
[0060]
FIG. 11 shows that the semiconductor device having the portion 3 in which the current flows in the vertical direction is formed at the end of the semiconductor substrate on which the semiconductor device is formed regardless of the presence or absence of the channel limiting layer in the second embodiment so as to surround the semiconductor device. A p-type peripheral region 26 is arranged. The reason for arranging the peripheral region is to prevent dielectric breakdown of a portion between the electrode located on the surface layer at the outer end and the semiconductor substrate on which the electrode facing this electrode is arranged, as described above. is there. When the semiconductor is SiC, the width Dg of the p − -type peripheral region 26 may be 3 μm or more, more preferably 5 μm or more, and preferably 10 μm to pursue further certainty. It is desirable to have the above.
[0061]
【Example】
Next, a description will be given of the results of simulation calculation of the electric field distribution and the potential distribution by forming a predetermined impurity concentration in each layer and each region in the above-described semiconductor device and JFET.
[0062]
(Example 1)
FIG. 12 is a cross-sectional view (basic structure of breakdown voltage) of the JFET according to the first embodiment of the present invention. In this JFET, the effect of the effective interval De on the withstand voltage performance was examined. The overall width is constant at 10 μm. The impurity concentration of each of the upper channel limiting layer 5a and the lower channel limiting layer 5b is 1 × 10 ¹⁸ / Cm ³ And 1 × 10 ¹⁷ / Cm ³ It is. In this JFET, the drift layer is composed of two layers 3a and 3b, the lower layer 3b is a high concentration layer, and the upper layer 3a is a low concentration layer. Although not described in detail here, another study has confirmed that the merit of forming the drift layer in the two-layer structure is not so large. Therefore, in the case of a single drift layer 3a, the same result as that of the present embodiment can be obtained.
[0063]
FIG. 13 shows the relationship between the drain voltage and the maximum electric field strength when the effective interval is changed in the range of 3.2 μm to 0.4 μm. Experience shows that the maximum electric field strength is 2.3 × 10 ⁶ Since dielectric breakdown occurs at V / cm or more, the electric field strength is used as a reference for dielectric breakdown. According to FIG. 13, in the test sample C7 having an effective interval of 2.0 μm, even when the drain voltage exceeds 1000 V, the maximum electric field intensity is 2.3 × 10 ⁶ V / cm. Further, in the test specimens C3 to C6 whose effective intervals are smaller than that, the pressure resistance performance is more excellent than that of C7.
[0064]
FIG. 14 shows the effect of the effective spacing on the maximum electric field strength when the drain-gate voltage is 500 V and 1000 V. When the drain-gate voltage is 500 V, the maximum electric field strength is 2.3 × 10 ⁶ V / cm or more, but when the drain-gate voltage becomes 1000 V, the effective electric field De exceeds 2 μm and the maximum electric field intensity becomes 2.3 × 10 ⁶ V / cm or more. From these, it can be seen that, for example, when it is desired to obtain a withstand voltage of 1000 V, the effective interval should be 2.0 μm or less.
[0065]
FIG. 15 is a diagram showing an electric field distribution when the effective interval De of the JFET shown in FIG. 12 is 2.0 μm. For convenience of calculation, the anode 31 was arranged on the left and right of the upper end, and the cathode 32 was arranged on the bottom of the SiC substrate, and a voltage was applied between the anode and the cathode. According to FIG. 15, the maximum value of the electric field intensity is distributed not at the end portions of the channel limiting layers 5a and 5b, but at least inside the channel limiting layers 5a and 5b with a slight gap therebetween. This is because the electric field intensity is reduced in the channel-limited layer due to the lowering of the impurity concentration in the lower channel-limited layer by making the channel-limited layer a two-layer structure. That is, the electric field strength of 1 × 10 ⁵ There is a constant electric field strength line of V / cm, and the electric field strength is 1 × 10 ⁶ The isoelectric field strength line of V / cm is located. The gap 30 can be said to be a region where the electric field concentration is reduced near the channel limiting layer. Therefore, the maximum electric field intensity is located in the drift layer without being located at the corner of the end of the channel limiting layer facing the passage. Therefore, the local formation of an abnormally high electric field strength is solved.
[0066]
From Example 1 described above, it was found that the electric field was alleviated by reducing the impurity concentration of the lower channel limiting layer by forming the channel limiting layer into a two-layer structure. Due to this electric field relaxation, it is possible to eliminate distribution of an abnormally large electric field intensity locally in contact with a corner portion of the channel limitation layer facing the passage. When the effective distance between the passages is 2.0 μm or less and the gate / drain voltage is 1000 V, the maximum electric field strength is 2.3 × 10 ⁶ Can be less than. As described above, the depletion layer blocks the channel layer at the gate voltage that maintains the off state. When the effective spacing is narrow, the depletion layers projecting from both sides are easy to unite, and it looks like an integrated depletion layer is formed when viewed from the source and drain. It is considered to be a position that enters the drift layer greatly from the corner portion of. As a result, the electric field intensity distribution is further reduced in the influence of the corners, and the maximum electric field intensity is reduced.
[0067]
(Example 2)
In the second embodiment of the present invention, the effect of the peripheral region 5e in which the lower channel limiting layer having a low impurity concentration extends toward the end of the SiC substrate of the semiconductor device in which the JFET is arranged will be described. FIG. 16 is a diagram showing the structure of the semiconductor device used. In the semiconductor device shown in FIG. 16, the drift layer has a two-layer structure. Of the four specimens examined in this example, three have the two drift layers shown in FIG. The body was composed of one drift layer.
[0068]
As shown in FIG. 17, when the width Db of the peripheral region is about 9.8 μm, it can be seen that very excellent withstand voltage performance is exhibited. Further, since there is no great difference in the maximum electric field strength depending on whether the drift layer is a single layer or a multilayer, it is understood that the number of layers of the drift layer does not significantly affect the withstand voltage performance. If the width Db of the peripheral region is 9.8 μm, the maximum electric field intensity is 2.3 × 10 at the maximum. ⁶ V / cm has not been reached.
[0069]
FIG. 18 shows the electric field distribution. In the present embodiment, the problem is that the JFET is located at the edge of the substrate, so that the anode 31 is located as shown in FIG. According to this electric field distribution, the maximum electric field intensity occurs at the corner of the upper channel limiting layer. However, as described with reference to FIG. 17, even when the maximum electric field strength occurs at the end of the channel limiting layer, the maximum electric field strength is 2.3 × 10 ⁶ V / cm has not been reached. This is achieved by setting the width Db of the peripheral region to about 10 μm as shown in FIG. ⁶ This is because the contour lines of V / cm were pushed down from the surface layer to the drift layer side. As a result, the maximum electric field strength is 2.3 × 10 ⁶ The value does not become so high as to exceed V / cm. The region 30 can be said to be a region in which the electric field concentration is reduced near the channel limiting layer.
[0070]
Although the embodiments of the present invention have been described above, the embodiments of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to these embodiments. The scope of the present invention is shown by the description of the claims, and further includes all modifications within the meaning and scope equivalent to the description of the claims.
[0071]
【The invention's effect】
The JFET and the semiconductor device of the present invention are configured so that local electric field concentration is unlikely to occur, and have excellent breakdown voltage performance. In the method of manufacturing a JFET of the present invention, a channel limiting layer having a two-layer structure can be easily formed by an ion implantation method.
[Brief description of the drawings]
FIG. 1 is a diagram showing a JFET according to a first embodiment of the present invention.
FIG. 2 is a diagram showing another JFET according to the first embodiment of the present invention.
FIG. 3 is a diagram showing still another JFET according to the first embodiment of the present invention.
FIGS. 4 (a) to 4 (c) are diagrams showing other JFETs according to the first embodiment of the present invention, wherein FIG. 4 (a) is a plan view and FIG. 4 (b) is a IVB-IVB of FIG. FIG. 4C is a cross-sectional view taken along line IVC-IVC of FIG.
FIG. 5 is a cross-sectional view in which ions are implanted into a channel limiting layer in the manufacture of the JFET of FIG. 1;
6 is a diagram showing a depth distribution of an impurity concentration after the ion implantation of FIG. 5;
FIG. 7 is a diagram showing a semiconductor device according to a second embodiment of the present invention.
FIG. 8 is a sectional view taken along the line VIII-VIII in FIG. 7;
FIG. 9 is a diagram showing a semiconductor device according to a third embodiment of the present invention.
FIG. 10 is a cross-sectional view of the semiconductor device of FIG. 9 at an end of a semiconductor substrate.
FIG. 11 is a sectional view of another semiconductor device according to a third embodiment of the present invention at an end of a semiconductor substrate.
FIG. 12 shows a JFET according to the first embodiment of the present invention.
FIG. 13 is a diagram showing a relationship between a drain voltage and a maximum electric field intensity.
FIG. 14 is a diagram showing a relationship between an effective distance De and a maximum electric field intensity.
FIG. 15 is a diagram showing an electric field distribution when the effective interval is 2.0 μm.
FIG. 16 shows a semiconductor device according to a second embodiment of the present invention.
FIG. 17 is a diagram showing a relationship between a drain voltage and a maximum electric field intensity for each width of each peripheral region.
FIG. 18 is a diagram showing an electric field distribution in the case where the width of the peripheral region is 9.8 μm.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 SiC substrate, 3, 3a, 3b drift layer, 4 passages, 5 channel limitation layer, 5a upper channel limitation layer, 5b lower channel limitation layer, 5e lower channel limitation layer extending to the end of semiconductor device, 6 channel layer , 7, 7a, 7b Gate region, 7cp + type region (connection region), 8 drain region, 9 insulating layer, 10JFET, 18p + type contact, 26 peripheral region, 30, 40 Relaxed electric field region near channel limited layer , 31 Positive electrode in simulation calculation, 32 Negative electrode in simulation calculation, 50, 60 Semiconductor device, 50b, 60b End face of semiconductor device, Db substrate end face, De effective spacing, width of Dg peripheral region, D drain, G gate, S Source.

Claims (14)

A junction field effect transistor including a semiconductor substrate of a first conductivity type and a semiconductor layer stacked on and in contact with the first conductivity type,
A first conductivity type source region located at a surface portion of the stacked semiconductor layers;
A first conductivity type channel layer which is in contact with the source region and extends from below the source region to below the surface layer portion;
A gate region located in contact with the channel layer;
A first conductivity type drift layer located in contact with the semiconductor substrate and communicating with the drain region;
A second conductive type channel limiting layer positioned between the drift layer and the channel layer from above and below and surrounding a first conductive type passage from the channel layer to the drift layer;
The channel limiting layer is located below and in contact with the channel layer, an upper channel limiting layer having a predetermined second conductivity type impurity concentration, and is located in contact with and below the upper channel limiting layer; A junction field effect transistor comprising: a lower channel limiting layer having a second conductivity type impurity concentration lower than the second conductivity type impurity concentration. The junction field effect transistor according to claim 1, wherein the gate region is provided in a surface layer portion above the channel layer, and the gate region sandwiches the channel limiting layer and the source region. 2. The junction field effect transistor according to claim 1, wherein said channel limiting layer is a gate region. 4. The method according to claim 1, wherein the lower channel limiting layer covers a side of the upper channel limiting layer and extends between the upper channel limiting layer and the first conductivity type passage. The junction type field effect transistor according to the above. The junction field effect transistor according to claim 1, wherein the channel limiting layer is electrically connected to a source region. The junction field effect transistor according to claim 1, wherein an edge region of the second conductivity type is provided at an edge of the semiconductor layer at an edge of the semiconductor substrate of the first conductivity type. . A plurality of the junction field-effect transistors are arranged over the semiconductor substrate. In the junction field-effect transistor located at an edge of the semiconductor substrate, at the edge of the semiconductor substrate, the lower channel limiting layer is formed by the upper channel limiting layer. 7. The junction field effect transistor according to claim 1, wherein the junction field effect transistor covers an outer side of a layer and extends between an edge of the semiconductor layer and the upper channel limiting layer. 8. The semiconductor device according to claim 1, wherein the semiconductor substrate and the semiconductor layer are SiC, a main component of an impurity in the lower channel limiting layer is boron, and a main component of an impurity in the upper channel limiting layer is aluminum and boron. Or a junction type field effect transistor. 9. The junction field effect transistor according to claim 8, wherein an effective distance between the first conductivity type paths is 4 μm or less. 9. The junction field effect transistor according to claim 8, wherein a width of a lower channel limiting layer extending between an edge of the semiconductor layer and the upper channel limiting layer is 3 μm or more. A semiconductor substrate of a first conductivity type and a semiconductor layer stacked on and in contact with the first conductivity type; a current flows through the channel layer in a direction along a surface of the semiconductor substrate; A method for manufacturing a junction field effect transistor flowing in a direction crossing a plane,
Forming a first conductivity type semiconductor layer including the drift layer on the semiconductor substrate;
In forming two layers of the second conductivity type impurity concentration on the drift layer and under the channel layer, ion implantation of different ion species into the first conductivity type semiconductor layer is performed. A method of manufacturing a junction field effect transistor. The semiconductor is SiC. In forming the two layers of the second conductivity type impurity concentration, first, boron is ion-implanted using a mask to form a lower p-type low concentration layer, and then aluminum is formed. The method of manufacturing a junction field-effect transistor according to claim 11, wherein the p-type high-concentration layer, which is located thereon and has a higher concentration than the p-type high-concentration layer, is formed by ion implantation. A semiconductor device formed by a semiconductor substrate and a semiconductor layer formed thereon,
A semiconductor device comprising: a first conductivity type semiconductor layer in which a current flows in a direction intersecting a surface of the semiconductor substrate; and a second conductivity type edge region located at an edge of the semiconductor layer. A semiconductor device formed by a semiconductor substrate and a semiconductor layer formed thereon,
A first conductive type semiconductor layer in which a current flows in a direction intersecting the surface of the semiconductor substrate; a second conductive type peripheral region located between an end surface of the semiconductor substrate and the first conductive type semiconductor layer; A semiconductor device comprising:

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