JP2004334295A - Storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage device capable of speeding up writing operation for run-length-encoded serial data. <P>SOLUTION: A memory array (a storage means) 80 has a plurality of memory blocks 81-88 (a plurality of storage areas) provided correspondingly to data width of parallel data DP. Pixel data DG are imparted to the plurality of memory blocks 81-88 in common, and the pixel data DG are developed to the parallel data DP of the prescribed data width and are stored. At that time, one or more memory blocks to be stored with the pixel data are simultaneously selected from the memory blocks 81-88 on the basis of run-length data (second data) showing continuous numbers of the pixel data DG (first data). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a storage device, and more particularly, to a technique for speeding up a storage operation for data whose value to be stored and the number of consecutive values are known.
[0002]
[Prior art]
Conventionally, in a facsimile or the like, serial data composed of binary data representing white or black pixels is generated by scanning an image. When transmitting this serial data, the serial data is generated by run-length encoding. Is compressed. On the other hand, as a storage device for storing this kind of serial data, there is a storage device which develops and stores parallel data (see Patent Document 1). According to this conventional technique, each data included in the serial data is sequentially input and written to a separate memory array. However, the write operation of the memory array that stores the last input data is performed earlier than that. The speed is higher than that of a memory array that stores data input to the memory array. As a result, the data setup time is shortened, and the writing operation is accelerated as a whole.
[0003]
[Patent Document 1]
JP-A-11-328948 (paragraph number 0012, FIG. 2)
[0004]
[Problems to be solved by the invention]
However, according to the above-described prior art, since each data included in the serial data is individually latched and individually written into the memory array, even when data of the same value continues, each data is individually It is necessary to latch and repeat the same write operation. Therefore, when storing serial data having a large run length, there is a problem that the write operation cannot be effectively speeded up.
The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a storage device that can speed up a write operation of run-length encoded serial data.
[0005]
[Means for Solving the Problems]
In order to solve the above problems, the present invention has the following configurations.
That is, a storage device according to the present invention includes a storage unit having a plurality of storage areas to which a first data is commonly provided and provided in correspondence with a data width of the predetermined number of the first data, Inputting second data representing the number of consecutive 1 data, and, based on the second data, selecting one or more storage areas in which the first data is to be stored from among the plurality of storage areas; Storage area selection means for selecting simultaneously.
According to this configuration, from among the plurality of storage areas, the storage areas in which the plurality of first data having the same value are to be stored are selected in parallel. As a result, a plurality of first data having the same value are developed into parallel data and stored in the memory array 80 in one write operation, and therefore, the write operation is sped up.
[0006]
In the above-mentioned storage device, for example, the storage area selection means stores a first address for providing a start point of an area where the first data is to be stored, and a first register for storing a first address. An adder for adding the value of the second data to a first address; storing an addition result of the adder as a second address for providing an end point of an area where the first data is to be stored; A second register for providing a result to the first register; and a control unit for selectively controlling the plurality of storage areas to be in a writable state based on the contents of the first and second registers. It is characterized by the following.
Also, for example, the control unit selects a storage area to be controlled to be in a writable state based on a relationship between a unit area corresponding to the data width and the first and second addresses. .
[0007]
Further, for example, when the control unit specifies the inside of a unit area to be currently written in the unit area, the first and second addresses may include the plurality of storage areas. The storage area specified by each address from the first address to the second address is simultaneously selected.
Also, for example, the control unit may be configured so that the first address specifies the inside of a unit area of the unit area which is a current writing target of the unit area, and the second address is When the outside of the unit area to be currently written is designated, a storage area designated by each address after the first address is simultaneously selected from the plurality of storage areas. It is characterized by the following.
[0008]
Further, for example, when the control unit specifies the outside of the area currently being written in the unit area in the first and second addresses, the control unit may store the plurality of storage areas. It is characterized in that all are selected simultaneously.
Further, for example, the control unit may be configured so that the first address specifies an outside of a unit area of the unit area which is a current writing target of the unit area, and the second address is In the case where the inside of the unit area to be currently written is designated, a storage area designated by each address before the second address is simultaneously selected from the plurality of storage areas. It is characterized by the following.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a storage device according to an embodiment of the present invention will be described.
FIG. 1 shows a configuration of a storage device according to an embodiment of the present invention. This storage device expands and stores serial data DS as image data into parallel data DP having a predetermined data width including eight pixel data (DP1 to DP8). In this embodiment, the input serial data DS is run-length-encoded in advance, and as shown in FIG. 2A, the pixel data DG and the run-length data RL indicating the number of consecutive pixel data (run-length). Is converted to and input from outside. Each pixel data DG is assumed to be 16-bit data.
[0010]
In FIG. 1, reference numeral 10 denotes an adder, reference numerals 20 and 30 denote registers, reference numeral 40 denotes a comparator, reference numeral 50 denotes a light controller, reference numeral 60 denotes a counter, reference numeral 70 denotes a multiplexer, and reference numeral 80 denotes a memory array. Among them, the adder 10, the registers 20, 30, the comparator 40, the write controller 50, and the counter 60 function as storage area selecting means, and based on the above-described run-length data RL, a plurality of memory blocks 81 to 88. , One or more memory blocks in which pixel data is to be stored are simultaneously selected. The memory array 80 is storage means having eight memory blocks 81 to 88 provided corresponding to the data width of the parallel data DP, and pixel data DG is commonly applied to each memory block.
[0011]
FIG. 2A shows a relationship between the pixel data DG and the run-length data RL. In the figure, the values of the run-length data RL correspond to the values “5”, “8”, “0”, “4”, “2”, “0”, “1”, and “2” of the pixel data DG. “1”, “1”, “8”, “1”, “1”, “2”, “1”, and “1” correspond to each other. According to this example, the serial data before run-length encoding is, for example, that one pixel data “5” and one pixel data “8” are generated, and then eight pixel data “0” are consecutive. Represents. By this run-length encoding, continuous equivalent pixel data included in the serial data DS is replaced with one pixel data DG, thereby reducing the data amount.
[0012]
The description returns to FIG. The above-described run length data RL is applied to one input of an adder 10, and the other input of the adder 10 is supplied with an address ADS which is an output signal of a register 30 described later. An output signal of the adder 10 is applied to a register 20. An address signal ADE, which is an output signal of the register 20, is applied to a comparator 40 and a register 30, and an address ADEL composed of lower 3 bits of the address signal ADE is applied to a write controller 50. Given to. An address signal ADS, which is an output signal of the register 30, is given to the adder 10, the comparator 40, and the counter 60, and an address ADSL consisting of the lower three bits of the address signal ADS is given to the write controller 50. As shown in FIG. 2B, each of the addresses ADE and ADS is made up of 13 bits of “A0” to “A12”, and among these, the lower three bits “A0” to “A2” have eight memories. Data corresponding to any of blocks 81 to 88 appears.
[0013]
An address ADC which is an output signal of the counter 60 is supplied to one input of the comparator 40 and the multiplexer 70, and the other input of the multiplexer 70 is supplied with a read address ADDR. The address AD, which is the output signal of the multiplexer 70, is commonly provided to the memory blocks 81 to 88 forming the memory array 80. The output signal J of the comparator 40 is supplied to the write controller 50, and the write control signal SWE, which is the output signal of the write controller 50, is supplied to the memory array 80. In addition, a trigger signal T for counting up is supplied from the light controller 50 to the above-described counter 60.
[0014]
Each memory block constituting the memory array 80 has a storage area for n (n is an arbitrary natural number) pixel data. In this embodiment, a storage area of one pixel data is defined as a “cell”. One cell stores one pixel data (16 bits). In the example shown in FIG. 3, one memory block 81 includes n cells M (1,1) to M (1, n). Similarly, the other memory blocks 82 to 88 are also composed of n cells, and in the entire memory array 80, the cells M (1, 1) to M (8, n) are arranged in a matrix of 8 rows and n columns. Have been. These eight memory blocks 81 to 88 are provided corresponding to the data width of the parallel data DP, that is, the pixel data included in one parallel data.
[0015]
The cells M (1,1) to M (8, n) arranged in a matrix of 8 rows × n columns are assigned addresses that advance in the column direction. It is continuous. That is, in FIG. 3, the head address is assigned to the cell M (1, 1) in the first column, and hereinafter, the cells (2, 1), M (3, 1), M (4, 1),..., M (8, 1) are assigned addresses that are incremented by “1”. Further, an address which is continuous with the address of the last cell M (8, 1) in the first column is assigned to the first cell M (1, 2) in the second column. Similarly, in the same manner, the stepped address is assigned to each of the cells in the third to n-th columns, and the address is continuous throughout all the columns.
[0016]
Hereinafter, the operation of the storage device according to this embodiment will be described.
First, the correspondence between each image data of the serial data DS and a storage location in the memory array 80 will be described with reference to FIG. FIG. 3 shows a correspondence between each pixel data of the serial data DS and a storage location of the memory array 80. As shown in this example, the serial data DS is stored in a cell group constituting each column of the memory array 80 in units of pixel data corresponding to the number of the memory blocks 81 to 88. For example, in FIG. 3, pixel data values “5”, “8”, “0”, “0”, “0”, “0”, “0”, “ "0" means cells M (1,1), M (2,1), M (3,1), M (4,1), M (5,1), M (6,1), M (7, 1) and M (8, 1). That is, the data string DSm is developed into parallel data and stored in the first column of the memory array 80.
[0017]
Further, pixel data values “0”, “0”, “4”, “2”, “0”, “0”, “1”, and “2” of the pixel data constituting the data string DSm + 1 following the data string DSm are represented by: Cells M (1,2), M (2,2), M (3,2), M (4,2), M (5,2), M (6,2), M (7,2) ), M (8, 2). That is, the data string DSm + 1 is similarly expanded into parallel data and stored in the second column of the memory array 80. Similarly, each pixel data constituting the data sequence following the data sequence DSm + 1 is sequentially stored in the third and subsequent columns of the memory array 80. As described above, the cell group forming each column of the memory array 80 forms an area which is a unit corresponding to the data width for storing the parallel data PD, and the serial data DS is a parallel data consisting of eight pixel data. And stored in one column.
[0018]
Next, the operation of the storage device shown in FIG. 1 will be described by taking as an example the operation until the data string DSm shown in FIG. 3 is stored in the first column of the memory array 80.
First, the operation of the storage device shown in FIG. 1 will be schematically described. This storage device writes successive image data of the same value collectively to a plurality of memory blocks. At this time, a plurality of memory blocks to which the same value is written collectively are designated by addresses stored in the registers 20 and 30, and the write controller 50 simultaneously controls the corresponding plurality of memory blocks to a writable state. I do. That is, the register 30 stores an address that specifies the first memory cell that is the start point of the area where pixel data is to be stored. The register 20 stores an address that specifies the last memory cell that is the end point of the area where pixel data is to be stored. All the memory cells existing within the range specified by each address stored in these registers are controlled to be in a state where they can be written at once. When the image data of the same value is stored over a plurality of columns, the column to be written is switched by incrementing the address ADC output from the counter 60.
[0019]
Next, the operation of each unit will be described in detail. In the initial state, the registers 20 and 30 shown in FIG. 1 are reset, and all bits of the addresses ADE and ADS output from these registers are “0”. Further, the counter 60 is also in a reset state, and all bits of the address ADC which is an output signal thereof are “0”. The multiplexer 70 selects an address ADC output from the counter 60 during a write operation, and selects an externally applied address ADDR during a read operation. Here, since the write operation is mainly described, it is assumed that the multiplexer 70 has selected the address ADC. Further, the write control signal SWE output from the write controller 50 is deactivated, and all of the memory blocks 81 to 88 constituting the memory array 80 to which the write control signal SWE is input are in a state in which data writing is not accepted. .
[0020]
From this initial state, an external device such as a CPU transfers the leading pixel data “5” of the pixel data DG shown in FIG. 2A as the pixel data DG to the memory blocks 81 to 88 of the memory array 80 shown in FIG. Give to the common. At this stage, since none of the memory blocks 81 to 88 accepts writing, the pixel data “5” is not yet written to any of the memory blocks.
On the other hand, when data “1” representing the continuous number of pixel data “5” provided to the memory array 80 is provided to the adder 10 as the run-length data RL, the adder 10 sets the value of the run-length data RL to “ "1" is added to the value of the address ADS stored in the register 30, and the result of the addition is output to the register 20.
[0021]
The comparator 40 compares the address ADS with the address ADE larger by “1” than the address ADS, and outputs a signal J representing the result of the comparison to the write controller 50. In response to the signal J, when the difference between the address ADE and the address ADS is “1”, the write controller 50 uses the write control signal SWE to start from the lower three bits of the address ADS in the memory blocks 81 to 88. Only the memory block 81 specified by the address ADSL is controlled to be in a writable state. As a result, the pixel data “5” is written to the memory block 81.
Thereafter, the value of the register 20 is written into the register 30, and the value "1" of the address ADE that has designated the last memory block until then becomes the value of the address ADS that newly designates the first memory block.
[0022]
Subsequently, the external device supplies the pixel data “8”, and supplies the data “1” representing the number of consecutive pixels as the run-length data RL. In this case, since the value of the address ADS output from the register 30 is “1”, the value “1” of the run-length data RL is added thereto, and the value “2” is output to the register 20. Also in this case, the comparator 40 outputs a signal J indicating that the difference between the address ADE and the address ADS is “1” to the write controller 50, and in response thereto, the write controller 50 sets the lower 3 bits of the address ADS. Is controlled so that only the memory block 82 specified by the address ADSL consisting of is written. As a result, the pixel data “8” is written to the memory block 82.
Thereafter, the value of the register 20 is written into the register 30, and the value "2" of the address ADE that has designated the last memory block until then is set as the value of the address ADS that newly designates the first memory block.
[0023]
Subsequently, the external device supplies the pixel data “0” and supplies the data “8” representing the continuous number as the run-length data RL. In this case, since the value of the address ADS output from the register 30 is “2”, the value “8” of the run-length data RL is added thereto, and the value “10” is output to the register 20. The value “2” of the address ADS and the value “10” of the address ADE are output to the comparator 40. As described above, when the difference between the value “2” of the address ADS and the value “10” of the address ADE is a value “8” larger than the value “1”, the comparator 40 is a unit for storing the parallel data. A memory block to be controlled to be in a writable state is selected based on the relationship between the area (column) and the address ADS and the address ADE.
[0024]
Here, the principle by which the comparator 40 determines a memory block will be described with reference to FIG. FIG. 7A shows a range of memory blocks to be selected when the address ADS and the address ADE specify a cell inside the column C1 to which writing is currently performed. In this case, a memory block indicated by the address ADS to a memory block indicated by the address ADE are simultaneously selected. FIG. 11B shows a case where the address ADS specifies a cell inside the column C1 to be written at present, and the address ADE specifies a cell existing in the column C2 outside the column C1. Indicates the range of memory blocks to be selected when In this case, a memory block specified by each address after the address ADS, that is, a memory block inside the column C1 indicated by the address ADS to the last memory block in the column C1 are simultaneously selected.
[0025]
FIG. 11C shows a case where the address ADS designates a cell existing in the column C0 outside the column C1 to be currently written, and the address ADE also exists in the column C2 outside the column C1. The range of the memory block to be selected when a cell is designated is shown. In this case, all of the plurality of memory blocks 81 to 88 existing in the column C1 are simultaneously selected. FIG. 11D shows a case where the address ADS designates a cell existing in the column C0 outside the column C1 to be currently written, and the address ADE designates a cell inside the column C1. Indicates the range of memory blocks to be selected when In this case, a memory block designated by each address before the address ADE, that is, from the first memory block in the column C1 to the memory block indicated by the address ADE is simultaneously selected.
[0026]
The description returns to FIG. As shown in FIG. 4B, the comparator 40 designates a cell in the column C1 to which the address ADS is to be written, based on the value “10” of the address ADE and the value “2” of the address ADS. It is determined that the address ADE specifies a cell existing in the column C2 outside the column C, and the result of this determination is output to the write controller 50. In response to this, based on the address ADSL consisting of the lower three bits of the address ADS, the write controller 50 starts writing the same value from the first memory block 83 to the last memory block 88 for the column C1 to be written. Is controlled to be in a writable state. As a result, the pixel data “0” is collectively written into the memory blocks 83 to 88, and the writing operation is speeded up.
[0027]
Subsequently, the write controller 50 outputs the trigger signal T to the counter 60, and increments the address ADC, which is the output signal of the counter 60, by “1”. As a result, the second column C2 is the target of writing. In this case, as shown in FIG. 4D, the address ADS specifies a cell existing in the column C1 outside the column C2 to be newly written, and the address ADE is the cell in the column C2. Therefore, the comparator 40 controls the state from the head memory block of the column C2 to the memory block 82 specified by the address ADEL including the lower three bits of the address ADE in a writable state. Pixel data “0” is collectively written into 81 and 82. Hereinafter, pixel data “4” and the like are sequentially written in the same manner. As described above, the pixel data DG is developed into parallel data and stored in the memory array 80.
[0028]
The pixel data written in the memory array 80 as described above is read for each column. In this case, the multiplexer 70 selects the address ADDR and outputs it to the memory array 80 as the address AD. The column of the memory array 80 is alternatively selected by the address AD (ADDR), and the pixel data DP1 to DP8 stored in this column are read in parallel.
As described above, the embodiments of the present invention have been described in detail. However, the specific configuration is not limited to the embodiments, and includes a design change or the like without departing from the gist of the present invention. For example, in the above-described embodiment, serial data composed of image data is described as an example. However, the present invention is not limited to this, and any serial data that is run-length encoded data may be used.
[0029]
【The invention's effect】
As described above, according to the present invention, the second data representing the continuous number of the first data included in the serial data is input, and a plurality of storage areas are selected based on the second data. Therefore, the write operation of the run-length encoded serial data can be speeded up.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a storage device according to an embodiment of the present invention.
FIG. 2 is a diagram for explaining a data and address configuration of the storage device according to the embodiment of the present invention;
FIG. 3 is an explanatory diagram for explaining a relationship between serial data and a storage location of the storage device according to the embodiment of the present invention;
FIG. 4 is an explanatory diagram for explaining an operation of the storage device according to the embodiment of the present invention;
[Explanation of symbols]
10; adders, 20, 30; registers, 40; comparators, 50; light controllers, 60; counters, 70; multiplexers, 80; memory arrays, 81 to 88;

Claims (7)

Storage means having a plurality of storage areas to which a first data is provided in common and which is provided corresponding to a data width of the predetermined number of the first data;
Second data representing the number of continuations of the first data is input, and one or more storages in which the first data is to be stored from the plurality of storage areas based on the second data. Storage area selecting means for simultaneously selecting an area;
A storage device comprising: The storage area selecting means,
A first register for storing a first address giving a start point of an area in which the first data is to be stored;
An adder for adding a value of the second data to a first address stored in the first register;
A second register for storing an addition result of the adder as a second address for providing an end point of an area where the first data is to be stored, and for providing the addition result to the first register;
A control unit that selectively controls the plurality of storage areas to a writable state based on the contents of the first and second registers;
The storage device according to claim 1, further comprising: The control unit includes:
3. The storage device according to claim 2, wherein a storage region to be controlled to be in a writable state is selected based on a relationship between a unit region corresponding to the data width and the first and second addresses. . The control unit includes:
In the case where the first and second addresses specify the inside of a unit area to be currently written in the unit area, the first address and the second address of the plurality of storage areas are 4. The storage device according to claim 3, wherein a storage area specified by each address up to a second address is simultaneously selected. The control unit includes:
The first address specifies the inside of the unit area of the unit area to be currently written, and the second address is the target of the current write. 4. The method according to claim 3, wherein when the outside of the unit area is designated, a storage area designated by each address after the first address is simultaneously selected from the plurality of storage areas. The described storage device. The control unit includes:
When the first and second addresses specify outside the area of the unit area to be written at present, it is preferable that all of the plurality of storage areas be simultaneously selected. The storage device according to claim 3, wherein: The control unit includes:
The first address specifies the outside of the unit area of the unit area to be currently written, and the second address is the target of the current write. 4. The method according to claim 3, wherein when specifying the inside of the unit area, a storage area specified by each address before the second address is simultaneously selected from the plurality of storage areas. The described storage device.

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