JP2004320180A - Imaging apparatus and control method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent DMA noise from being superimposed on a video signal. <P>SOLUTION: A CCD receiving a horizontal transfer pulse or the like provides an output of a video signal. An analog signal processing is applied to the video signal to convert the video signal into image data. The image data are written in a line memory in a digital signal processing circuit, subjected to digital signal processing therein and again written in the line memory. The image data written in the line memory are read and subjected to DMA transfer to a memory via a data bus. Application of the horizontal transfer pulse ϕH to the CCD is stopped for a time (t12 to t13, t14 to t15, and t16 to t17 or the like) when the image data are subjected to DMA transfer from the line memory to the memory. Superimposition of the DMA noise on the video signal outputted from the CCD is prevented. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
【Technical field】
The present invention relates to an imaging apparatus and a control method thereof.
[0002]
BACKGROUND OF THE INVENTION
In a digital still camera, a solid-state electronic image sensor such as a CCD is used. In a camera using a solid-state electronic image sensor, a high-quality image is required, so that there is a high demand for noise removal.
[0003]
Depending on the case of high-sensitivity imaging and low-sensitivity imaging, there are cases in which noise is not conspicuous due to, for example, how to read a signal charge in a CCD or change the pass band of a low-pass filter (for example, Patent Document 1). reference).
[0004]
[Patent Document 1]
Japanese Patent Laid-Open No. 2000-50169
However, it cannot be said that noise has been completely removed.
[0006]
DISCLOSURE OF THE INVENTION
An object of the present invention is to remove noise.
[0007]
An image pickup apparatus according to the present invention includes a solid-state electronic image pickup device that picks up an image of a subject and outputs image data representing the image of the subject in response to a given readout pulse, a drive circuit that applies the readout pulse to the solid-state electronic image pickup device, and the solid-state electronic device. A first memory for temporarily storing image data output from the imaging device, a digital signal processing for performing predetermined digital signal processing on the image data stored in the first memory and storing the image data in the first memory A circuit, a second memory for storing applied image data, a memory controller for reading image data stored in the first memory of the digital signal processing circuit and supplying the read image data to the second image memory, and the second An output device for outputting image data stored in the memory, and the first by the memory controller Characterized in that it comprises a control means for controlling the drive circuit so as to stop the output of the image data from the solid-state electronic image sensing device in the memory of the image data into the second memory transfer.
[0008]
The present invention also provides a control method suitable for the imaging apparatus. That is, in this method, a solid-state electronic imaging device that captures an image of a subject and outputs image data representing a subject image according to a given readout pulse, a drive circuit that provides the readout pulse to the solid-state electronic imaging device, and the solid-state electronic imaging A first memory for temporarily storing image data output from the apparatus, a digital signal processing circuit for performing predetermined digital signal processing on the image data stored in the first memory and storing the image data in the first memory , A second memory for storing given image data, and a memory controller for reading the image data stored in the first memory of the digital signal processing circuit and giving it to the second image memory, In the imaging device that outputs the image data stored in the second memory, the memory controller It is characterized in that for controlling the drive circuit so as to stop the output of the image data from the solid-state electronic image sensing device in the transfer of image data from the first memory to the second memory.
[0009]
Image data obtained by imaging is temporarily stored in a first memory in the digital signal processing circuit. The image data is read from the first memory and subjected to predetermined digital signal processing. The image data subjected to the signal processing is stored again in the first memory. Image data is read from the first memory and stored in the second memory. The image data stored in the second memory is output from the output device. For example, an image recorded on the recording medium or represented by the image data is displayed on the display screen of the display device.
[0010]
According to the present invention, when image data is being transferred from the first memory to the second memory, the output of the image data from the solid-state electronic imaging device is stopped. Due to the transfer of the image data, noise may occur in the image data output from the solid-state electronic imaging device. According to the present invention, when image data is transferred from the first memory to the second memory, the output of the image data from the solid-state electronic imaging device is stopped, so that noise is added to the image data output from the solid-state electronic imaging device. Can be prevented in advance.
[0011]
The solid-state electronic imaging device includes a large number of photoelectric conversion elements, a vertical transfer path for transferring in the vertical direction based on a vertical transfer pulse to which signal charges accumulated in the photoelectric conversion elements are applied, and a signal transferred through the vertical transfer path. A horizontal transfer path that transfers charges in the horizontal direction based on a given horizontal transfer pulse and outputs the charges as image data may be provided. In this case, the driving circuit will give the vertical transfer pulse and the horizontal transfer pulse to the solid-state electronic imaging device. Further, the control means will stop the horizontal transfer pulse during the transfer of the image data from the first memory to the second memory by the memory controller.
[0012]
Further, a recording mode setting means may be further provided. In this case, the output device will record the image data stored in the second memory on the recording medium in accordance with the setting of the recording mode by the recording mode setting means. Then, the control means responds to the setting of the recording mode by the recording mode setting means and the solid-state electronic imaging during the transfer of the image data from the first memory to the second memory by the memory controller. The drive circuit is controlled so as to stop the output of image data from the apparatus.
[0013]
Image data from which noise has been removed can be recorded on a recording medium.
[0014]
Level adjusting means for increasing the level of image data output from the solid-state electronic imaging device in response to setting of the high sensitivity imaging mode by the high sensitivity imaging mode setting means and the high sensitivity imaging mode setting means. You may make it provide further. In this case, the control means transfers the image data from the first memory to the second memory by the memory controller in response to the setting of the high sensitivity imaging mode by the high sensitivity imaging setting mode setting means. The drive circuit is controlled to stop outputting image data from the solid-state electronic imaging device.
[0015]
In the case of the high sensitivity imaging mode, the level of the image data is often small, so that the level is raised. The noise increases as the level is raised. In the high-sensitivity imaging mode, the output of the image data from the solid-state electronic imaging device during the transfer of the image data from the first memory to the second memory is stopped, so even if the level of the image data is increased Noise is inconspicuous.
[0016]
[Explanation of Examples]
FIG. 1 shows an embodiment of the present invention and is a block diagram showing an electrical configuration of a digital still camera.
[0017]
The entire operation of the digital still camera is controlled by the CPU 7.
[0018]
The digital still camera according to this embodiment is capable of high-sensitivity imaging, and includes a high-sensitivity imaging setting switch 21 for setting high-sensitivity imaging. Further, an imaging mode setting switch 22 for setting the imaging mode and a recording mode setting switch 23 for setting the recording mode are provided. Output signals from these switches 21, 22 and 23 are input to the CPU 7.
[0019]
The digital still camera includes a timing generator 6 that generates various pulses and the like. In the timing generator 6, a horizontal pulse H and a vertical pulse V for generating a horizontal transfer pulse φH and a vertical transfer pulse φV are generated and supplied to the driver 5. Further, the timing generator 6 generates a horizontal synchronizing signal HD and supplies it to the digital signal processing circuit 3.
[0020]
In the driver 5, a horizontal transfer pulse φH and a vertical transfer pulse φV are generated from the applied horizontal pulse H and vertical pulse V. The generated horizontal transfer pulse φH and vertical transfer pulse φV are applied to the CCD 1.
[0021]
When the imaging mode is set by the imaging mode setting switch 22, the subject is imaged by the CCD 1. When the vertical transfer pulse φV and the horizontal transfer pulse φH are supplied from the driver 5, an analog video signal representing the subject image is output from the CCD 1. The analog video signal is subjected to predetermined analog signal processing such as correlated double sampling, video signal level adjustment, and analog / digital conversion processing in the analog signal processing circuit 2. Image data (AD image data) and AD clock pulses are output from the analog signal processing circuit 2 and input to the digital signal processing circuit 3.
[0022]
The analog signal processing circuit 2 is also supplied with an AD clock / pulse stop control signal from the CPU 7. Specifically, as described later, when the analog stop control signal becomes H level, the AD clock pulse output from the analog signal processing circuit 2 is stopped. Then, the writing of AD image data to the line memory 4 included in the digital signal processing circuit 3 is stopped.
[0023]
As described above, the digital signal processing circuit 3 includes the line memory 4. When the AD image data and the AD clock pulse are given to the digital signal processing circuit 3, the AD image data is written into the line memory 4. The written AD image data is read from the line memory 4 and subjected to predetermined digital signal processing such as white balance adjustment and gamma correction. The AD image data on which the digital signal processing has been performed is written again in the line memory 4. The AD image data after the digital signal processing is read from the line memory 4 by DMA transfer control by a DMAC (direct memory access controller) 8 and written to the memory 9 via the data bus. Writing of AD image data to the line memory 4, digital signal processing, rewriting of the AD image data after the digital signal processing to the line memory 4, and DMA of the image data written to the line memory 4 to the memory 9 The transfer is repeated.
[0024]
When the image data for one frame is written in the memory 9, the image data is read from the memory 9 and given to the display device 11 via the display interface 10. A subject image obtained by imaging is displayed on the display screen of the display device 11.
[0025]
When the recording mode is set by the recording mode setting switch 23, the image data written in the memory 9 as described above is input to the compression circuit 12. In the compression circuit 12, compression based on jpeg (joint photographic experts group) is performed. The compressed image data is given to the memory card 13 and recorded.
[0026]
2 (A), (B), (C) and (D) and FIGS. 3 (A), (B) and (C) are time charts of pulses and the like flowing through the circuit shown in FIG. 3 is shown enlarged compared to FIG.
[0027]
The digital still camera according to this embodiment reads the image data written in the line memory 4 and stops the horizontal transfer pulse φH applied to the CCD 1 when DMA transfer is performed to write it in the memory 9. is there. When DMA transfer is performed, what is called DMA noise may occur. Then, the generated DMA noise may be superimposed on the analog video signal output from the CCD 1. In this embodiment, when DMA transfer is being performed, the horizontal transfer pulse φH applied to the CCD 1 is stopped, so that it is possible to prevent DMA noise from being superimposed on the video signal output from the CCD 1. .
[0028]
As shown in FIG. 2A, the horizontal transfer pulse φH is given to the CCD 1 during a period in which the horizontal synchronization signal HD is at the H level (for example, between the periods t11 to t17). During a period during which DMA transfer is performed (t12 to t13, t14 to t15, t16 to t17, etc.), the horizontal transfer pulse φH is stopped. During a period when DMA transfer is not performed (t11 to t12, t13 to t14, t15 to t16, etc.), the horizontal transfer pulse φH is applied to the CCD 1 and a video signal is output from the CCD 1. Since the video signal is output from the CCD 1 during the period when the DMA transfer is not performed, it is possible to prevent the DMA noise from being superimposed on the video signal as described above.
[0029]
During the period in which the horizontal transfer pulse φH is stopped and the video signal output from the CCD 1 is stopped (t11 to t12, t13 to t14, t15 to t16, etc.), the CPU 7 sends an AD clock pulse to the analog signal processing circuit 2. A stop control signal is provided. As described above, when an AD clock pulse is applied to the digital signal processing circuit 3, AD image data is written into the line memory 4.
[0030]
When the horizontal transfer pulse φH is applied to the CCD 1, no video signal is output from the CCD 1, but invalid AD image data is output from the analog signal processing circuit 2 even when no video signal is output from the CCD 1. (See FIG. 3A). Invalid AD image data is written into the line memory 4.
[0031]
In this embodiment, during the period when the horizontal transfer pulse φH is stopped and the video signal is not output from the CCD 1 (for example, the period from t12 to t13), the analog signal processing circuit 2 is supplied with an AD clock pulse stop control signal. Is given. The output of the AD clock pulse from the analog signal processing circuit 2 is stopped, and invalid data is prevented from being written in the line memory 4 beforehand.
[0032]
While the horizontal transfer pulse φH is stopped, the analog signal processing in the analog signal processing circuit 2 may be continued or stopped. Further, as described above, the horizontal transfer pulse φH during the DMA transfer of the image data from the line memory 4 to the memory 9 is stopped when the recording mode is set or when the high-sensitivity imaging mode is set. You may make it carry out. When the high-sensitivity imaging mode is set, the level of the analog video signal output from the CCD 1 is raised in the analog signal processing circuit. When the DMA noise is superimposed on the video signal, the level of the DMA noise is also increased. For this reason, when the high-sensitivity imaging mode is set, the output of the video signal is stopped during DMA transfer to prevent the DMA noise from being superimposed on the video signal.
[0033]
Further, the DMA transfer may be performed within the horizontal blanking period. Even in that case, it is possible to prevent the image signal from being superimposed on the DMA noise.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an electrical configuration of a digital still camera.
2A to 2D are time charts showing pulses and the like flowing through the circuit shown in FIG.
3A to 3C are time charts showing pulses and the like flowing through the circuit shown in FIG. 1, and are enlarged compared to FIG.
[Explanation of symbols]
1 CCD
2 Analog signal processing circuit 3 Digital signal processing circuit 4 Line memory (first memory)
5 Driver 6 Timing generator 7 CPU
8 DMA controller (memory controller)
9 Memory (second memory)
21 High sensitivity mode setting switch 23 Recording mode setting switch

Claims (5)

A solid-state electronic imaging device that images a subject and outputs image data representing the subject image in accordance with a given readout pulse;
A drive circuit for applying the readout pulse to the solid-state electronic imaging device;
A first memory for temporarily storing image data output from the solid-state electronic imaging device;
A digital signal processing circuit for performing predetermined digital signal processing on the image data stored in the first memory and storing the image data in the first memory;
A second memory for storing the given image data;
A memory controller for reading image data stored in the first memory of the digital signal processing circuit and supplying the image data to the second image memory;
An output device for outputting image data stored in the second memory, and an image from the solid-state electronic imaging device during transfer of the image data from the first memory to the second memory by the memory controller Control means for controlling the drive circuit to stop data output;
An imaging apparatus comprising: The solid-state electronic imaging device is
A number of photoelectric conversion elements, a vertical transfer path for transferring signal charges accumulated in the photoelectric conversion elements in a vertical direction based on a given vertical transfer pulse, and a horizontal transfer for receiving signal charges transferred through the vertical transfer path It is equipped with a horizontal transfer path that transfers in the horizontal direction based on the pulse and outputs it as image data.
The drive circuit is
Providing the vertical transfer pulse and the horizontal transfer pulse to the solid-state electronic imaging device;
The control means is
Stopping the horizontal transfer pulse during transfer of image data from the first memory to the second memory by the memory controller;
The imaging device according to claim 1. A recording mode setting means;
The output device records the image data stored in the second memory on a recording medium according to the recording mode setting by the recording mode setting means,
In response to the setting of the recording mode by the recording mode setting means, the control means causes the solid-state electronic imaging device to transfer the image data from the first memory to the second memory by the memory controller. The drive circuit is controlled to stop the output of the image data of
The imaging device according to claim 1. High-sensitivity imaging mode setting means,
Level adjustment means for increasing the level of image data output from the solid-state electronic imaging device in response to the high sensitivity imaging mode being set by the high sensitivity imaging mode setting means,
The control means is responsive to the setting of the high-sensitivity imaging mode by the high-sensitivity imaging setting mode setting means, during the transfer of image data from the first memory to the second memory by the memory controller. The drive circuit is controlled so as to stop the output of image data from the solid-state electronic imaging device.
The imaging device according to claim 1. A solid-state electronic imaging device that images a subject and outputs image data representing a subject image according to a given readout pulse, a drive circuit that gives the readout pulse to the solid-state electronic imaging device, and an image output from the solid-state electronic imaging device A first memory for temporarily storing data, a predetermined digital signal processing for the image data stored in the first memory, and a digital signal processing circuit for storing the data in the first memory; A second memory for storing, and a memory controller for reading the image data stored in the first memory of the digital signal processing circuit and applying the read image data to the second image memory, and storing the second memory in the second memory In an imaging device that outputs the processed image data,
The drive circuit is controlled to stop outputting the image data from the solid-state electronic imaging device during the transfer of the image data from the first memory to the second memory by the memory controller. Do,
Control method of imaging apparatus.

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