JP2004318640A - Terminal-positioning device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a terminal-positioning device and method that can position the terminals taking into consideration the noise caused by simultaneous operating of a plurality of output buffer cells. <P>SOLUTION: A terminal layout sheet 22 is obtained in a layout editing section 12 for editing the template generated in a template sheet generating section 11, according to the information from a package library file 21. A simultaneous output group name combining section 13 specifies the output buffer cell groups operating, at the same time, on this terminal layout sheet, and checks if there is a corresponding matching the constraints of the simultaneous operations of the prescribed output terminals between the terminals of the semiconductor package and the output pins, using an output simultaneous operation terminal number limiting checking section 14. By extracting the circuit port information 25 in the circuit port information extracting section 15 and comparing it with the circuit information in the circuit information comparison section 16, correspondence is confirmed between the terminals of the semiconductor package and the outer connection pins of the logic circuit, by checking the consistency with the circuit information from the early stage of the circuit design. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a terminal arrangement device and a terminal arrangement method for associating terminals on a semiconductor package with external connection pins of a logic circuit.
[0002]
[Prior art]
A semiconductor integrated circuit device includes a semiconductor chip called a die on which a logic circuit is mounted, and a semiconductor package that covers the semiconductor chip. As a semiconductor package, a BGA (Ball Grid Array) package or a PGA (Pin Grid Array) package that can be easily mounted at high density on a circuit board incorporated in an electronic device is widely used. Such a semiconductor package includes a terminal (referred to as an external terminal) for connecting to a circuit board of an electronic device, and an internal terminal wire-bonded to a pad which is an external connection pin of a logic circuit mounted on a semiconductor chip. And a wiring pattern formed by connecting the external terminals and the internal terminals. On the other hand, the semiconductor chip is provided with a plurality of output buffer cells, and these plurality of output buffer cells are connected to a plurality of external terminals provided in the semiconductor package via the pads, bonding wires, and internal terminals. Have been.
[0003]
Here, when the plurality of output buffer cells simultaneously change from the OFF state to the ON state, the signals of the plurality of external terminals provided corresponding to the plurality of output buffer cells also simultaneously change from the “H” level to the “L” level. Change. Similarly, when the plurality of output buffer cells simultaneously change from the on state to the off state, the signals of the plurality of external terminals simultaneously change from the “L” level to the “H” level. Accordingly, charge / discharge currents corresponding to the load capacities of the plurality of external terminals simultaneously and instantaneously flow through the power supply line and the ground line. Then, noise occurs in the power supply line and the ground line.
[0004]
Therefore, in designing a semiconductor package, there has been proposed a terminal arrangement device which places a limit on the number of output buffer cells that can be operated simultaneously and arranges external terminals including a power supply terminal and a ground terminal in consideration of the limitation. For example, a first terminal information editing unit for displaying a pad number of a semiconductor chip and performing an editing operation and a second terminal information editing unit for displaying an external terminal number of a semiconductor package and performing an editing operation are provided. A terminal arrangement device that visually arranges external terminals by interlocking a terminal information editing unit and a second terminal information editing unit has been proposed (see Patent Document 1).
[0005]
[Problems to be solved by the invention]
In designing a semiconductor integrated circuit device, the required number of power supply terminals and ground terminals are checked, and depending on the result, the size of a semiconductor package or a semiconductor chip may be changed. Therefore, it is preferable to arrange the external terminals at an early stage of designing a logic circuit mounted on the semiconductor chip.
[0006]
However, the terminal arranging device proposed in the above-mentioned Patent Literature 1 has a configuration in which the correspondence between the external terminal number of the semiconductor package and the pad number of the semiconductor chip has already been assigned and the external terminal at the time when the design of the logic circuit is almost completed Since the arrangement is performed, it is difficult to input the arrangement information of the external terminals at the initial stage of designing the logic circuit. Therefore, there is a point that the external terminal arrangement in which the noise generated due to the charge / discharge current corresponding to the load capacitance on the plurality of external terminals accompanying the simultaneous operation of the plurality of output buffer cells is taken into account is lacking.
[0007]
In addition, the terminal arrangement device proposed in Patent Document 1 extracts a plurality of pieces of external terminal information corresponding to a plurality of simultaneously operating output buffer cells from a result of a simulation by applying a test pattern. To obtain such information, a considerable number of test patterns are required. However, there is a problem that such a simulation itself is difficult in a large-scale integrated circuit in recent years, and is therefore not realistic.
[0008]
Further, since the design of the logic circuit is almost completed, the control of allocating a plurality of external terminals corresponding to a plurality of output buffer cells operating simultaneously to the same group (simultaneous operation group) is performed only based on the result of the simulation. In some cases, it is difficult to perform a trial in which an external terminal corresponding to an output buffer cell of a certain simultaneous operation group is assigned to another simultaneous operation group and operated simultaneously. Therefore, when associating terminals on a semiconductor package with external connection pins of a logic circuit, which are pads of a semiconductor chip, there is a problem that a terminal arrangement lacking in consideration of noise generated due to simultaneous operation of a plurality of output buffer cells is lacking. There is.
[0009]
In view of the above circumstances, an object of the present invention is to provide a terminal arrangement device and a terminal arrangement method capable of performing terminal arrangement in consideration of noise generated due to simultaneous operation of a plurality of output buffer cells.
[0010]
[Means for Solving the Problems]
A terminal placement device of the present invention that achieves the above object is a terminal placement device that associates external connection pins of a logic circuit with terminals on a semiconductor package,
A function for associating terminals on the semiconductor package with power supply pins, ground pins, and external connection pins of circuit specifications,
A check function for checking whether the correspondence between the terminal on the semiconductor package and the external output pin is a correspondence that matches predetermined output terminal simultaneous operation restrictions,
A grouping function for dividing external output pins of the external connection pins of the logic circuit corresponding to the terminals on the semiconductor package into groups of external output pins that operate simultaneously according to an operation;
A group designation function for designating one or more groups among the groups divided by the grouping function according to an operation;
The check function performs the above-described check on the assumption that external output pins belonging to one or more groups specified by the group specification function operate simultaneously. The external output pins referred to here include external input / output pins having a bidirectional function.
[0011]
The terminal arrangement apparatus of the present invention associates a terminal on a semiconductor package with an external connection pin of a logic circuit specification, and checks whether the association is a correspondence that matches predetermined output terminal simultaneous operation restrictions. Therefore, the external connection pins of the logic circuit can be associated with the terminals on the semiconductor package while checking the consistency with the circuit information from the initial stage of circuit design. Therefore, an appropriate terminal arrangement can be performed in consideration of the arrangement of the power supply terminal and the ground terminal and the noise generated due to the simultaneous operation of the plurality of output buffer cells.
[0012]
By doing so, it is possible to check a combination of groups of external output pins that operate simultaneously.
[0013]
Further, the associating function associates the terminal with a power supply pin, a ground pin, and the external connection pin, and further associates the terminal with the external output pin, and further includes an output buffer having drive capability information. It associates cells,
The check function is based on information on the driving capability of the output buffer cell further associated with the association between the terminal and the external output pin, and on the association between the terminal, the power supply pin, and the ground pin. Performing the above check is also a preferred embodiment.
[0014]
With this configuration, the external connection pins of the logic circuit can be associated with the terminals on the semiconductor package according to the driving capability of the output buffer cell.
[0015]
Furthermore, it is determined whether or not the names and input / output attributes of the external connection pins associated with the terminals by the association function and the external connection pins on the logic circuit designed based on the circuit specifications match. It may have a confirmation function for checking.
[0016]
With such a confirmation function, the external connection pins of the logic circuit can be reliably associated with the terminals on the semiconductor package.
[0017]
Further, a terminal arrangement method of the present invention for achieving the above object is a terminal arrangement method for associating external connection pins of a logic circuit with terminals on a semiconductor package,
Associating a power supply pin, a ground pin, and an external connection pin of a circuit specification with a terminal on the semiconductor package;
A check step of checking whether or not the correspondence between the terminal on the semiconductor package and the external output pin is a correspondence that matches predetermined output terminal simultaneous operation constraints;
A grouping step of grouping external output pins of the external connection pins of the logic circuit corresponding to the terminals on the semiconductor package into groups of external output pins that operate simultaneously according to an operation;
A group designation step of designating at least one of the groups divided by the grouping step according to an operation;
The checking step is characterized in that the checking is performed by assuming that the external output pins belonging to one or more groups specified in the group specifying step operate simultaneously.
[0018]
According to the terminal arrangement method of the present invention, an external connection pin of a logic circuit can be associated with a terminal on a semiconductor package while checking consistency with circuit information from an initial stage of circuit design. Therefore, an appropriate terminal arrangement can be performed in consideration of the arrangement of the power supply terminal and the ground terminal and the noise generated due to the simultaneous operation of the plurality of output buffer cells.
[0019]
By doing so, it is possible to check a combination of groups of external output pins that operate simultaneously.
[0020]
The associating step associates the terminal with a power supply pin, a ground pin, and the external connection pin, and further associates the terminal with the external output pin, and further includes an output buffer having drive capability information. The step of associating cells
The checking step is based on information on the driving capability of the output buffer cell further associated with the association between the terminal and the external output pin, and on the association between the terminal, the power supply pin, and the ground pin. In a preferred embodiment, the above-mentioned check is performed.
[0021]
With this configuration, the external connection pins of the logic circuit can be associated with the terminals on the semiconductor package according to the driving capability of the output buffer cell.
[0022]
Further, it is determined whether or not the name and the input / output attribute match between the external connection pin associated with the terminal in the association step and the external connection pin on the logic circuit designed based on the circuit specification. It may have a confirmation step of checking.
[0023]
With such a checking step, the external connection pins of the logic circuit can be reliably associated with the terminals on the semiconductor package.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0025]
FIG. 1 is a block diagram of a terminal arrangement device according to an embodiment of the present invention.
[0026]
A terminal placement device 10 shown in FIG. 1 is a device to which the terminal placement method according to one embodiment of the present invention is applied. The terminal placement device 10 includes a template sheet generation unit 11 and a terminal placement sheet editing unit 12. , An output simultaneous operation group name combination generation unit 13, an output simultaneous operation terminal number constraint check unit 14, a circuit port information extraction unit 15, and a circuit information comparison unit 16.
[0027]
The template sheet generating unit 11 generates a template sheet based on information from the package library file 21. When the operator inputs desired data to the generated template sheet, the terminal arrangement sheet 22 is generated. The details will be described below with reference to FIGS. 2, 3, and 4.
[0028]
FIG. 2 is a diagram showing the structure of the package library file.
[0029]
The package library file 21 shown in FIG. 2 includes a pad number (PAD) of a semiconductor chip which is an external connection pin of a logic circuit, a terminal number (PIN) of a semiconductor package, and a name of a power supply or a ground (power / ground). It is composed of Here, names (PAD) 1 to 14, terminal numbers A1 to A14 corresponding to the numbers (PAD) 1 to 14, and names indicating that the terminals represented by terminal numbers A1, A10, and A14 are power terminals. OVDD is shown. As described above, the terminal arrangement of the power supply terminals among the terminals of the semiconductor package is predetermined.
[0030]
FIG. 3 is a diagram showing two fields and a template sheet.
[0031]
FIG. 3 shows a first field 26, a second field 27, and a template sheet 28. The first field 26, the second field 27, and the template sheet 28 are displayed on a display unit (not shown) of the terminal arrangement device 10. At the beginning, only the first field 26 and the second field 27 are displayed.
[0032]
The first field 26 includes a template button (Template) 26_1, a group button (Group) 26_2, and a check button (Check) 26_3.
[0033]
The template button 26_1 is a button for generating the template 28. When the template button 26_1 is operated by the operator, the template sheet 28 is generated based on the information from the package library file 21 shown in FIG. Is done.
[0034]
The group button 26_2 has a role of a grouping function that divides the external output pins of the external connection pins of the logic circuit corresponding to the terminals on the semiconductor package into groups of external output pins that operate simultaneously according to an operation. Button.
[0035]
The check button 26_3 is used to check whether or not the correspondence between the terminal on the semiconductor package and the external output pin matches the predetermined output terminal simultaneous operation constraint. This is a button for performing the operation on 14.
[0036]
The second field 27 includes a pad section (PAD) 27_1, a terminal section (PIN) 27_2, a signal section (SIGNAL) 27_3, a cell section (CELL) 27_4, an input / output section (IN / OUT) 27_5, and a group. A section (GROUP) 27_6, a power supply coefficient section (OVDD) 27_7, a ground coefficient section (OVSS) 27_8, and a message section (Message) 27_9.
[0037]
The pad portion 27_1 and the terminal portion 27_2 are portions for displaying a pad number (PAD) and a terminal number (PIN) of the package library file 21 shown in FIG. The signal section 27_3 is a section for displaying a signal name of a terminal of the semiconductor package.
[0038]
When the template button 26_1 is operated, a template sheet 28 is generated. Here, the contents of the package library file 21 shown in FIG. 2 are displayed on the pad section 27_1, the terminal section 27_2, and the signal section 27_3 of the template sheet 28.
[0039]
The cell part 27_4 is a part for displaying the name of the IO cell connected to the pad of the semiconductor chip.
[0040]
The input / output unit 27_5 is a unit for displaying the input / output attribute of the signal displayed on the signal unit 27_3.
[0041]
The group section 27_6 is a section for displaying a group name of output buffer cells that operate simultaneously.
[0042]
The power supply coefficient unit 27_7 is a part for displaying the accumulated value of the drive coefficient on the power supply side of the output buffer cell (corresponding to an example of the driving capability information according to the present invention).
[0043]
The ground coefficient section 27_8 is a section for displaying the accumulated value of the drive coefficient on the ground side of the output buffer cell (corresponding to another example of the driving capability information according to the present invention). The accumulated values of these drive coefficients will be described later.
[0044]
The message part 27_9 is a part for displaying the operation check result (OK / NG) of the output buffer cells operating simultaneously. The description will be continued with reference to FIG. 1 again.
[0045]
The terminal arrangement sheet editing unit 12 included in the terminal arrangement apparatus 1 shown in FIG. 1 has a function of associating terminals on a semiconductor package with power supply pins, ground pins, and external connection pins of circuit specifications according to the present invention. The terminal arrangement sheet editing unit 12 inputs the signal part 27_3, the cell part 27_4, and the signal part 27_4 of the template sheet 28 shown in FIG. 3 according to the terminal number (or the pad number of the semiconductor chip). A signal name, an IO cell name, and an input / output attribute are assigned to the output unit 27_5. Thus, the template sheet 28 as a template is edited, and the terminal arrangement sheet 22 is generated.
[0046]
FIG. 4 is a diagram showing a terminal arrangement sheet edited and generated by the terminal arrangement sheet editing unit.
[0047]
The signal names N1 to N8 and N9 to N11 assigned to the terminal numbers A2 to A9 and A11 to A13 are displayed on the terminal arrangement sheet 22 shown in FIG. In addition, IO cell names OBT1, OBT2, OBT3, and OBT4 assigned corresponding to the terminal numbers A2 to A5, A6 to A8, A11 to 12, and A13 are displayed. Further, input / output attributes OUT assigned corresponding to the terminal numbers A2 to A9 and A11 to A13 are displayed.
[0048]
Here, the operator operates the group button 26_2. Then, a group name of output buffer cells that operate simultaneously is assigned. In other words, for output signals and bidirectional signals output from terminals corresponding to simultaneously operating output buffer cells, the group names of the output buffer cells are defined.
[0049]
FIG. 5 is a diagram showing a state in which a group name of output buffer cells which operate simultaneously by operating a group button is assigned to the terminal arrangement sheet shown in FIG.
[0050]
The group part 27_6 of the terminal arrangement sheet 22 shown in FIG. 5 includes a group name A for four simultaneously operating output buffer cells OBT1 and a group name B for three simultaneously operating output buffer cells OBT2. A state is shown in which the group name C is assigned to one output buffer cell OBT2, two output buffer cells OBT3, and one output buffer cell OBT4 that operate.
[0051]
The output simultaneous operation group name combination generation unit 13 shown in FIG. 1 has a role of a group designation function according to the present invention, and operates one or more of the groups assigned by operating the group button 26_2. Specify the group according to the operation. Here, all combinations (A, B, C, AB, BC, AC, ABC) of the three groups are specified.
[0052]
Further, the output simultaneous operation terminal number constraint check unit 14 shown in FIG. 1 plays a role of a check function according to the present invention. It is checked whether or not the correspondence with the output pin is a correspondence that matches the predetermined output terminal simultaneous operation restriction. More specifically, the output simultaneous operation terminal number constraint check unit 14 regards that the external output pins belonging to any one or more of the groups specified by the output simultaneous operation group name combination generation unit 13 operate simultaneously. Check.
[0053]
Further, the above-described terminal arrangement sheet editing unit 12 associates the terminal with the power supply pin, the ground pin, and the external connection pin, and further associates the terminal with the external output pin, and further calculates the accumulated value of the drive coefficient. The output concurrently operating terminal number constraint check unit 14 determines the drive coefficient of the output buffer cell further associated with the association between the terminal and the external output pin. The check is performed based on the accumulated value and the correspondence between the terminal, the power supply pin, and the ground pin. Hereinafter, description will be made with reference to FIG.
[0054]
FIG. 6 is a diagram showing a state in which the accumulated values of the drive coefficients are displayed on the terminal arrangement sheet shown in FIG.
[0055]
The drive coefficients of the output buffer cells OBT1, OBT2, OBT3, and OBT4 are defined in the output simultaneous operation rule file 23 shown in FIG. 1, and are 3, 2, 3, and 4, respectively. Between the terminal number A1 and the terminal number A10 in the power supply coefficient section 27_7 of the terminal arrangement sheet 22 shown in FIG. 6, the accumulated value (3, 6, 9) of the power supply side drive coefficient of each output buffer cell OBT1, OBT2 is provided. , 12, 14, 16, 18, and 20) are displayed. In addition, between the terminal number A10 and the terminal number A14 in the power supply coefficient unit 27_7, the accumulated value (3, 6, 10) of the drive coefficient on the power supply side of each of the output buffer cells OBT3 and OBT4 is displayed.
[0056]
Here, the output simultaneous operation terminal number constraint check unit 14 checks (calculates) all combinations of the output simultaneous operation groups, and displays an error (NG) in the following cases.
[0057]
OVDD (OVSS) allowable drive coefficient <Σdrive coefficient of output buffer cell between OVDD (OVSS) / 2
However, OVDD / OVSS indicates the power / ground of the output buffer cell.
[0058]
Here, since OVDD (OVSS) exists on both sides of the output buffer cell to be calculated, the result of addition (accumulated value) is divided by two.
[0059]
The allowable drive coefficient and the drive coefficient of the output buffer cell are defined in the output simultaneous operation rule file 23.
[0060]
FIG. 7 is a diagram showing a terminal arrangement sheet for explaining the calculation by the output simultaneous operation terminal number constraint check unit.
[0061]
The combinations (A, B, C, AB, BC, AC, ABC) of all output simultaneous operation groups are displayed on the terminal arrangement sheet 22 shown in FIG.
[0062]
Here, when the output simultaneous operation group name = ABC is targeted, NG (output simultaneous operation terminal number error) is displayed in the column of the message part (Message) 27_9 of PAD = 10. This output simultaneous operation terminal number error is calculated as follows.
[0063]
As a calculation target, PAD = 2 to 9, PAD where output simultaneous operation group names A, B, or C are defined in output buffer cells arranged on both sides of a power supply of PAD = 10 in the semiconductor chip. = Output buffer cells assigned to 11-13.
[0064]
Here, the allowable drive coefficient of OVDD (spec shown in FIG. 7) is 8 (from the output simultaneous operation rule file 23).
[0065]
The drive coefficient ΣOVDD (val shown in FIG. 7) of the output buffer cell between PAD1 and PAD10 is
ＶOVDD = (drive coefficient of OBT1 × number of OBT1 + drive coefficient of OBT2 × number of OBT2) / 2 + (drive coefficient of OBT3 × number of OBT3 + drive coefficient of OBT4 × number of OBT4) / 2 = 10.
[0066]
Therefore, NG (spec = 8, val = 10) is displayed in a portion corresponding to the PAD 10 in the message portion 27_9. Since the drive coefficient ΣOVDD of the output buffer cell between the PAD 10 and the PAD 14 is 10/2 = 5, OK is displayed in a portion corresponding to the PAD 14 in the message portion 27_9. Further, the drive coefficient ΣOVDD of the output buffer cell between PAD14 and PAD1 is 0, and therefore, OK is displayed in a portion corresponding to PAD1 of message portion 27_9. When NG is displayed (when an error occurs), the power supply / ground is added and the terminal arrangement is changed, and the above calculation is repeated until the error disappears.
[0067]
Then, the circuit port information extraction unit 15 shown in FIG. 1 extracts circuit port information 25 connected to the external connection pin from the circuit data 24.
[0068]
Further, the circuit information comparing unit 16 checks whether the circuit port information 25 matches the terminal assignment information of the terminal arrangement sheet 22, determines whether the number of signals in these files is sufficient or not, and checks whether the IO cell name matches the same signal. A check is made as to whether the input and output attributes match.
[0069]
As described above, the terminal arrangement device 10 of the present embodiment associates the terminal on the semiconductor package with the external connection pin of the logic circuit specification, and associates the terminal with the predetermined output terminal simultaneous operation constraint. Since it is checked whether or not there is, the external connection pins of the logic circuit can be associated with the terminals on the semiconductor package while checking the consistency with the circuit information from the initial stage of circuit design. Therefore, an appropriate terminal arrangement can be performed in consideration of the arrangement of the power supply terminal and the ground terminal and the noise generated due to the simultaneous operation of the plurality of output buffer cells.
[0070]
【The invention's effect】
As described above, according to the terminal arrangement device and the terminal arrangement method of the present invention, terminal arrangement can be performed in consideration of noise generated due to simultaneous operation of a plurality of output buffer cells.
[Brief description of the drawings]
FIG. 1 is a block diagram of a terminal arrangement device according to an embodiment of the present invention.
FIG. 2 is a diagram showing a configuration of a package library file.
FIG. 3 is a diagram showing two fields and a template sheet.
FIG. 4 is a diagram illustrating a terminal arrangement sheet edited and generated by a terminal arrangement sheet editing unit.
5 is a diagram showing a state in which a group name of output buffer cells that operate simultaneously by operating a group button is assigned to the terminal arrangement sheet shown in FIG. 4;
FIG. 6 is a diagram showing a state where accumulated values of drive coefficients are displayed on the terminal arrangement sheet shown in FIG. 5;
FIG. 7 is a diagram showing a terminal arrangement sheet for explaining calculation by a simultaneous output operation terminal number constraint check unit;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Terminal arrangement apparatus 11 Template sheet generation unit 12 Terminal arrangement sheet editing unit 13 Output simultaneous operation group name combination generation unit 14 Output simultaneous operation terminal number constraint check unit 15 Circuit port information extraction unit 16 Circuit information comparison unit 21 Package library file 22 terminals Layout sheet 23 Output simultaneous operation rule file 24 Circuit data 25 Circuit port information 26 First field 26_1 Template button (Template)
26_2 Group Button
26_3 Check button (Check)
27 Second field 27_1 Pad section (PAD)
27_2 Terminal (PIN)
27_3 Signal part (SIGNAL)
27_4 Cell part (CELL)
27_5 Input / output unit (IN / OUT)
27_6 Group (GROUP)
27_7 Power supply coefficient section (OVDD)
27_8 Ground coefficient part (OVSS)
27_9 Message part (Message)
28 Template sheet

Claims (2)

In a terminal arrangement device which associates external connection pins of a logic circuit with terminals on a semiconductor package,
A function for associating terminals on the semiconductor package with power supply pins, ground pins, and external connection pins of circuit specifications,
A check function for checking whether the correspondence between the terminal on the semiconductor package and the external output pin is a correspondence that matches predetermined output terminal simultaneous operation restrictions,
A grouping function for dividing external output pins of the external connection pins of the logic circuit corresponding to the terminals on the semiconductor package into groups of external output pins that operate simultaneously according to an operation;
A group designation function for designating one or more groups among the groups divided by the grouping function according to an operation;
The terminal arrangement device, wherein the check function performs the check by assuming that external output pins belonging to one or more groups specified by the group specification function operate simultaneously. . In a terminal arrangement method for associating external connection pins of a logic circuit with terminals on a semiconductor package,
Associating a power supply pin, a ground pin, and an external connection pin of a circuit specification with a terminal on the semiconductor package;
A check step of checking whether or not the correspondence between the terminal on the semiconductor package and the external output pin is a correspondence that matches predetermined output terminal simultaneous operation constraints;
A grouping step of grouping external output pins of the external connection pins of the logic circuit corresponding to the terminals on the semiconductor package into groups of external output pins that operate simultaneously according to an operation;
A group designation step of designating one or more groups among the groups divided by the grouping step according to an operation;
The terminal arrangement method according to claim 1, wherein the checking step performs the check, assuming that external output pins belonging to one or more groups specified in the group specifying step operate simultaneously. .

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