JP2004304312A - Analog/digital converter and communication apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an analog-digital converter intended to reduce the power consumption, save the size of a circuit area and increase the operating speed. <P>SOLUTION: Only n-channel transistors NM2, NM3 are of a high withstanding voltage type to which an input voltage In and a reference voltage Ref are applied, and other transistors MP1, MP2 are of a low withstanding voltage type. This enables the high speed operation with holding the dynamic range of the analog input high and also the reduction of the circuit area. The A/D converter is provided with a plurality of power sources different in voltage, and a low power voltage among them is fed to a comparator 200 to realize a low power consumption. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an analog / digital converter and a communication device including the analog / digital converter.
[0002]
[Prior art]
The operating speed of a logic circuit can be increased as the size is reduced. In recent years, a technology for miniaturizing a CMOS (Complementary Metal Oxide Semiconductor) element has been developed, and a further increase in operation speed is being attempted. In addition, since the voltage resistance decreases as the size becomes smaller, the power supply voltage of the logic circuit has been reduced. As a result, power consumption can be reduced, and miniaturization of CMOS devices is expected to further advance in the future.
[0003]
On the other hand, since an analog circuit such as an operational amplifier needs to secure a dynamic range of a signal, it is difficult to reduce the operating power supply to a voltage lower than that of a logic circuit. Therefore, an analog circuit is often operated at a higher power supply voltage than a logic circuit. Therefore, in an analog circuit, it is difficult to use a miniaturized element as used in a logic circuit.
[0004]
By the way, in an analog / digital converter (hereinafter, referred to as an A / D converter), an analog circuit and a digital circuit are often mixed on a common semiconductor chip. However, it is difficult to lower the operating voltage of the analog circuit due to the above circumstances. For example, Non-Patent Document 1 below discloses an A / D converter in which an operational amplifier and a comparator are configured by high-voltage transistors that can withstand a power supply voltage of an analog circuit.
[0005]
However, as the operating voltage of the comparator increases, the power consumption increases and the circuit area also increases. Further, the operating speed must be lower than that of a miniaturized low-voltage element.
[0006]
Non-Patent Document 2 below discloses a comparator applicable to an A / D converter.
[0007]
[Non-patent document 1]
A 10-b, 100-MS / s CMOS A / D converter, Kwang Young Kim; Kusayanagi, N.A. Abidi, A .; A. Solid-State Circuits, IEEE Journal of, Volume: 32 Issue: 3, Mar 1997 Page (s): 302-311
[0008]
[Non-patent document 2]
T. B. Cho et al., "A 10b, 20 Msample / s, 35 mW Pipeline A / D Converter", IEEE Journal of Solid-State Circuits, Vol. 30, no. 3, pp166-172, March 1995.
[0009]
[Problems to be solved by the invention]
As described above, in the conventional A / D converter, the operating power supply voltage of the comparator circuit is often higher than the originally required minimum value. For this reason, there is a problem that power consumption increases, a circuit area increases, and an operation speed decreases.
[0010]
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an analog / digital converter and a communication device in which power consumption is reduced, circuit area is reduced, and operation speed is increased. .
[0011]
[Means for Solving the Problems]
In order to achieve the above object, an analog / digital converter according to the present invention outputs an operational amplifier (for example, an operational amplifier 101) and a digital signal by comparing the level of an analog signal output from the operational amplifier with a reference level. A comparison circuit (for example, a comparator 200), a first power supply unit that supplies a first drive voltage (for example, a power supply voltage Vddrop) to the operational amplifier, and a second power supply that is lower than the first drive voltage for the comparison circuit. A second power supply unit for supplying a drive voltage (for example, Vddcomp).
[0012]
With such a configuration, the power supply voltage of the operational amplifier becomes relatively higher than the power supply voltage of the comparison circuit. As a result, the amplitude of the analog signal output from the operational amplifier can be kept large, so that the dynamic range of the signal can be secured. In addition, since the latch provided in the comparison circuit handles a high / low binary signal, the demand for the dynamic range is lower than that of the operational amplifier, and there is a problem even if the power supply voltage of the comparison circuit is lower than the power supply voltage of the operational amplifier. Does not occur. The present invention pays attention to this, and makes the power supply voltage of the comparison circuit lower than the power supply voltage of the operational amplifier. As a result, the power consumption of the comparison circuit can be reduced, and the power consumption of the entire circuit is reduced. It becomes possible to do.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0014]
(1st Embodiment)
FIG. 1 is a circuit block diagram showing a first embodiment of the A / D converter according to the present invention. This A / D converter is realized as an integrated semiconductor chip or the like, and can be suitably used * as, for example, the A / D converters 14-1 and 14-2 in the communication device of FIG. The A / D converter of FIG. 1 includes an input circuit 100 and a comparator 200. The input circuit 100 includes an operational amplifier 101 to which an analog signal is input. The operational amplifier 101 operates under the power supply voltage Vddop.
[0015]
This analog amplified output signal is input to the comparator 200. The comparator 200 operates under the power supply voltage Vddcomp and includes a latch circuit (not shown). Comparator 200 compares the level of the input analog signal with a reference level, and outputs a binary A / D converter output having a level corresponding to power supply voltage Vddcomp.
[0016]
For example, in a pipeline type A / D converter, the input circuit 100 includes a sample / hold circuit. In the ΔΣ A / D converter, the input circuit 100 includes an integrator. In any type of A / D converter, the dynamic range obtained by the operational amplifier 101 greatly affects the accuracy of the entire A / D converter.
[0017]
In this example, the operational amplifier 101 is supplied with a power supply voltage Vddop at a level that can secure a dynamic range necessary for the comparator 200 at the subsequent stage. Further, in this example, the power supply voltage Vddcomp lower than the power supply voltage Vddop of the operational amplifier 101 is applied to the comparator 200. Since the latch circuit of the comparator 200 handles a high / low binary signal, it is generally not required to have a dynamic range as large as that of the operational amplifier 101. For this reason, no problem occurs even if Vddcomp is made lower than Vddop.
[0018]
Further, by setting Vddcomp to be lower than Vddop, power consumption in the comparator 200 can be reduced. Therefore, the power consumption of the entire circuit can be made lower than that of an existing A / D converter in which the power supply voltage of the comparator and the power supply voltage of the operational amplifier 101 are equal.
[0019]
(Second embodiment)
FIG. 2 is a circuit block diagram showing a second embodiment of the A / D converter according to the present invention. This A / D converter includes a logic circuit 300 connected to the output stage of the comparator 200 in FIG. The logic circuit 300 performs processing such as converting the thermometer code output from the comparator 200 into a binary code. That is, the analog input signal that has passed through the input circuit 100 is quantized by the comparator 200, subjected to a process such as code conversion by the logic circuit 300, and converted into a digital output signal.
[0020]
In FIG. 2, the comparator 200 and the logic circuit 300 are connected to a common power supply line and supply the same power supply voltage Vddlogic. Then, the power supply voltage Vddlogic is set lower than the power supply voltage Vddop of the operational amplifier 101. By increasing Vddrop in this manner, a dynamic range of an analog signal can be secured. Further, by making Vddlogic lower than Vddop, power consumed in the comparator 200 and the logic circuit 300 can be reduced.
[0021]
Further, since the same Vddlogic is supplied to the comparator 200 and the logic circuit 300, the signal amplitudes of the comparator 200 and the logic circuit 300 are both equal. This eliminates the need for a level conversion circuit for matching the two, as compared with an existing A / D converter that operates only the logic circuit 300 at a low power supply voltage. Therefore, power consumption can be further reduced, and the circuit scale can be reduced.
[0022]
<First Circuit Configuration Example>
FIG. 3 is a diagram showing a first circuit configuration example of the comparator 200 shown in FIG. 1 or FIG. In FIG. 3, the voltage of the power supply voltage Vddcomp is connected to a lower voltage side among a plurality of power supplies provided in the A / D converter.
[0023]
In FIG. 3, an analog input signal is input to a gate terminal In of an N-channel transistor MN2, and a reference voltage is input to a gate terminal Ref of an N-channel transistor MN3. The P-channel transistors MP1 and MP2 are connected to the loads of the N-channel transistors MN2 and MN3, respectively. P-channel transistors MP1 and MP2 constitute a latch. An N-channel transistor MN1 is connected to the drains of the N-channel transistors MN2 and MN3, and supplies a clock signal Ck to the gate of the N-channel transistor MN1.
[0024]
In such a configuration, when the clock signal Ck becomes High, the N-channel transistor MN1 is turned on. At this time, since the drains of the P-channel transistors MP1 and MP2 are commonly connected, the P-channel transistors MP1 and MP2 do not operate as a latch, and the outputs Outp and Outn have the same potential. That is, when the clock signal Ck is High, the reset mode is set.
[0025]
When the clock signal Ck goes low, the P-channel transistors MP1 and MP2 operate as latches. Therefore, when the input voltage In is higher than the reference voltage Ref, the output Outp is High and the output Outn is Low. When the input voltage In is lower than the reference voltage Ref, Outp is Low and Outn is High. Thus, the period in which the clock signal Ck is Low is the comparison mode.
[0026]
In the present embodiment, a high breakdown voltage transistor is used as the transistors MN2 and MN3 to which the input voltage In and the reference voltage Ref are applied. Thus, the voltages of the analog input signal and the reference signal can be increased without any trouble.
[0027]
On the other hand, the transistors other than these, that is, the sources of P-channel transistors MP1 and MP2 are connected to a power supply line having power supply voltage Vddcomp. Since Vddcomp is lower than the input voltage In and the reference voltage Ref, low-breakdown-voltage P-channel transistors MP1 and MP2 can be used. In general, the element size of a low withstand voltage transistor can be smaller than that of a high withstand voltage type transistor, and higher speed operation is possible. Thus, the size of the comparator 200 on the chip can be reduced, and high-speed operation can be realized.
[0028]
As described above, in this example, only the N-channel transistors NM2 and NM3 to which the input voltage In and the reference voltage Ref are applied are of the high withstand voltage type, and the other transistors MP1 and MP2 are of the low withstand voltage type. As a result, high-speed operation can be performed while keeping the dynamic range of the analog input signal high, and the circuit area can be reduced. Furthermore, a plurality of power supplies having different voltages are provided in the A / D converter, and a low power supply voltage is supplied to the comparator 200, whereby low power consumption can be realized.
[0029]
<Second circuit configuration example>
FIG. 4 is a diagram showing a second circuit configuration example of the comparator 200 shown in FIG. 1 or FIG. In this example, as in FIG. 3, the power supply voltage Vddcomp is connected to the lower voltage side of the plurality of power supplies of the A / D converter.
[0030]
In FIG. 4, the sources of the P-channel transistors MP3 and MP4 are connected together to the supply path of the power supply voltage Vddcomp, and the drains are connected to each other to take out the output Outn. Similarly, the sources of the P-channel transistors MP5 and MP6 are connected to the supply path of the power supply voltage Vddcomp, and the drains are connected to each other to take out the output Outp.
[0031]
The output Outn is connected to the drain of the N-channel transistor MN5 and the gates of the P-channel transistors MP5 and MN7 of the N-channel transistor. The output Outp is connected to the drain of the N-channel transistor MN8 and the gates of the P-channel transistors MP4 and MN6 of the N-channel transistor. The source of N-channel transistor MN5 is connected to the drain of N-channel transistor MN6, and the source of N-channel transistor MN8 is connected to the drain of N-channel transistor MN7. The source of N-channel transistor MN6 is connected to the drains of N-channel transistors MN1 and MN2. The source of N-channel transistor MN7 is connected to the drains of N-channel transistors MN3 and MN4. The sources of the N-channel transistors MN1, MN2, MN3, MN4 are all grounded.
[0032]
The clock signal Ck is supplied to the gates of the P-channel transistors MP3 and MP6 and the N-channel transistors MN5 and MN8. The input voltages Inp and Inn are applied to the gates of the N-channel transistors MN2 and MN3, respectively, and the reference voltages Refn and Refp are applied to the gates of the N-channel transistors MN1 and MN4, respectively.
[0033]
In the above configuration, the transistors MN1 to MN4 to which the input voltages Inp and Inn and the reference voltages Refp and Refn are input are of a high withstand voltage type, and the other transistors MP3 to MP6 and MN5 to MN8 are of a low withstand voltage type.
[0034]
When the transistors MN1 to MN4 are all operated in the linear region, and when the equivalent parallel resistance of the transistors MN1 and MN2 is lower than the equivalent parallel resistance of MN3 and MN4, Outp is High and Outn is Low at the rise of the clock signal Ck. Become.
[0035]
With the above configuration, the comparator 200 of this example can compare the differential input signals Inp, Inn with the differential reference voltages Refp, Refn. Also, by appropriately adjusting the size ratio between the transistors MN1 and MN2 and between the transistors MN3 and MN4, the equivalent parallel resistance can be adjusted. That is, the comparison voltage of the comparator 200 can be adjusted by the size of the transistor. Thus, even when a multi-bit A / D converter is configured using a plurality of comparators 200, there is an advantage that only one type of reference voltage Refp and Refn is required. The details of the operation of the comparator 200 in this example are described in detail in Non-Patent Document 2.
[0036]
As described above, also in this example, similarly to the first circuit configuration example, only the N-channel transistors NM1 to NM4 to which the input voltages Inp, Inn and the reference voltages Refp, Refn are applied are of the high withstand voltage type, and the other transistors are of the low withstand voltage type. Pressure-resistant type. As a result, high-speed operation can be performed while keeping the dynamic range of the analog input signal high, and the circuit area can be reduced. Furthermore, a plurality of power supplies having different voltages are provided in the A / D converter, and a low power supply voltage is supplied to the comparator 200, whereby low power consumption can be realized.
[0037]
(Third embodiment)
FIG. 5 is a circuit block diagram showing a third embodiment of the A / D converter according to the present invention. The A / D converter in FIG. 5 is a simple A / D converter that realizes most of its functions by a comparator 200, for example, a flash A / D converter. The comparator 200 includes a preamplifier 201 and a latch 202. The preamplifier 201 is used to increase the sensitivity of the comparator 200 or to prevent the charge generated in the latch 202 from flowing back to the input side.
[0038]
In the A / D converter of this example, the power supply voltage Vddlatch of the latch 202 is set lower than the power supply voltage Vddpre of the preamplifier 201. By increasing the power supply voltage Vddpre of the preamplifier 201, a dynamic range of an analog signal can be secured. In addition, since the dynamic range of the latch 202 is not required to be as high as that of the preamplifier 201, the power supply voltage Vddlatch of the latch 202 can be lowered without any trouble from the power supply voltage Vddpre of the preamplifier 201. Thereby, power consumption can be reduced.
[0039]
(Fourth embodiment)
FIG. 6 is a circuit block diagram showing a fourth embodiment of the A / D converter according to the present invention. This A / D converter includes a logic circuit 300 connected to the output stage of the latch 202 in FIG.
[0040]
In FIG. 6, the latch 202 and the logic circuit 300 are connected to a common power supply line to supply the same power supply voltage Vddlogic. Then, the power supply voltage Vddlogic is set lower than the power supply voltage Vddpre of the preamplifier 201. By increasing Vddpre in this manner, a dynamic range of an analog signal can be secured. Further, by making Vddlogic lower than Vddpre, power consumed in the latch 202 and the logic circuit 300 can be reduced.
[0041]
<Third Circuit Configuration Example>
FIG. 7 is a diagram showing a circuit configuration example of the preamplifier 201 and the latch 202 shown in FIG. 5 or FIG. This configuration can be applied to an A / D converter that supplies two types of power to the comparator 200. 7, the power supply voltage Vddlatch of the latch 202 is lower than the power supply voltage Vddpre of the preamplifier 201.
[0042]
In FIG. 7, differential input signals Inn and Inp are input to P-channel transistors MP1 and MP4 of the preamplifier 201, and differential reference voltages Refn and Refp are input to MP2 and MP3. The differential output voltage (Outp_pre-Outn_pre) of the preamplifier 201 becomes positive when the differential input signal voltage (Inp, Inn) is higher than the differential reference voltage (Refp, Refn), and becomes negative when the differential input signal voltage is lower than the differential reference voltage (Refp, Refn). Input to MN1 and MN2.
[0043]
The latch 202 includes a P-channel latch and an N-channel latch, and the comparison operation is performed at the falling edge of the clock signal Ck. When the differential input signal (Inp, Inn) is higher than the differential reference voltage (Refp, Refn), Outp becomes High and Outn becomes Low. By using two pairs of differential pairs for the preamplifier 201, it is possible to compare a differential input pair with a differential reference voltage. In addition, by using two sets of P-channel and N-channel latch circuits for the latch 202, high-speed operation becomes possible.
[0044]
In this example, all transistors constituting the preamplifier 201 and the input transistors MN1 and MN2 of the latch 202 are of a high withstand voltage type, and the other transistors are of a low withstand voltage type.
[0045]
By using a high-voltage transistor for the preamplifier 201, the dynamic range of an analog input signal can be kept high. In addition, by using a low breakdown voltage transistor for the latch 202, it is possible to increase operation speed, reduce size, and reduce power consumption. Further, the power consumption can be further reduced by setting the power supply voltage Vddlatch of the latch 202 lower than the power supply voltage Vddpre of the preamplifier 201.
[0046]
In this example, low breakdown voltage transistors can be used for transistors other than the transistors MP1 to MP4 in the preamplifier 201 depending on the design of the power supply voltage and the bias voltage of each unit. In such a case, it is more advantageous to use a low breakdown voltage transistor in terms of operation speed as much as possible.
[0047]
Note that the present invention is not limited to the above embodiment. For example, in FIG. 2, the comparator 200 and the logic circuit 300 are connected to a common power supply line. In short, if the drive voltage Vddlogic of the comparator 200 and the logic circuit 300 is lower than Vddop, power can be supplied individually. good. Similarly, in FIG. 6, the latch 202 and the logic circuit 300 are connected to a common power supply line. In short, if the drive voltage Vddlogic of the latch 202 and the logic circuit 300 is lower than Vddpre, power is supplied individually to each of them. Is also good.
[0048]
Further, the circuits shown in FIGS. 3 and 4 are not limited to those shown in FIGS. 1 and 2, but in short, what kind of A / D converter is of the type that supplies power to the comparator 200 through a single power supply line. It is also applicable to a D converter.
[0049]
Further, the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements in an implementation stage without departing from the scope of the invention. For example, this A / D converter can be used for a communication device.
[0050]
FIG. 8 is a block diagram showing an embodiment of a communication device including an A / D converter according to the present invention. This communication apparatus is applied to a system employing a multi-level QAM modulation scheme such as 64QAM or 256QAM. This communication device includes an antenna 40, a receiving device 10, and a control unit 19. The receiving device 10 includes a high-frequency receiving circuit (RF / IF) 12, a quadrature demodulator 13, A / D converters 14-1 and 14-2, and a digital signal processing unit 15.
[0051]
The QAM modulated signal arriving at the antenna 40 is filtered and low-noise-amplified in a high-frequency receiving circuit (RF / IF) 12, frequency-converted, and converted to an intermediate frequency signal. This intermediate frequency signal is subjected to filtering processing, AGC processing, and the like, and is input to the quadrature demodulator 13.
[0052]
The intermediate frequency signal supplied to the quadrature demodulator 13 is quadrature-demodulated, and a mutually orthogonal I-channel (I-ch) and Q-channel (Q-ch) complex baseband signal is output. The baseband signals of each channel are input to A / D converters 14-1 and 14-2, respectively, and are converted into digital signals. The digital signal of each channel is input to the digital signal processing unit 15 and received and demodulated.
[0053]
By applying the A / D converters described in the above embodiments as the A / D converters 14-1 and 14-2 in the communication device having such a configuration, the power consumption of the entire communication device can be reduced, and It is possible to promote size reduction.
[0054]
Various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiment. Further, components of different embodiments may be appropriately combined.
[0055]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to provide an analog-to-digital converter and a communication device in which power consumption is reduced, circuit area is reduced, and operation speed is increased.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram showing a first embodiment of an A / D converter according to the present invention.
FIG. 2 is a circuit block diagram showing a second embodiment of the A / D converter according to the present invention.
FIG. 3 is a diagram showing a first circuit configuration example of a comparator 200 shown in FIG. 1 or FIG. 2;
FIG. 4 is a diagram showing a second circuit configuration example of the comparator 200 shown in FIG. 1 or FIG. 2;
FIG. 5 is a circuit block diagram showing a third embodiment of the A / D converter according to the present invention.
FIG. 6 is a circuit block diagram showing a fourth embodiment of the A / D converter according to the present invention.
FIG. 7 is a diagram showing a circuit configuration example of a preamplifier 201 and a latch 202 shown in FIG. 5 or FIG.
FIG. 8 is a block diagram illustrating an embodiment of a communication device including an A / D converter according to the present invention.
[Explanation of symbols]
MN1 to MN8 N-channel transistors, MP1 to MP4 P-channel transistors, 10 receiving device, 12 high-frequency receiving circuit, 13 quadrature demodulator, 14 D converter, 15 digital signal processing unit, 19 control unit , 40 antenna, 100 input circuit, 101 operational amplifier, 200 comparator, 201 preamplifier, 202 latch, 300 logic circuit

Claims (4)

An operational amplifier,
A comparison circuit that compares an analog signal output from the operational amplifier with a reference level and outputs a digital signal;
A first power supply unit for supplying a first drive voltage to the operational amplifier;
A second power supply unit for supplying a second drive voltage lower than the first drive voltage to the comparison circuit. A comparison circuit having a latch circuit and a preamplifier connected to a stage preceding the latch circuit, and comparing the analog signal with a reference level to output a digital signal;
A first power supply for supplying a first drive voltage to the preamplifier;
A second power supply unit for supplying a second drive voltage lower than the first drive voltage to the latch circuit. 3. The analog / digital converter according to claim 1, further comprising a logic circuit to which the digital signal is input and receives power supply from the second power supply unit. 4. At least one of the analog / digital converters provided in a communication device for digitizing an analog received signal and then demodulating the received signal is constituted by the analog / digital converter according to any one of claims 1 to 3. Communication device.

Images