JP2004303988A - Semiconductor storage device and method of manufacturing the same - Google Patents

Abstract

The present invention provides a semiconductor memory device and a method of manufacturing the same capable of achieving a high integration by realizing a stable reduction of an electrode arrangement pitch in a cross-point type FeRAM.
An underlayer barrier insulating film is provided on a predetermined layer on a semiconductor substrate. A lower electrode 12 is formed on the insulating film 11. An interlayer insulating film 13 covering the lower electrode 12 is formed. The ferroelectric film 14 is embedded in an opening of the interlayer insulating film 13 reaching a predetermined region of the lower electrode 12. Thus, the ferroelectric film 13 does not depend on the etching shape of the lower electrode 12. An upper electrode 15 is provided on the interlayer insulating film 13 so as to intersect with the lower electrode 12 including on the ferroelectric film 13.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention particularly relates to a semiconductor memory device having a cross-point type FeRAM (Ferroelectric Random Access Memory) cell and a method of manufacturing the same.
[0002]
[Prior art]
An FeRAM, a so-called ferroelectric memory, is one of the non-volatile memories having high speed, low power consumption, high integration, and excellent rewriting resistance. The ferroelectric memory can perform high-speed rewriting using the hysteresis characteristic of the ferroelectric thin film, that is, high-speed polarization inversion and its remanent polarization. In particular, a cross-point type FeRAM has a configuration in which memory cells having a structure in which a lower electrode and an upper electrode intersect via a ferroelectric thin film are arranged in a matrix, and is excellent in high integration.
[0003]
FIG. 11 is a sectional view showing a part of a memory cell part in a conventional cross-point type FeRAM. An underlying barrier insulating film, for example, a silicon nitride film 101 is formed in a predetermined layer on a semiconductor substrate. The lower electrode 102 is formed on the silicon nitride film 101 in a stripe shape. Above the lower electrode 102, an upper electrode 104 is formed in a stripe shape so as to intersect. A ferroelectric thin film 103 is disposed between the lower electrode 102 and the upper electrode 104, and a memory cell structure in which the intersecting regions of the two electrodes are arranged in a matrix form constitutes a memory section 105.
[0004]
In the cross-point type FeRAM, the relationship between the sub-bit line potential of the lower electrode 102 and the word line potential of the upper electrode 104 is controlled so that the ferroelectric capacitors each having the ferroelectric thin film 103 are moved in a predetermined applied electric field direction. Polarize. The selected memory cell has a sub-bit line potential corresponding to the polarization state of the ferroelectric capacitor, and is transmitted to a selection transistor and a bit line (not shown). Such a cross-point type FeRAM is disclosed in Patent Document 1, for example.
[0005]
[Patent Document 1]
JP-A-9-116107 (pages 5 to 10)
[0006]
[Problems to be solved by the invention]
Regarding the memory cell structure, the upper electrode 104 and the lower electrode 102 are generally formed of Pt. When etching Pt, chemical reaction etching cannot be used, and a rimming process of physically etching with inert atoms or the like is used. Therefore, the shape after the etching becomes a tapered shape. Therefore, it is difficult to control the arrangement pitch of the lower electrodes 102. Further, the ferroelectric film 103 also inherits the tapered shape during the etching process. As a result, there is a problem that the electrodes that can be effectively used as capacitors are reduced.
[0007]
According to the above configuration, it is difficult to control the arrangement pitch of the lower electrodes 102, and it is difficult to further increase the integration. Further, with the increase in integration, it is desired to increase the size of an electrode that can be effectively used as a capacitor. However, since the ferroelectric film 103 also inherits the tapered shape at the time of the etching, there is a problem that the electrode becomes smaller.
[0008]
The present invention has been made in view of the above circumstances, and realizes a semiconductor memory device capable of realizing a stable reduction of an electrode array pitch in a cross-point type FeRAM and achieving high integration, and a method of manufacturing the same. It is intended to provide.
[0009]
[Means for Solving the Problems]
A semiconductor device according to the present invention includes a planarized underlying insulating film provided on a predetermined layer on a semiconductor substrate, a lower electrode on the insulating film, and an interlayer insulating film covering the lower electrode,
A ferroelectric film buried in an opening of the interlayer insulating film reaching a predetermined region of the lower electrode; and a ferroelectric film provided on the interlayer insulating film so as to intersect the lower electrode including the ferroelectric film. And an upper electrode provided.
[0010]
The semiconductor device according to the present invention may further include a planarized underlying insulating film provided on a predetermined layer on the semiconductor substrate, a lower electrode on the insulating film, an interlayer insulating film covering the lower electrode, A ferroelectric film provided on a predetermined region of the lower electrode, and an upper electrode provided on the interlayer insulating film so as to intersect the lower electrode including on the ferroelectric film, at least the Regarding the ferroelectric film, the cross-sectional shape of the lower electrode in the direction of extension shows a rectangle according to the first processing, and the cross-sectional shape of the upper electrode in the direction of extension shows a trapezoid according to the second processing. It is characterized by.
[0011]
According to the semiconductor device according to the present invention, the cross-sectional shape of the ferroelectric film is not simply a forward tapered shape, and a configuration in which the cross-sectional area is increased is possible. This is a mode that contributes to reduction of the arrangement pitch of the electrodes.
[0012]
In the method of manufacturing a semiconductor device according to the present invention, a step of forming a planarized underlying insulating film provided on a predetermined layer on a semiconductor substrate, and forming a first metal film serving as a lower electrode on the insulating film Forming a second metal film on the first metal film, forming a first mask pattern on the second metal film, and forming the second metal film according to the first mask pattern. An etching step for selectively removing a film and the first metal film, a step of forming an interlayer insulating film covering the shapes of the first metal film and the second metal film after the etching step, and a step of forming the second metal film Flattening the interlayer insulating film exposing the upper surface of the semiconductor device, removing the second metal film, embedding a ferroelectric film in at least a removed portion of the second metal film, And an upper electrode on the interlayer insulating film. Forming a third metal film, forming a second mask pattern on the third metal film, and selectively forming the third metal film and the ferroelectric film according to the second mask pattern. And an etching step of removing the substrate.
[0013]
The method of manufacturing a semiconductor device according to the present invention includes the step of burying a ferroelectric film at least in a portion where the second metal film is removed. By selecting a material having better workability as the second metal film, a better shape of the ferroelectric film can be obtained. The processing of the first metal film is also easy. As a result, the cell array pitch of the memory unit is improved in a direction to be reduced.
[0014]
In the method of manufacturing a semiconductor device according to the present invention, a step of forming a planarized underlying insulating film provided on a predetermined layer on a semiconductor substrate, and forming a first metal film serving as a lower electrode on the insulating film Performing a step of forming a processing film on the first metal film; forming a first mask pattern on the processing film; and forming the processing film and the processing medium in accordance with the first mask pattern. An etching step of selectively removing the first metal film, a step of forming an interlayer insulating film covering the shapes of the first metal film and the processing film after the etching step, and exposing an upper surface of the processing film A step of flattening the interlayer insulating film, a step of removing the processing film, a step of embedding a ferroelectric film at least in a removed portion of the processing film, and a step of forming a layer on the ferroelectric film and the interlayer insulating film. Second metal to be the upper electrode Forming a second mask pattern on the second metal film; and etching the second metal film and the ferroelectric film selectively according to the second mask pattern. And characterized in that:
[0015]
The method of manufacturing a semiconductor device according to the present invention includes the step of embedding a ferroelectric film at least in a removed portion of the processing film. By selecting a film for processing excellent in workability, a better shape of the ferroelectric film can be obtained. The processing of the first metal film is also easy. As a result, the cell array pitch of the memory unit is improved in a direction to be reduced.
In the method for manufacturing a semiconductor device according to the present invention, a film having a barrier function for at least the lower electrode is selected as the base insulating film.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention, and showing a part of a memory portion in a cross-point type FeRAM.
An insulating film 11 for a base barrier which is flattened on a predetermined layer on a semiconductor substrate is provided. A lower electrode 12 is formed on the insulating film 11. An interlayer insulating film 13 covering the lower electrode 12 is formed. The ferroelectric film 14 is embedded in an opening of the interlayer insulating film 13 reaching a predetermined region of the lower electrode 12. Thus, the ferroelectric film 13 does not depend on the etching shape of the lower electrode 12. An upper electrode 15 is provided on the interlayer insulating film 13 so as to intersect with the lower electrode 12 including on the ferroelectric film 13.
[0017]
According to the above embodiment, the cross-sectional shape of the ferroelectric film 14 is not simply a forward tapered shape, and a configuration that increases the cross-sectional area is possible. This will be described below.
2 to 6 are cross-sectional views showing the main parts of a manufacturing process for realizing the configuration of FIG. The same parts as those in FIG. 1 are denoted by the same reference numerals.
As shown in FIG. 2, a planarized base insulating film 11 provided on a predetermined layer on a semiconductor substrate is formed. The insulating film 11 is a barrier insulating film, for example, a silicon nitride film. Next, a metal film 21 to be the lower electrode 12 and a metal film 22 for processing are formed on the insulating film 11. The metal film 21 is, for example, Pt, and is formed to a thickness of about 100 nm by a sputtering method. The metal film 22 for processing is, for example, TiN, and is formed to a thickness of about 100 nm by a sputtering method. A resist pattern 23 is formed on the metal film 22 using a photolithography technique.
[0018]
Next, as shown in FIG. 3, the metal film 22 and the metal film 21 are etched according to the resist pattern 23. The metal film 21 made of Pt is mainly subjected to sputter etching, and the side portion has a form including a tapered shape.
Next, as shown in FIG. 4, an interlayer insulating film 13 is deposited and planarized by using a CMP (chemical mechanical polishing) technique. The planarization ends when the exposure of the metal film 22 is detected.
Next, as shown in FIG. 5, the metal film 22 is removed by etching. The metal film 22 made of TiN can be etched with a somewhat high temperature (about 60 ° C.) chemical solution for RCA cleaning, for example, a mixed solution of ammonia and hydrogen peroxide. Thereby, a groove 24 having the metal film 21 at the bottom is formed.
[0019]
Next, as shown in FIG. 6, a ferroelectric film is spin-coated using a sol-gel method and baked. Various types of ferroelectric films are conceivable. For example, a ferroelectric film is selected from a PZT (Pb (Zr, Ti) O ₃ ) -based compound and a Bi-based compound having a layered structure (SBT (SrBi ₂ Ta ₂ O ₉ )). adopt. Thus, the ferroelectric film 14 embedded in the groove 24 appears. If planarization is required, planarization is performed using a CMP (chemical mechanical polishing) technique.
Next, as shown in FIG. 7, a metal film 25 serving as an upper electrode is formed on the interlayer insulating film 13 including the ferroelectric film 14. The metal film 25 is, for example, Pt and is formed to a thickness of about 100 nm by a sputtering method. Thereafter, the upper electrode 15 is formed by patterning, and the structure shown in FIG. 1 is obtained.
[0020]
According to the above-described embodiment and method, the step of embedding the ferroelectric film 14 in at least the removed portion of the processing metal film 22 is provided. By selecting a metal film 22 having better workability, a better shape of the ferroelectric film 14 can be obtained. Further, the metal film 21 serving as the lower electrode (Pt) can be easily processed. As a result, the cell array pitch of the memory unit is improved in a direction to be reduced.
[0021]
The metal film 22 for processing is not limited to TiN, and a metal film having good workability can be used. Further, a processing film other than a metal film may be used.
FIGS. 8 to 10 are cross-sectional views corresponding to FIGS. 2 to 4, in which a processing film 32 that is not a metal film is used in place of the processing metal film 22. The film 32 for processing is, for example, a SiN film, and can be selectively removed as shown in FIG. 5 by immersing it in an etching solution of hot phosphoric acid (about 120 ° C.).
[0022]
As described above, according to the present invention, a step of embedding a ferroelectric film at least in a removed portion of a processing film is provided. By selecting a film for processing excellent in workability, a better shape of the ferroelectric film can be obtained. As a result, the cell array pitch of the memory unit is improved in a direction to be reduced. As a result, it is possible to provide a semiconductor memory device capable of stably reducing the electrode array pitch in a cross-point type FeRAM and achieving high integration, and a method of manufacturing the same.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention, showing a part of a memory portion in a cross-point type FeRAM.
FIG. 2 is a first sectional view showing an intermediate step for realizing the configuration of FIG. 1;
FIG. 3 is a second sectional view following FIG. 2;
FIG. 4 is a third sectional view following FIG. 3;
FIG. 5 is a fourth sectional view following FIG. 4;
FIG. 6 is a fifth sectional view following FIG. 5;
FIG. 7 is a sixth sectional view following FIG. 6;
FIG. 8 is a sectional view showing another example corresponding to FIG. 2;
FIG. 9 is a sectional view showing another example corresponding to FIG. 3;
FIG. 10 is a sectional view showing another example corresponding to FIG. 4;
FIG. 11 is a cross-sectional view showing a part of a memory cell part in a conventional cross-point type FeRAM.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Insulating film, 12 ... Lower electrode, 13 ... Interlayer insulating film, 14 ... Ferroelectric film, 15 ... Upper electrode, 21, 25 ... Metal film, 22 ... Metal film for processing, 23 ... Resist pattern, 24 ... Grooves, 32 ... Processing film.

Claims (5)

A planarized underlying insulating film provided on a predetermined layer on the semiconductor substrate,
A lower electrode on the insulating film;
An interlayer insulating film covering the lower electrode,
A ferroelectric film embedded in an opening of the interlayer insulating film reaching a predetermined region of the lower electrode,
An upper electrode provided on the interlayer insulating film so as to intersect the lower electrode including on the ferroelectric film;
A semiconductor memory device comprising: A planarized underlying insulating film provided on a predetermined layer on the semiconductor substrate,
A lower electrode on the insulating film;
An interlayer insulating film covering the lower electrode,
A ferroelectric film provided on at least a predetermined region of the lower electrode,
An upper electrode provided on the interlayer insulating film so as to intersect the lower electrode including on the ferroelectric film;
With
At least with respect to the ferroelectric film, the cross-sectional shape of the lower electrode in the extension direction shows a rectangle corresponding to the first processing, and the cross-sectional shape of the upper electrode in the extension direction shows a trapezoid corresponding to the second processing. A semiconductor memory device characterized in that: Forming a planarized underlying insulating film provided on a predetermined layer on the semiconductor substrate;
Forming a first metal film serving as a lower electrode on the insulating film;
Forming a second metal film on the first metal film;
Forming a first mask pattern on the second metal film;
An etching step of selectively removing the second metal film and the first metal film according to the first mask pattern;
Forming an interlayer insulating film covering the shapes of the first metal film and the second metal film after the etching process;
Flattening the interlayer insulating film exposing an upper surface of the second metal film;
Removing the second metal film;
Embedding a ferroelectric film at least in a removed portion of the second metal film;
Forming a third metal film to be an upper electrode on the ferroelectric film and the interlayer insulating film;
Forming a second mask pattern on the third metal film;
An etching step of selectively removing the third metal film and the ferroelectric film according to the second mask pattern;
A method for manufacturing a semiconductor memory device, comprising: Forming a planarized underlying insulating film provided on a predetermined layer on the semiconductor substrate;
Forming a first metal film serving as a lower electrode on the insulating film;
Forming a processing film on the first metal film;
Forming a first mask pattern on the processing film;
An etching step of selectively removing the processing film and the first metal film according to the first mask pattern;
Forming an interlayer insulating film covering the shapes of the first metal film and the processing film after the etching process;
Flattening the interlayer insulating film exposing the upper surface of the processing film;
Removing the processing film;
Embedding a ferroelectric film in at least the removed portion of the processing film;
Forming a second metal film to be an upper electrode on the ferroelectric film and the interlayer insulating film;
Forming a second mask pattern on the second metal film;
An etching step of selectively removing the second metal film and the ferroelectric film according to the second mask pattern;
A method for manufacturing a semiconductor memory device, comprising: 5. The method for manufacturing a semiconductor device according to claim 3, wherein a film having a barrier function for at least the lower electrode is selected as the base insulating film.

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