JP2004297993A - Motor drive, the motor drive methodology, and integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the inferiority of starting a sensor-less motor, by eliminating the problem that a beat lock is difficult to be prevented only by making a partial mask of a zero-cross detection range of the motor driving gear. <P>SOLUTION: The motor driving gear having a signal processing circuit for driving the sensor-less motor is provided with a detection means for detecting whether a zero-cross of back electromotive voltage generated in a drive coil of the sensor-less motor and neutral point voltage are in the prescribed timing or not; a counting means being reset based on an output of the detection means when the zero-cross is in the prescribed timing and performing counting based on an output of the detection means when the zero-cross is not in the prescribed timing; a brake means performing braking till the sensor-less motor is stopped based on an output when the counting means counts the prescribed value; and a start indicating means performing indication of the signal processing circuit for starting the sensor-less motor after it is stopped. In this way, inferiority of starting the sensor-less motor is surely detected, so as to make it surely capable of starting. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a motor driving device, a motor driving method, and an integrated circuit.
[0002]
[Prior art]
Since the sensorless motor (spindle motor, thread motor, etc.) has a structure that does not have a position detecting element (for example, a Hall element) for detecting a relative position between the rotor and the stator, the following driving method is required. For example, a motor driving device that drives a sensorless motor having a multi-phase drive coil has a multi-phase drive coil in an appropriate order based on a zero crossing of a back electromotive voltage and a neutral point voltage generated in a predetermined phase drive coil. To generate a timing signal for energizing in an appropriate direction, thereby controlling on / off of the driving transistor for energizing the driving coil. As a result, the sensorless motor rotates in a predetermined direction.
[0003]
By the way, when the motor drive device erroneously detects a zero cross, which is a reference when driving the sensorless motor, due to the influence of noise or the like, it cannot create an optimal timing signal for energizing the multi-phase drive coils. In this case, the sensorless motor cannot rotate because no torque is generated. If the above state continues, it appears that the motor driving device is energizing the multi-phase drive coils so that the sensorless motor rotates at a high speed, even though the sensorless motor is stopped. Defective). Therefore, conventionally, erroneous detection of the zero cross has been prevented by partially masking the zero cross detection range of the motor driving device.
[0004]
[Patent Document 1]
JP-A-11-4595
[Problems to be solved by the invention]
However, the timing for partially masking the zero-cross detection range of the motor driving device is based on the zero-cross. In other words, once the zero crossing is erroneously detected by the motor driving device, it becomes impossible to create an optimal timing for the mask, and thus the sensorless motor causes a beat lock phenomenon. Therefore, it is difficult to prevent beat lock only by partially masking the zero-cross detection range of the motor driving device.
[0006]
[Means for Solving the Problems]
The invention for solving the above-mentioned problem is directed to a motor driving device having a signal processing circuit for driving a sensorless motor, wherein a zero crossing of a back electromotive voltage and a neutral point voltage generated in a driving coil of the sensorless motor is performed at a predetermined timing. Detecting means for detecting whether or not there is, and resetting based on an output of the detecting means when the zero cross is at a predetermined timing, and counting based on an output of the detecting means when the zero cross is not at a predetermined timing. Counting means for performing the following, based on an output when the counting means has counted a predetermined value, braking means for performing braking until the sensorless motor stops, and after the sensorless motor stops, the signal processing circuit Starting instruction means for issuing an instruction for activating the sensorless motor. It is over motor drive unit. According to this motor drive device, it is possible to reliably detect whether or not the sensorless motor has a beatlock phenomenon, using the absolute predetermined value counted by the counting means as the threshold value. Further, when the sensorless motor has a beatlock phenomenon, the sensorless motor is stopped and then restarted, so that the sensorless motor can be reliably returned from the beatlock state to the normal state.
[0007]
In this motor drive device, the braking unit turns on the drive transistor that energizes the drive coil at a timing at which the back electromotive voltage of the drive coil is attenuated. According to this motor drive device, step-out of the sensorless motor can be effectively prevented.
[0008]
In this motor drive device, the predetermined timing is in a range from a zero cross, which should originally occur, to a predetermined time before. According to this motor driving device, even when the sensorless motor causes a load change or the like, the zero cross can be reliably detected.
[0009]
Further, in such a motor drive device, the start instruction means has a counter for detecting the zero cross and starting counting, and when the counter has counted a predetermined value, the signal processing circuit sends the sensorless motor to the signal processing circuit. Give instructions to start. According to this motor drive device, since the sensorless motor is stopped for a predetermined time and then restarted, the sensorless motor can be effectively returned from the beat lock state to the normal state.
[0010]
In this motor drive device, the sensorless motor has a multi-phase drive coil.
[0011]
A method of driving a motor drive device having a signal processing circuit for driving a sensorless motor, the method comprising: determining whether a zero cross of a back electromotive voltage and a neutral point voltage generated in a drive coil of the sensorless motor is at a predetermined timing. Detecting, and resetting when detecting that the zero cross is at a predetermined timing, performing counting when detecting that the zero cross is not at a predetermined timing, when counting a predetermined value, A motor driving method, comprising: braking until the sensorless motor stops; and, after the sensorless motor stops, the signal processing circuit instructs to start the sensorless motor. It is. According to this motor driving method, the sensorless motor can be reliably returned from the beat lock state to the normal state.
[0012]
Further, there is provided an integrated circuit in which the above motor drive device is integrated. According to this integrated circuit, it is possible to cope with a small device using a sensorless motor.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
At least the following matters will be made clear by the description in the present specification and the accompanying drawings.
[0014]
=== Overall configuration of motor drive device ===
The overall configuration according to the present invention will be described with reference to FIG. 1, FIG. 2, FIG. 3, and FIG. FIG. 1 is a configuration diagram for explaining a motor drive device of the present invention. FIG. 2 is a waveform diagram for explaining the operation of the motor drive device of the present invention. FIG. 3 is a waveform diagram for explaining the operation of the mask circuit of FIG. FIG. 4 is a waveform chart for explaining the operation of the forward / reverse circuit of FIG. In this embodiment, the motor driving device is an integrated circuit that drives a three-phase sensorless motor (for example, a spindle motor, a thread motor, or the like). Here, the sensorless motor is a motor having no element (for example, a Hall element) for detecting a relative position between the rotor and the stator.
[0015]
In FIG. 1, the U-phase drive coil 2, the V-phase drive coil 4, and the W-phase drive coil 6 are star-connected and have an electrical angle of 120 degrees, and are fixed to the stator of the sensorless motor.
[0016]
The N-channel MOSFET 8 is a source-side drive transistor for energizing the U-phase drive coil 2, and the N-channel MOSFET 10 is a sink-side drive transistor for energizing the U-phase drive coil 2. The drain sources of the N-channel MOSFETs 8 and 10 are connected in series between the power supply Vp and the ground, and the drain-source connection of the N-channel MOSFETs 8 and 10 is connected to one end of the U-phase drive coil 2. Similarly, the N-channel MOSFET 12 is a source-side drive transistor for energizing the V-phase drive coil 4, and the N-channel MOSFET 14 is a sink-side drive transistor for energizing the V-phase drive coil 4. The drain sources of the N-channel MOSFETs 12 and 14 are connected in series between the power supply Vp and the ground, and the drain-source connection portions of the N-channel MOSFETs 12 and 14 are connected to one end of the V-phase drive coil 4. Similarly, the N-channel MOSFET 16 is a source-side drive transistor for energizing the W-phase drive coil 6, and the N-channel MOSFET 18 is a sink-side drive transistor for energizing the W-phase drive coil 6. The drain sources of the N-channel MOSFETs 16 and 18 are connected in series between the power supply Vp and the ground, and the drain-source connection portions of the N-channel MOSFETs 16 and 18 are connected to one end of the W-phase drive coil 6. By turning on and off the N-channel MOSFETs 8, 10, 12, 14, 16, and 18 at appropriate timings described later, a drive current flows through the U-phase drive coil 2, the V-phase drive coil 4, and the W-phase drive coil 6. Thus, the sensorless motor rotates (for example, forward rotation). As a result, at one end of the U-phase drive coil 2, V-phase drive coil 4, and W-phase drive coil 6, drive voltages Vu, Vv, Vw having a phase difference of 120 electrical degrees appear, and the U-phase drive coil 2 , V-phase driving coil 4 and W-phase driving coil 6, a neutral point voltage Vcom appears in a dashed line. The upward and downward superimposed pulses KB on the drive voltages Vu, Vv, and Vw are generated by turning on and off the N-channel MOSFETs 8, 10, 12, 14, 16, and 18 so that the U-phase drive coil 2 and the V-phase This is a kickback pulse generated when the direction of the drive current flowing through the drive coil 4 and the W-phase drive coil 6 changes. Note that a bipolar transistor can be used as the driving transistor instead of the MOSFET.
[0017]
The switching circuit 20 has a U terminal, a V terminal, and a W terminal, and drive voltages Vu, Vv, and Vw are supplied to the U terminal, the V terminal, and the W terminal. The switching circuit 20 switches one of the U terminal, the V terminal, and the W terminal at a timing of 60 electrical degrees and outputs one of the driving voltages Vu, Vv, and Vw. The switching circuit 20 repeatedly switches in the order of the U terminal, the W terminal, and the V terminal when the sensorless motor rotates in the forward direction, and repeatedly switches in the order of the U terminal, the V terminal, and the W terminal when the sensorless motor rotates in the reverse direction. It will be.
[0018]
The comparator 22 compares any one of the drive voltages Vu, Vv, and Vw (+ terminal) obtained from the switching circuit 20 with the neutral point voltage Vcom (− terminal). As a result, the comparator 22 outputs a rectangular comparison signal CP that changes at a timing of 60 electrical degrees. The upward and downward superimposed pulses on the comparison signal CP are based on the kickback pulse KB. In the present embodiment, by providing the switching circuit 20, only one comparator need be provided, so that the number of elements can be reduced.
[0019]
The distribution circuit 32 has a U terminal, a V terminal, and a W terminal, and switches the U terminal, the V terminal, and the W terminal at the same timing as the switching circuit 20 to distribute and output the comparison signal CP. Note that the distribution circuit 32 repeatedly switches in the order of the U terminal, the W terminal, and the V terminal when the sensorless motor rotates in the forward direction, and in the order of the U terminal, the V terminal, and the W terminal when the sensorless motor rotates in the reverse direction. Switching will be repeated.
[0020]
From the U terminal of the distribution circuit 32, only a fragmentary signal with an electrical angle of 60 degrees is obtained, but a signal with an electrical angle of 120 degrees for energizing the U-phase drive coil 2 is missing. Similarly, only a fragmentary signal with an electrical angle of 60 degrees is obtained from the V terminal of the distribution circuit 32, and a signal with an electrical angle of 120 degrees for energizing the V-phase drive coil 4 is missing. Similarly, only a fragmentary signal having an electrical angle of 60 degrees is obtained from the W terminal of the distribution circuit 32, and a signal having an electrical angle of 120 degrees for energizing the W-phase drive coil 6 is missing. Note that noise corresponding to the kickback pulse KB is superimposed on signals obtained from the U terminal, the V terminal, and the W terminal of the distribution circuit 32.
[0021]
The mask circuit 34 removes noise corresponding to the kickback pulse KB from the signal having the electrical angle of 60 degrees obtained from the U terminal of the distribution circuit 32, and drives the U-phase drive coil 2 using the signal having the electrical angle of 60 degrees. And generates and outputs a continuous mask signal Umask for performing the operation. Similarly, the mask circuit 34 removes noise corresponding to the kickback pulse KB from the signal having the electrical angle of 60 degrees obtained from the V terminal of the distribution circuit 32, and uses the signal having the electrical angle of 60 degrees to generate the V-phase driving coil. 4 to generate and output a continuous mask signal Vmask. Similarly, the mask circuit 34 removes noise corresponding to the kickback pulse KB from the signal having the electrical angle of 60 degrees obtained from the W terminal of the distribution circuit 32, and uses the signal having the electrical angle of 60 degrees to generate the W-phase driving coil. 6 for generating a continuous mask signal Wmask for driving. The mask signals Umask, Vmask, and Wmask have a phase difference of 120 electrical degrees.
[0022]
The combining circuit 38 combines the mask signals Umask, Vmask, and Wmask obtained from the mask circuit 34, and outputs a rectangular combined signal FG that changes at a timing of 60 electrical degrees. That is, the composite signal FG is obtained by removing the superimposed pulse based on the kickback pulse KB from the comparison signal CP.
[0023]
The phase comparator 40, the filter 42, the buffer 44, the voltage controlled oscillator 46, and the 1 / N divider 48 constitute a PLL circuit. The phase comparator 40 outputs a voltage signal having a pulse width corresponding to the phase difference between the synthesized signal FG obtained from the synthesis circuit 38 and the frequency-divided signal DV obtained from the 1 / N frequency divider 48. . For example, the phase comparator 40 outputs a positive voltage signal when the phase of the composite signal FG is ahead of the phase of the frequency-divided signal DV, while the phase of the composite signal FG is higher than the phase of the frequency-divided signal DV. In a state of being late, a negative voltage signal is output. This voltage signal is integrated by the filter 42 and then supplied to the voltage controlled oscillator 46 via the buffer 44. The voltage controlled oscillator 46 outputs a frequency signal VCO corresponding to the voltage signal obtained from the buffer 44 and supplies the frequency signal VCO to the 1 / N frequency divider 48. By repeating this operation, the phase of the composite signal FG coincides with the phase of the frequency-divided signal DV. In the present embodiment, the frequency division number N of the 1 / N frequency divider 48 is set so that the half cycle (high level or low level) of the composite signal FG becomes eight cycles (not limited to this) of the frequency signal VCO. Shall be set.
[0024]
The shift register 50 delays the composite signal FG using the frequency signal VCO. In the present embodiment, it is assumed that the shift register 50 is composed of seven stages (not limited to this) of a D-type FF (not shown). Thus, in the D-type FF of the seventh stage (final stage) of the shift register 50, the composite signal FG is output as the delay signal SR with a delay corresponding to six periods of the frequency signal VCO. The mask circuit 34 creates an EXOR1 (exclusive OR) signal of the composite signal FG and the delay signal SR.
[0025]
The sensorless logic circuit 52 outputs a signal for energizing the U-phase drive coil 2, the V-phase drive coil 4, and the W-phase drive coil 6 at appropriate timing. In consideration of the fact that the sensorless motor itself cannot estimate the relative position between the rotor and the stator in the initial state, the sensorless logic circuit 52 operates from the predetermined initial levels of the mask signals Umask, Vmask, and Wmask. (For example, the initial levels of the mask signals Umask, Vmask, and Wmask are set to “L”, “L”, and “H”). The sensorless logic circuit 52 generates the energization signals Uiologic1 (= Umask-Vmask), Vlogic1 (= Vmask-Wmask), and Wlogic1 (= Wmask-Umask). Then, the sensorless logic circuit 52 outputs a signal for selecting the U terminal of the switching circuit 20 and the U terminal of the distribution circuit 32 while the energization signal Ulogic1 is at the “M” level. Similarly, the sensorless logic circuit 52 outputs a signal for selecting the V terminal of the switching circuit 20 and the V terminal of the distribution circuit 32 while the energization signal Vlogic1 is at the “M” level. Similarly, the sensorless logic circuit 52 outputs a signal for selecting the W terminal of the switching circuit 20 and the W terminal of the distribution circuit 32 while the energization signal Wlogic1 is at the “M” level. Then, the sensorless logic circuit 52 creates and outputs energization signals (drive signals) Ulogic2, Vlogic2, and Wlogic2 delayed from the energization signals Ulogic1, Vlogic1, and Wlogic1.
[0026]
The forward / reverse circuit 54 (braking means) performs braking of the sensorless motor and reverse rotation of the rotation direction of the sensorless motor. The forward / reverse circuit 54 executes reverse torque braking based on a normal brake instruction signal supplied from an external device or the like. As shown in FIG. 4, the reverse torque brake is energized in a direction to attenuate a back electromotive voltage of a sine wave generated in the U-phase drive coil 2, the V-phase drive coil 4, and the W-phase drive coil 6. As a result, the sensorless motor decelerates or stops. The forward / reverse circuit 54 first activates the reverse torque brake based on a change in the rotation instruction signal FR (for example, “H” during forward rotation and “L” during reverse rotation) supplied from an external device or the like. Then, the sensorless motor is stopped, and then the rotation direction is reversed. At this time, the mask signals Umask, Vmask, Wmask when the sensorless motor rotates in the forward direction and the mask signals Umask, Vmask, Wmask when the sensorless motor rotates in the reverse direction are V-phase and W-phase mask signals. Will be replaced. Thus, the sensorless motor accelerates with the rotation direction reversed. When the rotation instruction signal FR does not change because the brake instruction signal does not exist, the energization signals Ulogic2, Vlogic2, and Wlogic2 are output as they are via the forward / reverse circuit 54.
[0027]
The N-channel MOSFETs 8, 10, 12, 14, 16, 18 are turned on and off by the output signal of the forward / reverse circuit 54.
[0028]
The startup counter 58 (counter) counts the frequency signal VCO when the sensorless motor is stopped, based on the timing of the electrical angle 60 degrees of the composite signal FG when the sensorless motor is not started. When the activation counter 58 counts a predetermined value, the sensorless logic circuit 52 determines that the sensorless motor is stopped, and changes the level of the mask signals Umask, Vmask, and Wmask to the next level of 60 electrical degrees. . As a result, the sensorless motor is started again.
[0029]
The expected value circuit 60 is supplied with the comparison signal CP, the EXOR1 signal, and the energization signals Ulogic2, Vlogic2, and Wlogic2, so that each of the “H” periods of the EXOR1 signal has the same level as the comparison signal CP to be originally generated. It outputs an expected value signal EXP. The EXOR gate 62 calculates the exclusive OR of the comparison signal CP and the expected value signal EXP, and outputs an EXOR2 signal. The rising and falling points of the comparison signal CP are zero cross points of the back electromotive voltage and the neutral point voltage Vcom generated in the U-phase driving coil 2, the V-phase driving coil 4, and the W-phase driving coil 6. That is, when the comparison signal CP changes during the "L" period (range of the predetermined timing) of the EXOR1 signal, the EXOR gate 62 outputs the "L" EXOR2 signal assuming that the sensorless motor is rotating normally. On the other hand, when the comparison signal CP changes during the “H” period of the EXOR1 signal (the “H” or “L” period of the expected value signal EXP), the EXOR gate 62 determines that the sensorless motor is abnormally rotating. EXOR2 signal is output.
[0030]
In the D-type FF 64, the EXOR2 signal is supplied to a D (data) terminal, and the inverted signal of the EXOR1 signal is supplied to a C (clock) terminal. That is, the D-type FF 64 holds the EXOR2 signal at the falling edge of the EXOR1 signal, and then outputs the EXOR2 signal from the Q (output) terminal.
[0031]
The output from the Q terminal of the D-type FF 64 is supplied to the R (reset) terminal of the counter 66 (counting means), and the EXOR1 signal is supplied as a signal to be counted. That is, when the comparison signal CP changes during the “L” period of the EXOR1 signal, the counter 66 is kept reset by the output “L” of the Q terminal of the D-type FF 64 being supplied to the R terminal. . On the other hand, when the comparison signal CP changes in the “H” period of the EXOR1 signal, the counter 66 is reset and released immediately after the output “H” of the Q terminal of the D-type FF 64 is supplied to the R terminal. The rising edge of the EXOR1 signal (or the falling edge of the EXOR1 signal) is counted sequentially. When the count value of the counter 66 reaches N, the counter 66 outputs “H” as the sensorless motor is in the beat lock state. When the sensorless motor has a light load, the comparison signal CP immediately after startup may change in the “H” period of the EXOR1 signal. That is, N is an allowable number for determining that the sensorless motor has a light load and does not abnormally rotate.
[0032]
In the D-type FF 68, the output of the Q terminal of the D-type FF 64 is supplied to the D terminal, and the output of the counter 66 is supplied to the C terminal. That is, the D-type FF 68 holds the output “H” of the Q terminal of the D-type FF 64 at the output “H” (rising) of the counter 66, and thereafter, as a brake instruction signal for releasing the sensorless motor from the beat lock state. , The output “H” of the Q terminal of the D-type FF 64 is output from the Q terminal. The brake instruction signal at the time of beat lock is supplied to the forward / reverse circuit 54 via the OR gate 70 together with the normal brake instruction signal. When the brake command signal at the time of beat lock is supplied, the forward / reverse circuit 54 performs reverse torque braking to stop rotation of the sensorless motor. When the rotation of the sensorless motor is stopped, that is, when the mask signals Umask, Vmask, and Wmask are not supplied along with the disappearance of the zero cross, the sensorless logic circuit 52 forcibly discharges the charge of the capacitor 42 in the PLL circuit and outputs D. The type FFs 64 and 68 are reset. Thus, the D-type FF 64, the counter 66, and the D-type FF 68 are in a state where the beat lock of the sensorless motor can be detected.
[0033]
The entire block that performs signal processing until the output signal of the forward / reverse circuit 54 is obtained is a signal processing circuit. The start counter 58 and the PLL circuit are start instruction means.
[0034]
=== Beat lock detection operation of motor drive device ===
Next, a beat lock detection operation of the motor drive device will be described with reference to FIGS. FIG. 5 is a flowchart for explaining the beat lock detection operation of the motor drive device, and FIG. 6 is a waveform diagram for explaining the beat lock detection operation of the motor drive device. Note that, for convenience of explanation, noise based on the kickback pulse KB superimposed on the comparison signal CP is omitted.
[0035]
{Step S2}
The comparator 22 outputs a comparison signal CP as the sensorless motor rotates. The rising and falling points of the comparison signal CP are zero cross points between the back electromotive voltage generated in the U-phase driving coil 2, the V-phase driving coil 4, and the W-phase driving coil 6 and the neutral point voltage Vcom. That is, the comparison signal CP is a signal serving as a basis for detecting whether the zero cross exists in the “H” period or the “L” period of the EXOR1 signal.
[0036]
{Step S4}
It is determined whether the comparison signal CP is changing (rising or falling) during the “H” period or the “L” period of the EXOR1 signal. In other words, it is determined whether the zero cross is on the left side of the paper (the front side on the time axis) or the right side of the paper (the rear side on the time axis) with respect to the falling point of each period of the EXOR1 signal. When the zero cross is on the left side of the drawing with respect to the falling point of the EXOR1 signal, the zero cross is outside the allowable range. On the other hand, when the zero cross is on the right side of the drawing with respect to the falling point of the EXOR1 signal, the zero cross is within the allowable range. In the present embodiment, whether the comparison signal CP and the expected value signal EXP are at the same level at the falling point of the EXOR1 signal is determined using the EXOR2 signal obtained from the EXOR gate 62.
[0037]
{Step S6}
If the comparison signal CP changes during the "L" period of the EXOR1 signal, that is, if the above-described step S4 is denied, the D-type FF 64 assumes that the sensorless motor is rotating normally, and the D-type FF 64 changes to "L" at the falling edge of the EXOR1 signal. The EXOR2 signal is held and output. As a result, the counter 66 is reset and continues counting. Then, the above step S4 is executed again.
[0038]
{Step S8}
On the other hand, if the comparison signal CP changes during the "H" period of the EXOR1 signal, that is, if the above-described step S4 is affirmed, the D-type FF 64 determines that the sensorless motor is rotating abnormally or normally under light load, and the D-type FF 64 outputs the EXOR1 signal. The EXOR2 signal of "H" is held and output at the falling edge of the signal. As a result, the counter 66 is reset, and counts +1 increment at the rising edge of the EXOR1 signal.
[0039]
{Step S10}
It is determined whether the count value of the counter 66 is N or more. That is, it is determined whether the sensorless motor is rotating abnormally or rotating normally with a light load. If the count value of the counter 66 is smaller than N, that is, if the step S10 is denied, it is assumed that the sensorless motor is rotating normally with a light load, and the above steps S4 and thereafter are executed again.
[0040]
{Step S12}
On the other hand, if the count value of the counter 66 is N or more, that is, if the above step S10 is affirmed, the output of the counter 66 changes from "L" to "H". Then, assuming that the sensorless motor is beat-locked due to the abnormal rotation, the D-type FF 68 holds and outputs the output “H” of the D-type FF 64 at the rising edge of the output of the counter 66. The output “H” of the D-type FF 68 is supplied to the forward / reverse circuit 54 via the OR gate 70 as a brake instruction signal at the time of beat lock. As a result, the forward / reverse circuit 54 executes the reverse rotation torque brake.
[0041]
{Step S14}
The sensorless logic circuit 52 determines whether the rotation of the sensorless motor has stopped. In the present embodiment, the sensorless logic circuit 52 determines whether or not a zero cross exists according to whether or not the mask signals Umask, Vmask, and Wmask are supplied.
[0042]
{Step S16}
When the mask signals Umask, Vmask, and Wmask are supplied, the sensorless logic circuit 52 determines that the rotation of the sensorless motor has been decelerated by the reverse rotation torque brake, and resets the counting operation of the activation counter 58. As a result, the activation counter 58 continues to stop counting.
[0043]
{Step S18}
On the other hand, when the mask signals Umask, Vmask, and Wmask are not supplied, the sensorless logic circuit 52 determines that the rotation of the sensorless motor has stopped due to the reverse rotation torque brake. At this time, the sensorless logic circuit 52 cancels the reset of the counting operation of the activation counter 58. Thus, the start counter 58 starts counting the frequency signal VCO having the set frequency when the sensorless motor is stopped.
[0044]
{Step S20}
It is determined whether or not the count value of the activation counter 58 is X or more. That is, the sensorless logic circuit 52 determines whether or not a fixed time has elapsed after the stop of the sensorless motor. Then, if the count value of the activation counter 58 is less than X, that is, if the step S20 is denied, the above steps S14 and thereafter are executed again.
[0045]
{Step S22}
On the other hand, if the count value of the activation counter 58 is equal to or more than X, that is, if the above step S20 is affirmed, the sensorless logic circuit 52 forcibly discharges the charge of the capacitor 42 in the PLL circuit and causes the D-type FFs 64 and 68 to discharge. Reset and release the reverse torque brake. Thereby, the motor drive device is initialized and restarts the sensorless motor.
[0046]
As described above, the beat lock of the sensorless motor can be reliably detected, and the sensorless motor can be reliably started.
[0047]
=== Other Embodiments ===
As described above, the motor drive device according to the present invention has been described. However, the embodiments of the present invention described above are intended to facilitate understanding of the present invention, and do not limit the present invention. The present invention can be modified and improved without departing from the gist of the present invention, and the present invention naturally includes equivalents thereof.
[0048]
≪Brake means≫
In the present embodiment, the normal / reverse circuit 54 is described as executing reverse torque braking, but is not limited to this. For example, a short brake that short-circuits one ends of the U-phase drive coil 2, the V-phase drive coil 4, and the W-phase drive coil 6 may be used. As a result, the sensorless motor loses smooth deceleration but does not lose synchronism.
[0049]
≪Detection means≫
In the present embodiment, it is determined whether or not the zero-crossing of the back electromotive voltage and the neutral point voltage of the U-phase drive coil 2, the V-phase drive coil 4, and the W-phase drive coil 6 is at a predetermined timing by the rising and falling of the comparison signal CP. The detection is performed every time a down change occurs, but the present invention is not limited to this. For example, whether or not the zero crossing is at a predetermined timing may be detected based on one of a rising change and a falling change of the comparison signal CP, or both a rising change and a falling change of the comparison signal CP may be detected. It may be detected in parallel with the base.
[0050]
≪Predetermined timing≫
In the present embodiment, the 1 / N frequency divider 48 has a frequency division number N at which a half cycle (high level or low level) of the composite signal FG is equal to eight cycles of the frequency signal VCO. However, the present invention is not limited to this. For example, the dividing number N may be set small. As a result, the falling point of the EXOR1 signal can be finely adjusted, and the zero cross can be accurately and effectively detected.
[0051]
≪Drive transistor≫
In the present embodiment, an N-channel MOSFET is used, but the present invention is not limited to this. For example, any of a P-channel MOSFET, an NPN-type bipolar transistor, and a PNP-type bipolar transistor can be used.
[0052]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, starting of a sensorless motor can be reliably detected and a sensorless motor can be started reliably.
[Brief description of the drawings]
FIG. 1 is a configuration diagram for explaining a motor drive device of the present invention.
FIG. 2 is a waveform chart for explaining the operation of the motor drive device of the present invention.
FIG. 3 is a waveform chart for explaining the operation of the mask circuit of FIG. 1;
FIG. 4 is a waveform chart for explaining the operation of the forward / reverse circuit of FIG. 1;
FIG. 5 is a flowchart illustrating a beat lock detection operation of the motor drive device of the present invention.
FIG. 6 is a waveform chart for explaining a beat lock detection operation of the motor drive device of the present invention.
[Explanation of symbols]
2 U-phase drive coil 4 V-phase drive coil 6 W-phase drive coil 8, 10, 12, 14, 16, 18 N-channel MOSFET
46 Voltage-controlled oscillator 52 Sensorless logic circuit 54 Forward / reverse circuit 58 Start-up counter 60 Expected value circuit 62 EXOR gates 64, 68 D-type FF
66 counter

Claims (7)

In a motor driving device having a signal processing circuit for driving a sensorless motor,
Detecting means for detecting whether the zero crossing of the back electromotive voltage and the neutral point voltage generated in the drive coil of the sensorless motor is at a predetermined timing,
Counting means for resetting, based on an output of the detecting means when the zero cross is at a predetermined timing, and counting based on an output of the detecting means when the zero cross is not at a predetermined timing,
Braking means for performing braking until the sensorless motor stops, based on an output when the counting means has counted a predetermined value,
After the sensorless motor is stopped, the signal processing circuit issues an instruction for activating the sensorless motor, and a start instruction unit configured to start the sensorless motor.
A motor drive device comprising: 2. The motor drive device according to claim 1, wherein the braking unit turns on a drive transistor that energizes the drive coil at a timing at which the back electromotive voltage of the drive coil is attenuated. 3. The motor drive device according to claim 1, wherein the predetermined timing is in a range from a zero cross which should occur to a predetermined time before. The start instructing means has a counter for detecting the zero cross and starting counting, and when the counter has counted a predetermined value, the signal processing circuit issues an instruction to start the sensorless motor. The motor drive device according to claim 1, wherein: The motor drive device according to claim 1, wherein the sensorless motor has a drive coil having a plurality of phases. A method of driving a motor driving device having a signal processing circuit for driving a sensorless motor,
Detecting whether the zero-crossing of the back electromotive voltage and the neutral point voltage generated in the drive coil of the sensorless motor is at a predetermined timing,
Resetting when detecting that the zero cross is at a predetermined timing, performing counting when detecting that the zero cross is not at the predetermined timing,
When counting a predetermined value, performing braking until the sensorless motor stops,
After the sensorless motor is stopped, the signal processing circuit instructs to start the sensorless motor,
A motor driving method comprising: An integrated circuit, wherein the motor drive device according to claim 1 is integrated.

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