JP2004296975A - Semiconductor integrated circuit and its designing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit and its designing method by which electric potential of metal wiring in a circuit is easily observed in a failure analysis or the like. <P>SOLUTION: In designing a layout of the semiconductor integrated circuit of multi-layer wiring construction, each interlayer wiring is verified after automatic placement and routing, then an area where opening of an observation window reaching up to the metal wiring of a lower layer from a surface of a semiconductor chip after manufacture seems to be difficult is detected. For the metal wiring of the lower layer where opening of the observation window is determined to be difficult, an additional interconnection for observation extended from the metal wiring of the lower layer is provided at a region where the metal wiring is not provided on the upper layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit having a multilayer wiring structure and a method for designing the same.
[0002]
[Prior art]
In the layout design of a semiconductor integrated circuit having a multi-layer wiring structure, it is general that the metal wiring is wired mainly for the purpose of improving the performance of the entire circuit. No consideration is given to facilitating waveform measurement). For this reason, the lower metal wiring may be almost completely covered by the upper metal wiring, and it may be very difficult to observe the potential of the lower metal wiring.
[0003]
FIG. 3A is a layout plan view of an example of a conventional semiconductor integrated circuit having a multilayer wiring structure, and FIG. 3B is a layout cross-sectional view taken along the line BB ′. This figure shows a semiconductor integrated circuit 24 having a three-layer wiring structure as an example.
[0004]
In the semiconductor integrated circuit 24, the first-layer metal wiring 12 is wired in the horizontal direction in the figure. In the upper layer of the first-layer metal wiring 12, two second-layer metal wirings 14a and 14b are vertically arranged at predetermined intervals via an interlayer insulating film 20, and further in the upper layer, Two third-layer metal wirings 16a and 16b are wired in the left-right direction at a predetermined interval via the interlayer insulating film 20.
[0005]
The second-layer metal wirings 14a and 14b and the third-layer metal wiring 16b are connected to each other via vias 18a and 18b formed by opening the interlayer insulating film 20.
[0006]
When observing the potential of a metal wiring using an electron beam in a failure analysis or the like, generally, a metal wiring corresponding to an internal node to be observed from a surface of a manufactured semiconductor chip by a FIB (focused ion beam) device. A method of observing the potential of a metal wiring to be observed by opening a hole (observation window) that reaches the substrate and embedding a conductive substance in the observation window has been adopted.
[0007]
Since the first-layer metal wiring 12 of the semiconductor integrated circuit 24 is almost completely covered by the third-layer metal wiring 16b in the upper layer, when observing the potential of the first-layer metal wiring 12, the first-layer metal wiring 12 is used. It is very difficult to open the observation window reaching 12. As a result, when the observation window cannot be opened, it is impossible to observe the potential of the first layer metal wiring 12 or it is necessary to break the third layer metal wiring 16b and open the observation window. There was a problem.
[0008]
To cope with such a problem, for example, a semiconductor integrated circuit device of Patent Document 1 and a semiconductor device of Patent Document 2 have been proposed.
[0009]
The semiconductor integrated circuit device disclosed in Patent Document 1 is a semiconductor integrated circuit having a multi-layer wiring, in which a measurement terminal electrically connected to a lower wiring to be measured is provided in the uppermost layer.
[0010]
Further, in a semiconductor device disclosed in Patent Document 2, in a semiconductor device having a multi-layer wiring structure, after completion of automatic placement and routing, a wiring layer for which a signal is to be measured A contact hole which reaches is formed, and a signal measuring electrode is provided here.
[0011]
However, in the case of Patent Literature 1, the lower wiring to be measured is pulled up to the uppermost wiring in the functional block before the automatic placement and wiring. For this reason, the area must be designated as an automatic wiring prohibition area from the lowermost wiring to the uppermost wiring, and there is a problem that the execution of the automatic placement and routing is restricted.
[0012]
Further, when the lower wiring to be measured is pulled up to the uppermost wiring after the automatic placement and routing as in Patent Document 2, the lower wiring to be measured cannot be pulled to the uppermost wiring depending on the result of the automatic placement and routing. There was a problem that sometimes.
[0013]
Further, in either case of Patent Documents 1 and 2, it is necessary to correct the layout pattern by manual operation, which causes a problem that the number of steps increases and a correction error occurs.
[0014]
[Patent Document 1]
JP-A-5-335308 [Patent Document 2]
JP-A-9-232314
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit capable of solving the problems based on the conventional technique and facilitating observation of a potential of a metal wiring inside a circuit in a failure analysis or the like, and a design method thereof. .
[0016]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a method for designing a layout of a semiconductor integrated circuit having a multilayer wiring structure.
After the automatic placement and routing, the wiring between the layers is verified, and it is detected that it is difficult to open the observation window reaching from the surface of the manufactured semiconductor chip to the lower metal wiring, and the observation window is detected. An additional wiring for observation extending from the metal wiring of the lower layer is provided in a region where the metal wiring does not exist in the upper layer with respect to the metal wiring of the lower layer determined to be difficult to open. The present invention provides a method for designing a semiconductor integrated circuit.
[0017]
According to the present invention, an additional wiring for observation, which is manufactured by applying the method of designing a semiconductor integrated circuit described above and extends from the lower metal wiring in a region where no metal wiring exists in the upper layer, is provided. A semiconductor integrated circuit is provided.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a semiconductor integrated circuit and a design method thereof according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.
[0019]
FIG. 1 is a flowchart of one embodiment showing each step of the method for designing a semiconductor integrated circuit of the present invention. When designing the layout of a semiconductor integrated circuit according to the present invention, first, as shown in FIG. 1, automatic placement and routing is performed based on a netlist of the semiconductor integrated circuit (S1). That is, cells are automatically arranged based on the information of the netlist, and these cells are automatically wired. As the automatic placement and routing tool, any conventionally known tools can be used.
[0020]
After the automatic placement and routing is completed, the wiring between the layers is verified (S2). In the wiring verification, the lower metal wiring is almost completely covered by the upper metal wiring, and it is difficult to open an observation window from the surface of the manufactured semiconductor chip to the lower metal wiring by using an FIB device or the like. Is detected. For example, when the present invention is applied to the conventional semiconductor integrated circuit shown in FIG. 3, the first metal wiring 12 is detected by wiring verification.
[0021]
As a result, in the case of the lower metal wiring which is determined to be difficult to open the observation window (“Yes” in S3), a region where the upper metal wiring does not exist with respect to this lower metal wiring. Then, an additional wiring for observation extending from the metal wiring of the lower layer is provided (S4). On the other hand, as a result of the wiring verification, if it is determined that the observation window can be opened in all the lower metal wirings (“No” in S3), the automatic placement and wiring is completed (S5).
[0022]
In step S4, after the additional wiring for observation is provided in the lower metal wiring determined to be difficult to open the observation window, the process returns to step S1, and the automatic placement and wiring is performed again (S1). . In the second and subsequent automatic placement and routing, in the layout obtained by the first automatic placement and routing, a layout is obtained in which the additional wiring is extended with respect to the lower metal wiring in step S4. The subsequent operation is as described above.
[0023]
Since an additional wiring for observation is provided for all the lower metal wirings where it is difficult to open the observation window, the potential of the lower metal wiring is opened by opening the observation window to reach this additional wiring for observation. Observations can be made. When the additional wiring for observation is provided, there is no adverse effect on the automatic arrangement wiring, and when the observation window is opened, the upper metal wiring is not broken. Further, since an additional wiring for observation is automatically provided, there is an advantage that no human error occurs.
[0024]
FIG. 2A is a layout plan view of one embodiment of the semiconductor integrated circuit of the present invention, and FIG. 2B is a layout cross-sectional view taken along line AA ′. This figure shows a conventional semiconductor integrated circuit 24 by applying the semiconductor integrated circuit design method of the present invention so that it can be easily compared with the conventional semiconductor integrated circuit 24 shown in FIGS. 3 (a) and 3 (b). Has been redesigned. Therefore, the same components are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0025]
That is, the first-layer metal wiring 12 of the semiconductor integrated circuit 10 of the present embodiment is located in a region where the second-layer metal wirings 14a and 14b and the third-layer metal wirings 16a and 16b do not exist in the conventional semiconductor integrated circuit 24. And an additional wiring 22 for observation extending from the first-layer metal wiring 12.
[0026]
As described above, in the conventional semiconductor integrated circuit 24 shown in FIG. 3, the first-layer metal wiring 12 is almost completely covered by the third-layer metal wiring 16b. It is very difficult to open an observation window that reaches the single-layer metal wiring 12.
[0027]
On the other hand, in the semiconductor integrated circuit 10 of the present embodiment shown in FIG. 2, the first metal wiring 12 is observed in a region where the second-layer metal wirings 14a and 14b and the third metal wirings 16a and 16b do not exist. Additional wiring 22 is extended. Therefore, by opening the observation window reaching the additional wiring 22 for observation, the first-layer metal wiring 12a is not affected at all without affecting the second-layer metal wirings 14a and 14b and the third-layer metal wirings 16a and 16b. Can be easily observed.
[0028]
Although a semiconductor integrated circuit having a three-layer wiring structure has been described as an example, the present invention is applicable to a semiconductor integrated circuit having a multilayer wiring structure having two or more layers. Further, it is sufficient that one additional wiring for observation is provided. The provision of the additional wiring for observation slightly increases the capacity of the metal wiring. However, timing verification is performed, and if necessary, two or more wirings may be provided if necessary. Further, the criteria for providing the additional wiring for observation in the lower metal wiring may be appropriately determined as needed.
[0029]
The present invention is basically as described above.
As described above, the semiconductor integrated circuit and the design method thereof according to the present invention have been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. Of course.
[0030]
【The invention's effect】
As described above in detail, according to the present invention, it is difficult to verify the wiring between the layers after the automatic placement and routing, and to open the observation window from the surface of the manufactured semiconductor chip to the lower metal wiring. This is to detect a portion considered to be, and to provide an additional wiring for observation extending from the metal wiring in the lower layer in a region where the metal wiring does not exist in the layer above the metal wiring in the lower layer.
According to the present invention, by opening the observation window reaching the additional wiring for observation, it is possible to easily observe the potential of the lower metal wiring without affecting the upper metal wiring at all. In addition, when the additional wiring for observation is provided, there is no adverse effect on the automatic placement and wiring, and when the observation window is opened, the upper metal wiring is not destroyed. Further, since an additional wiring for observation is automatically provided, there is an advantage that no human error occurs.
[Brief description of the drawings]
FIG. 1 is a flowchart of one embodiment showing each step of a method for designing a semiconductor integrated circuit of the present invention.
FIG. 2A is a layout plan view of one embodiment of a semiconductor integrated circuit of the present invention, and FIG. 2B is a layout cross-sectional view taken along line AA ′.
3A is a layout plan view of an example of a conventional semiconductor integrated circuit, and FIG. 3B is a layout cross-sectional view taken along line BB ′.
[Explanation of symbols]
10, 24 Semiconductor integrated circuit 12 First layer metal wiring 14a, 14b Second layer metal wiring 16a, 16b Third layer metal wiring 18a, 18b Via 20 Interlayer insulating film 22 Additional wiring for observation

Claims (2)

When designing the layout of a semiconductor integrated circuit with a multilayer wiring structure,
After the automatic placement and routing, the wiring between the layers is verified, and it is detected that it is difficult to open the observation window reaching from the surface of the manufactured semiconductor chip to the lower metal wiring, and the observation window is detected. An additional wiring for observation extending from the metal wiring of the lower layer is provided in a region where the metal wiring does not exist in the upper layer with respect to the metal wiring of the lower layer determined to be difficult to open. Semiconductor integrated circuit design method. 2. An additional wiring for observation, which is manufactured by applying the method of designing a semiconductor integrated circuit according to claim 1 and has no metal wiring in the upper layer, extends from the lower metal wiring in a region where the metal wiring does not exist in the upper layer. A semiconductor integrated circuit characterized by the above-mentioned.

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