JP2004287451A - Drive technology for starting up liquid crystal devices - Google Patents

Abstract

An object of the present invention is to provide a liquid crystal panel having a high response speed and a wide viewing angle by transferring an OCB type liquid crystal having a bend alignment in a short time.
A liquid crystal transitions to a bend alignment in a short time by providing a period between a pixel electrode and a counter electrode of a liquid crystal panel for continuously applying a higher potential difference than that during normal image display. In addition, elaborate in order to obtain the contents of the period and a high potential difference. Also, the structure of the pixel is devised.
[Selection] Fig. 28

Description

  The present invention relates to a liquid crystal device, and more particularly to a startup technique for driving a liquid crystal device in which a liquid crystal layer is in a splay alignment when no voltage is applied but is in a bend alignment when a function such as display is performed.

  In a liquid crystal device, the electrical operation of a liquid crystal element is such that each pixel is a holding type that maintains light if bright and dark if dark during one display cycle. One of the features was that it became a still image with little flicker.

  However, in recent years, moving images can be easily processed in personal computers by increasing the speed and capacity of CPUs and memories. For this reason, it is desired to improve the image quality when displaying a moving image on a liquid crystal display device.

  Also, televisions as broadcast receivers have been increasing in screen size, but cathode-ray tubes have a larger screen and inevitably have a greater depth to some extent, which is not desirable for the demand for thin-screen televisions. It is considered that a liquid crystal display device is adopted as one means for that.

  Currently, the TN alignment liquid crystal device, which is the mainstream of the liquid crystal device, has a slow response speed, and in a cathode ray tube, each pixel emits light for a short period of time within each display period, whereas the liquid crystal element is If it is ON (open, light emission), the image is inferior to that of a cathode ray tube, for example, it is a holding type that keeps emitting light during the display period within one display cycle, and looks like a trail when displaying a moving image.

  As a countermeasure, for example, if a liquid crystal having a bend orientation called OCB type (type) disclosed in Japanese Patent Application Laid-Open No. 61-116329 or Japanese Patent Application Laid-Open No. It is possible to provide a large-screen display that can sufficiently cope with a screen and is thinner and consumes less power than a CRT.

  In addition, devices using liquid crystals are being used not only for display units such as word processors, personal computers, and television receivers, but also for display units of liquid crystal plasma displays, circuits and devices using optical logic elements, and the like. However, even in such applications, OCB type liquid crystals have been receiving attention from the viewpoints of good display performance, high-speed operation, and the like.

  However, in such a liquid crystal, a high potential difference needs to be continuously applied to the liquid crystal layer for a certain period of time or more in order to make a transition from the splay alignment 51 shown in (1) or (2) of FIG. 1 to the bend alignment shown in (3). However, applying such a voltage imposes a burden on the transistor element and the wiring, resulting in high cost. That is, a technique for easily and surely performing such transition by using a voltage, a current, or the like that can be used in an element, a wiring, or the like that is widely used at present has not yet been realized. As a result, this type of liquid crystal has not been used for general purposes at present.

  Therefore, in such an OCB type liquid crystal device or its driving circuit, the liquid crystal layer can be surely transferred to the bend alignment in a short time without burdening the current hardware such as transistor elements and wirings, and at a low cost. Technology development was desired.

  Similarly, development of a reliable and easy start-up technique has been desired for use in other applications described above.

  The present invention has been made for the purpose of solving the above problems, and has devised the structure of each element of a device using a liquid crystal. Similarly, a voltage as high as possible for the start-up is applied, and timing and the like when applying the voltage are devised. Specifically, the following is performed.

  In the inventions of the first invention group, the structure of the OCB type liquid crystal display device and the like is devised, and as a result, the gate line between the first substrate and the counter electrode of the second substrate are used for startup. When a higher electric field strength is applied to the liquid crystal layer at the time of display of a normal image, the bend alignment occurs in that portion, and this becomes a nucleus, which grows, and the bend alignment of the entire liquid crystal layer It is intended to shift to. At this time, since a gate line which is driven at a higher voltage than other parts in the liquid crystal panel is used, it is possible to apply a high electric field strength to the liquid crystal layer without burdening the source line driving IC and the pixel transistor. it can.

  In order to give a higher electric field strength to the liquid crystal layer, the thickness of the insulating film on the gate line is reduced to increase the capacitance of the insulating film, and the voltage division ratio between the gate line and the counter electrode is changed.

  Similarly, the insulating film capacity is increased by using a material having a high relative dielectric constant for the insulating film on the gate line, and the voltage division ratio of the voltage between the liquid crystal layer and the insulating film between the gate line and the counter electrode is changed.

  Similarly, the thickness of the liquid crystal layer on the gate line is reduced by about 0.5 to 1.5 μm by increasing the thickness of the metal forming the gate line in a portion where there is no other metal film or semiconductor layer between the liquid crystal layer and the liquid crystal layer. are doing.

  Similarly, the source line forming metal is electrically contacted and laminated on the gate line where there is no other metal film or semiconductor layer between the liquid crystal layer and the thickness of the gate line is increased, and the liquid crystal layer on the gate line is increased. Has been reduced in thickness.

  Similarly, a source line forming metal is laminated on a portion of the gate line where there is no other metal film or semiconductor layer between the liquid crystal layer and the metal line or the semiconductor layer without electrically contacting the portion to reduce the thickness of the liquid crystal layer on the gate line. .

  Similarly, the opposing electrode on the second substrate is divided into a portion facing the gate line of the first substrate and the other portion, and a higher voltage is applied to the opposing electrode facing the gate line than the other portion. Multiply.

  Similarly, the thickness of the liquid crystal layer over the gate line is reduced by making the thickness of the counter electrode at the portion facing the gate line on the second substrate thicker than at other portions.

  Similarly, the color filter forming resin on the second substrate is laminated on the portion of the first substrate facing the gate line to reduce the thickness of the liquid crystal layer on the gate line.

  Similarly, a columnar spacer is provided on a portion of the second substrate facing the gate line of the first substrate, and an opposing substrate electrode is formed between the columnar spacer and the liquid crystal layer to form a liquid crystal layer on the gate line. Is thinner.

  In the second invention group, the circuit for starting up the liquid crystal device and the like are devised so that the potential difference between the pixel electrode on the first substrate and the counter electrode on the second substrate is higher than that during normal image display. Is given continuously according to a predetermined procedure and rules.

  Thereby, the variation of the counter electrode can be used. The change to the bend alignment is promoted by changing the scan timing and the applied potential difference and controlling the change.

  Similarly, a period is provided between the pixel electrode of the first substrate and the counter electrode of the second substrate to continuously apply a first type of potential difference different from the normal image display period, and the liquid crystal is made as large as possible in area. By increasing the potential difference applied to the layer, the generation of transition nuclei to bend alignment is increased, the speed of bend region expansion is increased, and the transition to bend alignment is performed in a short time.

  Similarly, a first type potential difference applying step of applying a first type potential difference different from the normal video display period between the pixel electrode of the first substrate and the counter electrode of the second substrate; Is a driving method in which a second type of potential difference applying step of applying a second type of potential difference smaller than the potential difference is repeatedly and alternately performed at least once by a control step, and 50% to 95% of these periods A first type of potential difference applying step is performed in which the time is a first type of potential difference applying step and a bend alignment nucleus is generated and a bend region is expanded, and a bend alignment nucleus cannot be generated or the bend region is not expanded. By alternately applying the second type of potential difference applying step for rearranging the liquid crystal layer in the bent portion, the entire surface of the panel can be transferred to the bend alignment at high speed.

  Similarly, when the pixel transistor is turned on from off in the second type of potential difference applying step, a potential reflecting on the potential of the pixel electrode caused by the potential fluctuation of the gate line and reflected on the counter electrode potential is applied to the source line. It has a small charging step to charge the pixel electrode by changing the on / off timing of the gate line from the normal video display period, and fixes the potential of the pixel electrode to a desired potential to bend the entire panel. Transfer to the site can be accelerated.

  Similarly, when the pixel transistor is turned on from off in the second type of potential difference applying step, a potential reflecting on the potential of the pixel electrode caused by the potential fluctuation of the gate line and reflected on the counter electrode potential is applied to the source line. A first type of potential difference applying step, the source line potential is set to a different potential from the second type potential difference applying step so that the first type potential difference becomes larger. Thus, the generation of the bend alignment nucleus and the expansion of the bend region are accelerated, and the transition to the bend alignment over the entire panel is accelerated.

  Similarly, the driving period for bend alignment of the liquid crystal layer is started from the second type of potential difference applying step, and the first type of potential difference between the pixel electrode and the counter electrode is performed by aligning the liquid crystal layer first. In the first type of potential difference applying step, the generation of bend nuclei and the expansion of the bend region are accelerated, and the transition to the bend orientation over the entire panel is accelerated.

  Similarly, a first type of potential difference applying step of providing a first type of potential difference between the pixel electrode and the counter electrode in order to bend the liquid crystal layer, and the potential difference between the pixel electrode and the counter electrode is smaller than the first type potential difference. A driving method in which a second type of potential difference applying step for making a second type of potential difference is alternately performed at least once, and the first type of potential difference applying step or the second type of potential difference applying step is completed to perform a normal input video information display period. Before the transition to, the image information having a large potential difference applied to the liquid crystal layer is displayed in one or more fields, and the transition to the bend alignment of the liquid crystal layer is completed by enlarging the bend area, thereby changing the bend alignment over the entire panel. Speeds up the transition.

    The third invention group aims to stabilize the liquid crystal layer at the time of startup. For this reason, efforts have been made to turn on the power.

As can be seen from the above description, according to the present invention,
By applying a first type of potential difference between the pixel electrode and the counter electrode, which occupy a large area in the liquid crystal panel, as compared with that during normal image display, it is possible to generate nuclei in the bend alignment of the liquid crystal layer and expand the bend region. As a result, the liquid crystal layer can be transferred to the bend alignment in a short time on the entire surface of the panel, and a liquid crystal panel with high response speed and a wide viewing angle can be provided.

A first type of potential difference applying step for applying a first type of potential difference between the pixel electrode and the counter electrode of the liquid crystal panel which is higher than during normal image display; and a second type of potential difference smaller than the first type of potential difference. Are alternately provided to generate nuclei for the bend alignment of the liquid crystal layer, expand the bend region, and alternately rearrange the liquid crystal layer, and consequently over the entire panel. The liquid crystal layer can be transferred to the bend alignment in a short time, and a liquid crystal panel with a high response speed and a wide viewing angle can be provided.

  Further, by changing the potential of the common electrode forming a storage capacitor between the pixel electrode and the pixel electrode, the potential of the pixel electrode is changed so that the potential difference between the pixel electrode and the counter electrode becomes larger than the potential given from the source line. By applying a high potential difference to the liquid crystal layer, the liquid crystal layer can be transferred to the bend alignment in a shorter time over the entire surface of the panel, and a liquid crystal panel with high speed response and a wide viewing angle can be provided.

  In addition, by changing the potential of the gate line in the previous stage where a storage capacitor is formed between the pixel electrode and the pixel electrode, the potential difference between the pixel electrode and the counter electrode is made larger than the potential given from the source line. By causing the liquid crystal layer to fluctuate and apply a high potential difference to the liquid crystal layer, the liquid crystal layer can be transferred to the bend alignment in a shorter time over the entire surface of the panel, and a liquid crystal panel with high speed response and a wide viewing angle can be provided.

  Also, by taking into account the potential fluctuation generated in the pixel electrode when the pixel transistor is turned off, the on / off timing of the gate line is not changed from that during normal image display, so that the pixel electrode and the counter electrode can be used. A first type of potential difference and a second type of potential difference effective for the transition of the liquid crystal layer to the bend alignment can be provided therebetween, and the transition to the bend alignment over the entire panel can be performed at high speed.

  Similarly, while the on / off timing of the gate line is the same as during normal image display, when the pixel transistor is off, the potential of the source line is further changed so that the liquid crystal layer is also provided between the source line and the counter electrode. By providing a second type of potential difference effective for the transition to the bend orientation, the transition to the bend orientation over the entire panel can be accelerated.

  In addition, by performing at least one charge of the pixel electrode by turning on the pixel transistor at the beginning of the driving period for shifting the liquid crystal layer to the bend alignment, the complexity of changing the on / off timing of the pixel transistor from the normal video display period is eliminated. However, since the number of times of charging the pixel electrode during the second type of potential difference applying step is smaller than the normal timing, the time during which the potential difference between the pixel electrode and the counter electrode is zero increases during the second type of potential difference applying step. The transition to bend alignment over the entire surface can be made faster.

  In addition, the pixel transistor is charged by turning on the pixel transistor at least once at the beginning of each of the first type potential difference applying step and the second type potential difference applying step for bend alignment of the liquid crystal layer. The control of the OFF timing becomes more complicated, but by determining the pixel electrode potential at the beginning of each period, the influence of the fluctuation of the counter electrode potential is completely eliminated, and the first type potential difference and the second type potential difference are provided. Therefore, the transition to the bend alignment over the entire surface of the panel can be further accelerated.

  In addition, during the driving period of the transition of the liquid crystal layer to the bend alignment, the off-voltage of the gate line is set to DC, thereby eliminating the influence of the pixel line from the gate line potential fluctuation, particularly in the second type potential difference applying step. Thus, the transition to the bend alignment over the entire panel can be performed at high speed.

  Further, the potential of the source line is varied between the first type potential difference applying step and the second type potential difference applying step, and the potential difference between the pixel electrode and the counter electrode in the first type potential difference applying step is increased. In addition, the transition to the bend alignment over the entire panel can be performed at high speed.

  In addition, before the drive period for bend alignment of the liquid crystal layer is completed and before the transition to the normal image display period, video information having a large potential difference between the pixel electrode and the counter electrode is displayed in one field, so that the bend alignment is performed. Bend alignment by adding one field, that is, tens of milliseconds, without adding a first type of potential difference applying step or a second type of potential difference applying step to increase the time for completion of transition by several hundred milliseconds. Can be completed, and the time required for completing the transfer on the entire panel can be reduced.

  In addition, by starting the second type of potential difference applying step without excessively disturbing the state of the liquid crystal layer when the power is turned on from the state when the power is not turned on, the liquid crystal layer can be aligned in a shorter time, and the entire panel can be aligned. Of the liquid crystal layer to the bend alignment can be accelerated.

  In addition, by reducing the thickness of the insulating film between the gate line electrode and the counter electrode, the electric field strength between the gate line electrode and the counter electrode is increased, and the amount and speed of generation of bend alignment nuclei in the liquid crystal layer are increased. The transition to the bend alignment over the entire panel can be performed at high speed.

  Also, by thinning the insulating film between the gate line electrode and the counter electrode by patterning, the amount of nuclei for bend alignment in the liquid crystal layer can be increased and speeded up, and the transition to bend alignment over the entire panel can be performed at high speed. Can be

  In addition, by increasing the thickness of the gate line electrode, the thickness of the liquid crystal layer on the gate line is reduced, the electric field intensity applied to the liquid crystal layer is increased, and the generation of nuclei of bend alignment of the liquid crystal layer can be increased at a high speed. Thus, the transition to the bend alignment over the entire panel can be performed at a high speed.

  In addition, the source line forming metal is electrically contacted and laminated on the gate line forming metal to substantially increase the thickness of the gate line electrode and the thickness of the liquid crystal layer on the gate line, thereby forming a liquid crystal layer. By increasing the electric field strength, the transition to the bend alignment can be performed at high speed.

  The thickness of the liquid crystal layer on the gate line is reduced by electrically insulating the metal forming the source line between the gate line electrode and the counter electrode, and the electric field strength applied to the liquid crystal layer is increased to bend alignment. The transition to is faster.

  In addition, since the counter electrode is patterned into a first counter electrode and a second counter electrode, and the first counter electrode and the second counter electrode are electrically insulated, voltage fluctuation is caused by the liquid crystal layer and the insulating film. An arbitrary electric field intensity can be given to the liquid crystal layer on the gate line electrode while preventing the pixel electrode and the pixel transistor from being affected via the capacitive load, and the transition to the bend alignment can be performed at high speed. During normal image display, by setting the first and second counter electrodes to the same potential, it is possible to obtain the same image quality as that of a conventional liquid crystal display device in which the counter electrodes are not patterned.

  Further, by forming the counter electrode facing the gate line into two layers, the thickness of the liquid crystal layer on the gate line is reduced, the electric field strength can be increased, and the transition to the bend alignment can be performed at high speed.

  Further, by laminating a color filter forming resin on a portion of the second substrate facing the gate line electrode of the first substrate, the counter electrode in this portion is raised, and the thickness of the liquid crystal layer on the gate line is reduced. The electric field strength of the liquid crystal layer can be increased, and the transition to bend alignment can be performed at a high speed.

  Further, on the second substrate, a columnar spacer is formed at a portion of the first substrate facing the gate line electrode, and an opposing electrode is formed between the columnar spacer and the liquid crystal layer, whereby the thickness of the liquid crystal layer on the gate line is increased. , The electric field strength of the liquid crystal layer can be increased, and the transition to bend alignment can be accelerated.

  Hereinafter, the present invention will be described based on the embodiments.

<< First invention group >>
In the present invention, a high voltage is applied to transfer the liquid crystal layer by mainly devising the structure of the insulating film of the pixel.

  Hereinafter, the present invention will be described based on its embodiments.

(Embodiment 1-1)
Here, “(1-1 embodiment)” means “first embodiment of the first invention group”. For this reason, if it is "the second embodiment of the present invention group", it is described as "(1-2nd embodiment)". The same applies to other invention groups.

  In practice, pixels having such a circuit configuration are formed on the substrate in vertical, horizontal, multiple rows, multiple rows, and even in multiple cases depending on the case, but this is obvious and complicated. , Illustration is omitted. This is the same in other invention groups and embodiments.

  FIG. 2 shows a plane (1) of a structure of one pixel of a conventional liquid crystal panel and a cross section (2) taken along the line AA of the transistor element portion. In the figure, reference numeral 21 denotes a transparent pixel electrode. 3 is a pixel electrode. 5 is a liquid crystal layer. 64 is a channel protective film. 65 is an a-Si (amorphous silicon) layer. 66 is an n + a-Si layer. 7 is a source line electrode. Reference numeral 76 denotes an insulating film between the source line electrode and the liquid crystal layer. 8 is a gate line electrode. Reference numeral 86 denotes an insulating film between the gate line electrode and the a-Si layer. 9 is a counter electrode.

  FIG. 2 schematically shows a capacitive load between the gate line electrode and the counter electrode of the liquid crystal panel shown in FIG.

  In the figure, reference numeral 8 denotes a gate line electrode. 9 is a counter electrode. C1 is a capacitive load of the liquid crystal layer. C2 is a capacitive load of the insulating film between the source line electrode and the liquid crystal layer. C3 is a capacitive load of the insulating film between the gate line electrode and the a-Si layer.

  FIG. 4 shows a plane (1) of a structure for one pixel of the liquid crystal panel of the present embodiment and a cross section (2) taken along line AA of FIG.

  In this figure, 8 is a gate line electrode, 7 is a source line electrode, 3 is a pixel electrode, 64 is a channel protective film, 65 is an a-Si layer, 66 is an n + a-Si layer, 86 is a gate line electrode and a-Si A first insulating film between the layers, 762 a second insulating film between the source line electrode and the liquid crystal layer, 5 a liquid crystal layer, 9 a counter electrode, 21 a transparent pixel electrode, 862 a gate line electrode and a-Si interlayer A second insulating film 761 is a first insulating film between the source line electrode and the a-Si layer.

  Hereinafter, the operation in the present embodiment will be described with reference to these three figures.

  In FIG. 2, when a voltage V is applied to the gate line electrode 8 and the counter electrode 9, the capacitances of the liquid crystal layer 5, the source line electrode 7, the insulating film 762 between the liquid crystal layers, and the gate line electrode and the insulating film 86 between the a-Si layers are respectively increased. The voltage determined by the ratio of the active load values is applied to each layer. The partial pressures are defined as V1, V2, and V3. These relationships will be described with reference to FIG.

The capacitive load value C per unit area S is represented by the following (Equation 1-1), where ε is the relative dielectric constant of the layer, 1 is the thickness of the layer, and ε0 is the dielectric constant of vacuum.

C = ε0 × ε × S / 1 (Equation 1-1)

On the other hand, the divided voltage V1 of the capacitive loads C1, C2, and C3 connected in series is expressed by the following equation (1-2).
V1 = V * C2 * C3 / (C1 * C2 + C2 * C3 + C3 * C1) (Equation 1-2).

Assuming that the relative permittivity and the thickness of the liquid crystal layer 5 and the insulating films 762 and 86 are ε1, ε2, ε311, l2, and l3, respectively, the partial pressure V1 of Equation (1-2) is V1 = V * ε2 * ε3 * 11 / (Ε1 * ε2 * 13 + ε2 * ε3 * 11 + ε3 * ε1 * 12) (Equation 1-3)
And the electric field intensity E1 is E1 = V1 / 11
= V * ε2 * ε3 / (ε1 * ε2 * 13 + ε2 * ε3 * 11 + ε3 * ε1 * 12)
= V / (11 + 12 * ε1 / ε2 + 13 * ε1 / ε3) (Equation 1-4)
It becomes.

  In the structure of FIG. 4, the gate line electrode and the a-Si interlayer, the source line electrode and the source line electrode are patterned by making the insulating film between the gate line electrode and the a-Si layer, the source line electrode, and the liquid crystal layer into two layers. The insulating film between the gate line electrode and the liquid crystal layer is made thinner while the insulation between the liquid crystal layers remains the same as before. With such a structure, the denominator of the electric field intensity E1 represented by the expression (1-4) is reduced, and as a result, the electric field intensity applied to the liquid crystal layer can be increased, and a high-speed transition to bend alignment can be achieved. Will be possible.

  The relative dielectric constant of the liquid crystal layer changes from about 3 to about 8 depending on the transmittance of the liquid crystal. The relative dielectric constants of SiOx, SiNx, and TaOx used as the insulating film are about 3.9, about 6.4, and about 23, respectively. When the relative permittivity of the liquid crystal varies uniformly, the electric field intensity applied to the liquid crystal layer in FIG. 13 is often higher than the electric field intensity (formula 1-4) of the conventional structure. In order to rapidly transfer a liquid crystal layer having a bend alignment from an initial homogeneous state to a bend alignment, it is very effective to apply an electric field strength as high as possible to the liquid crystal layer. Is a very effective means.

(Embodiment 1-2)
FIG. 5 shows a structural diagram of the first to second embodiments of the present invention.

  In the figure, 8 is a gate line electrode, 7 is a source line electrode, 3 is a pixel electrode, 64 is a channel protective film, 65 is an a-Si layer, 66 is an n + a-Si layer, 86 is a gate line electrode and a-Si An interlayer insulating film, 76 is an insulating film between the source line electrode and the liquid crystal layer, 5 is a liquid crystal layer, 9 is a counter electrode, 21 is a transparent pixel electrode, and A is a line showing a cross section.

  In the first embodiment (the first to eleventh embodiments are abbreviated as described above because no misunderstanding occurs. The same applies to the following description), the insulating films are each composed of two layers. As shown, the same effect can be obtained even if the thickness of the insulating film between the gate line electrode and the liquid crystal layer is reduced by patterning.

(First to Third Embodiments)
FIG. 6 shows a configuration diagram of the first to third embodiments.

  Also in this figure, 8 is a gate line electrode, 7 is a source line electrode, 3 is a pixel electrode, 64 is a channel protective film, 65 is an a-Si layer, 66 is an n + a-Si layer, 86 is a gate line electrode and a- Reference numeral 76 denotes an insulating film between the Si layers, reference numeral 76 denotes an insulating film between the source line electrode and the liquid crystal layer, reference numeral 5 denotes a liquid crystal layer, reference numeral 9 denotes a counter electrode, reference numeral 21 denotes a transparent pixel electrode, and reference numeral A denotes a line showing a cross section.

  In this structure, the thickness of the gate line electrode is increased and the thickness of the liquid crystal layer on the gate line is reduced by increasing the thickness of the gate line electrode, thereby increasing the electric field strength applied to the liquid crystal layer and causing transition to bend alignment. Can be faster.

  The thickness of the gate line electrode is usually about 0.2 μm to 0.6 μm, but by doubling the thickness, the thickness of the liquid crystal layer can be reduced by about 0.5 μm.

(Embodiment 1-4)
FIG. 7 shows a configuration diagram of the first to fourth embodiments.

  Also in this figure, 8 is a gate line electrode, 7 is a source line electrode, 3 is a pixel electrode, 64 is a channel protective film, 65 is an a-Si layer, 66 is an n + a-Si layer, 86 is a gate line electrode and a- An insulating film between the Si layers, 76 is an insulating film between the source line electrode and the liquid crystal layer, 5 is a liquid crystal layer, 9 is a counter electrode, 21 is a transparent pixel electrode, A is a line showing a cross section, and 70 is a gate line. It is a source line forming metal that is electrically contacted and laminated on the electrode.

  In this structure, a partially contacting gate line is formed by electrically contacting and laminating a source line forming metal on a gate line forming metal, so that the thickness of the gate line electrode is substantially increased. By reducing the thickness of the layer and increasing the electric field intensity applied to the liquid crystal layer, the transition to bend alignment can be performed at high speed.

  Since the thickness of the source line electrode is usually about 0.2 μm to 0.6 μm, the thickness of the liquid crystal layer can be reduced accordingly.

(First to fifth embodiments)
FIG. 8 shows a configuration diagram of the first to fifth embodiments.

  Also in this figure, 8 is a gate line electrode, 7 is a source line electrode, 3 is a pixel electrode, 64 is a channel protective film, 65 is an a-Si layer, 66 is an n + a-Si layer, 86 is a gate line electrode and a- An insulating film between the Si layers, 76 is an insulating film between the source line electrode and the liquid crystal layer, 5 is a liquid crystal layer, 9 is a counter electrode, 21 is a transparent pixel electrode, A is a line showing a cross section, and 713 is a gate line. It is a source line forming metal laminated on the electrode without making electrical contact.

  In this structure, the thickness of the liquid crystal layer on the gate line is reduced by using a non-contact type gate line in which a source line forming metal is electrically insulated and interposed between the gate line electrode and the counter electrode, so that the liquid crystal layer is covered. By increasing the electric field strength, the transition to the bend alignment can be made faster.

(1st-6th Embodiment)
FIG. 9 shows a configuration diagram of the first to sixth embodiments. In the figure, 1 is a first substrate, 8 is a gate line electrode, 7 is a source line electrode, 6 is a pixel transistor, 2 is a second substrate, and 91 is a position facing the gate line electrode of the first substrate. The first counter electrode 92 is a second counter electrode that is electrically insulated from the first counter electrode. In the structure of the split-type counter electrode, the first counter electrode and the second counter electrode are electrically insulated, so that a voltage change is caused by a pixel electrode or a pixel transistor via a capacitive load of a liquid crystal layer or an insulating film. The electric field strength can be given to the liquid crystal layer on the gate line electrode while preventing the influence on the liquid crystal layer, and the transition to the bend alignment can be performed at high speed. During normal image display, by setting the first and second counter electrodes to the same potential, it is possible to obtain the same image quality as that of a conventional liquid crystal display device in which the counter electrodes are not patterned.

(1st-7th Embodiment)
FIG. 10 is a sectional view of the liquid crystal display device according to the first to seventh embodiments. In this figure, 1 is a first substrate, 8 is a gate line electrode, 7 is a source line electrode, 87 is an insulating film, 2 is a second substrate, and 11 is a position facing the gate line electrode of the first substrate. Black matrix metal, 12 is a color filter, 5 is a liquid crystal layer, 91 is a first layer counter electrode formed almost uniformly on the entire surface of the second substrate, and 92 is formed at a position facing the gate line of the first substrate. This is the second layer counter electrode. In the structure of the opposed thick-film counter electrode, the thickness of the liquid crystal layer on the gate line can be reduced by increasing the number of counter electrodes facing the gate line to two, and the electric field strength can be increased. Can be done.

(Embodiment 1-8)
FIG. 11 is a sectional view of the liquid crystal display device according to the first to eighth embodiments. Also in this drawing, 1 is a first substrate, 8 is a gate line electrode, 7 is a source line electrode, 87 is an insulating film, 2 is a second substrate, and 11 is a position facing the gate line electrode of the first substrate. Reference numeral 121 denotes a color filter of a first color such as red, 121 denotes a color filter of another second color such as blue, 9 denotes a counter electrode, and 5 denotes a liquid crystal layer.

  In this structure, the color filter forming resin is laminated on a portion of the second substrate facing the gate line electrode of the first substrate, thereby raising the counter electrode in this portion to reduce the thickness of the liquid crystal layer on the gate line. In addition, the electric field strength of the liquid crystal layer can be increased, and the transition to bend alignment can be made faster.

(Embodiment 1-9)
FIG. 12 is a sectional view of the liquid crystal display device according to the first to ninth embodiments. Also in this drawing, 1 is a first substrate, 8 is a gate line electrode, 7 is a source line electrode, 87 is an insulating film, 2 is a second substrate, and 11 is a position facing the gate line electrode of the first substrate. Reference numeral 12 denotes a color filter, reference numeral 111 denotes a columnar spacer formed in a portion of the first substrate facing the gate line, reference numeral 9 denotes a counter electrode, and reference numeral 5 denotes a liquid crystal layer.

  In this structure, a columnar spacer is formed on a portion of the second substrate facing the gate line electrode of the first substrate, and a counter electrode is formed between the columnar spacer and the liquid crystal layer to form a liquid crystal layer on the gate line. The thickness can be reduced, the electric field strength of the liquid crystal layer can be increased, and the transition to bend alignment can be performed at high speed.

  Here, the structure of the liquid crystal panel has been described in the nine embodiments from the first embodiment to the ninth embodiment, but the thickness of the liquid crystal layer on the gate line is determined by combining a plurality of the embodiments. Is easier to obtain than when any of them is used alone, and the effect is further increased by dividing the counter electrode and applying an arbitrary voltage to the electrode facing the gate line.

<< Second invention group >>
The group of the present invention applies a higher voltage between the pixel electrode and the counter electrode than at the time of displaying an ordinary image, or applies two types of voltages for the transition of the liquid crystal layer. And so on.

(Embodiment 2-1)
FIG. 13 shows a configuration centering on a pixel circuit of the liquid crystal device of this embodiment. In this figure, 3 is a pixel electrode. 6 is a pixel transistor. 7 is a source line. 71 is the next source line. 8 is a gate line. 81 is a previous gate line. 9 is a counter electrode. Reference numeral 10 denotes a common electrode connected to all storage capacitors. Cgd is the capacitance between the gate and the drain of the pixel transistor. Cst is a storage capacitor connected to the pixel electrode and formed between the pixel electrode and the common electrode. Clc is the capacity of the liquid crystal layer. Cgs is the capacitance between the gate and the source of the pixel transistor.

  FIG. 14 schematically illustrates a plane and a cross section centered on the structure of the pixel. In this figure, 6 is a pixel transistor, 21 is a transparent pixel electrode, Cst is a storage capacitor connected to the pixel electrode and formed with the common electrode, Clc is a capacitance of the liquid crystal layer, 7 is a source line, and 71 is the following. A source line, 8 is a gate line, 81 is a previous gate line, 9 is a counter electrode, and 10 is a common electrode connected to all storage capacitors.

  FIG. 15 shows an example of the dimension per pixel. In the figure, Wt is the width of a pixel. Lt is the length of the pixel. Wp is the width of the pixel electrode. Lp is the length of the pixel electrode. Ws is the width of the source line. Wg is the width of the gate line. The area of the pixel electrode is 18224 μm 2 in the area of 30000 [μm 2] per pixel, which is 60.7% of one pixel.

  FIG. 16 shows the operation of the liquid crystal device of the present embodiment shown in FIGS.

  In FIG. 16, Vg is the voltage of the gate line. Vs is the voltage of the source line. Vp is the voltage of the pixel electrode. Vcc is the voltage of the common electrode. Vc is the voltage of the counter electrode.

  During normal image display, the voltage Vg of the gate line is changed until the pixel transistor is turned on, and the voltage Vs of the source line is charged to the pixel electrode 21, the storage capacitor Cst, and the liquid crystal capacitor Clc. The voltage Vp of the pixel electrode becomes equal to the voltage Vs of the source line.

  The voltage Vc of the counter electrode only needs to be in a range where the transmittance of the liquid crystal sufficiently changes between the voltage Vp of the pixel electrode and the potential difference Vpc between Vc and Vp is usually set to about 0 V to 5 V. In order to bend the liquid crystal layer, a different potential difference continuous application step of continuously applying a higher potential difference to the liquid crystal layer is required. The potential difference and time required for transition to bend alignment differ depending on the liquid crystal material, but it is experimental that some materials can complete transition within 1 second by applying a potential difference of 6 V or more between the pixel electrode and the counter electrode. Has been confirmed. For a liquid crystal display device, the shorter the transition time is, the better, and it is desirable that the transition time is within a few seconds to 10 seconds. For this purpose, a larger potential difference (about 20 V to 30 V) is given or a liquid crystal material is selected. . It is desirable to apply the potential difference for the liquid crystal layer to bend alignment to be as large as possible, and it is most effective to apply the potential difference between the pixel electrode and the counter electrode as shown in FIG.

(2-2nd Embodiment)
The operation in the second embodiment will be described with reference to FIG. 17, FIG. 14, and FIG.

  In FIG. 17, Vg is the voltage of the gate line. Vs is the voltage of the source line. Vp is the voltage of the pixel electrode. Vcc is the voltage of the common electrode. Vc is the voltage of the counter electrode. The operation of the liquid crystal panel having such a configuration at the time of displaying a normal image is the same as in the first embodiment, and the potential difference Vpc between Vc and Vp is 0 V to 5 V. When a first-type potential difference of 6 V or more is continuously applied between the pixel electrode and the counter electrode in order to cause the transition to the bend alignment, depending on the structure of the liquid crystal panel or the liquid crystal material, the transition state does not progress and the portion where the transition state sticks. May occur and transfer may not be possible even if it takes only 10 seconds or more. In the case of such a panel or liquid crystal material condition, the voltage Vc of the counter electrode is brought close to the voltage Vp of the pixel electrode, and the potential difference Vpc applied to the liquid crystal layer is changed to a small second type of potential difference so that the orientation of the liquid crystal element is initialized. After returning, a high first type potential difference is applied again. As a result, the liquid crystal element that originally transitioned to the bend state easily transitions even if the potential difference is applied again after returning to the initial state, so that the liquid crystal element immediately transitions, and the portion where the transition state has been stuck has a new potential difference. The transition to the bend orientation is facilitated by re-applying, and consequently, the entire panel can be transitioned to the bend orientation in a short time.

  FIG. 18 shows an example of the configuration of the control means of the liquid crystal device according to the present invention. In the figure, reference numeral 205 denotes a liquid crystal panel, 204 denotes a liquid crystal panel controller, and 203 denotes various power supply voltage generation circuits. A start switch 210 is connected to the liquid crystal panel controller 204 from outside. The start switch 210 is connected to a counter 211 inside the liquid crystal panel controller 204 and a switching means A subsequent to the counter 211. Immediately after the start, the counter counts a predetermined period by this counter. A signal is applied to the liquid crystal panel 205. While the predetermined period is being counted, the voltage generating means 1 at 214 and the voltage generating means 2 at 215 are switched by the switching means B 217 at a predetermined cycle set by the cycle counter 216. These voltage generating means are not limited to generating a single voltage. Since the liquid crystal panel 205 is an active matrix and the liquid crystal applied effective potential difference between the pixel electrode and the counter electrode therein is the point, the source line voltage and the gate line which are factors that determine the pixel electrode voltage as well as the counter electrode voltage. Switching is performed by combining a required voltage among the voltage and a common electrode voltage of the storage capacitor described later.

  The predetermined period immediately after the start described here is a period of about 0.1 to 10 seconds, and the predetermined period set by the period counter 216 is about 0.1 to 5 seconds. Time.

  In the present embodiment, the time for making the potential difference Vpc between the pixel electrode and the counter electrode a second type of potential difference is a time for returning the transition to the bend orientation to the initial state, The transition to the bend alignment in the entire liquid crystal panel is completed in a shorter time if the time is shorter than or equal to the time for applying the first type of potential difference. As shown in FIG. 19, when the duty ratio of the first type potential difference applying step in which a high first type potential difference is applied to Vpc exceeds 0.5, the transition time becomes significantly shorter. The step of applying the first type of potential difference is about 0.1 to 3 seconds. Further, the level of the slew rate of the voltage change of the counter electrode generated when switching between the first type potential difference applying step and the second type potential difference applying step does not directly affect the transition time to the bend alignment. For this reason, even when driving a high-load electrode such as a counter electrode, the same effect can be obtained even if the voltage is gradually changed using a driving element having only a small current driving capability. As shown in FIG. 20, when the potential difference Vpc is changed in the repetitive control step of the cycle T, quick transition can be performed even if the times tr and tf required for the change of the potential difference each reach 30% of the cycle T.

The current i [A] required to change the capacitance C [F] by V [V] in t seconds in a circuit as shown in FIG.
i = C * V / t
The current driving capability required to change the counter electrode having a capacitance of 10 [uF] by 10 [V] in 300 milliseconds is 0.33 [mA], which is suitable for a general-purpose operational amplifier or a low-power-consumption operational amplifier. A circuit can be formed by the current driving elements. Although not shown, the capacitive element may be driven by a pulse signal source and a series resistor.

(Second Embodiment)
13, 14, and 15, an operation of a common electrode potential variation type in which a first-type potential difference is increased by a potential change of a common electrode in the first embodiment is described as a third embodiment. Will be described with reference to FIG. The configuration is the same as in the first embodiment.

  In FIG. 22, Vg is the voltage of the gate line. Vs is the voltage of the source line. Vp is the voltage of the pixel electrode. Vcc is the voltage of the common electrode. Vc is the voltage of the counter electrode.

  While the pixel transistor is on, the potential Vs of the source line is written to the pixel electrode. When the pixel transistor is turned off, the penetration voltage calculated by (Equation 2-1) in accordance with the voltage change ΔVg of the gate line. The potential Vp of the pixel electrode changes by ΔVp1. Further, when the potential Vcc of the common electrode serving as the electrode of the storage capacitor is changed by ΔVcc while the pixel transistor is off, a penetration voltage ΔVp2 calculated by (Equation 2-2) is generated at the pixel electrode. In the case of the signal change shown in this drawing, a potential higher than the potential Vs written from the source line can be applied to the pixel electrode by making ΔVp2 larger than ΔVp1, and the potential difference Vpc between the pixel electrode and the counter electrode is reduced. And the transition time of the liquid crystal layer to the bend alignment can be shortened.

ΔVp1 = ΔVg * Cgd / (Cst + Clc + Cgd) (Equation 2-1)
ΔVp2 = ΔVcc * Cst / (Cst + Clc + Cgd) (Equation 2-2)
At this time, as shown in FIG. 23, even if the voltage of the common electrode is the same as the voltage of the gate signal, Vpc can be sufficiently increased, and the size of the power supply circuit can be reduced by sharing the voltage.

(Embodiment 2-4)
FIG. 24 shows a configuration diagram of one pixel of the liquid crystal panel. In this figure, 6 is a pixel transistor, 3 is a pixel electrode, Cgd is a gate-drain capacitance of the pixel transistor, Cst is a storage capacitor connected to the pixel electrode and formed with the previous gate line, and Clc is a liquid crystal layer. The capacitance, Cgs, is the gate-source capacitance of the pixel transistor, 7 is the source line, 71 is the next source line, 8 is the gate line, 81 is the previous gate line, and 11 is the counter electrode. The liquid crystal panel having such a configuration is called a pre-gate system, and the aperture ratio can be increased because the common electrode can be eliminated as compared with the configurations shown in FIGS.

  FIG. 25 is a schematic plan and sectional view of the pixel structure. 6 is a pixel transistor, 21 is a transparent pixel electrode, Cst is connected to the pixel electrode, a storage capacitance formed between the gate line in the previous stage, Clc is a capacitance of a liquid crystal layer, 7 is a source line, and 71 is a next source line. , 8 are gate lines, 81 is a previous gate line, and 9 is a counter electrode.

  FIG. 26 shows an example of the dimension per pixel. Wt is the pixel width, Lt is the pixel length Lt, Wp is the pixel electrode width, Lp is the pixel electrode length, Ws is the source line width, Wg is the gate line width, and Wst is the length of the storage capacitor. The side, Lst, is the gap between the pixel electrode and the gate line, and the area of the pixel electrode is 18564 [μm ^ 2] out of 30,000 [μm ^ 2] per pixel, which is 61.9% of one pixel.

  Referring to FIGS. 24, 25, and 26, a fourth embodiment uses a gate line potential variation type in which a first-type potential difference is increased by a potential change of a gate line in the preceding stage in the second embodiment. The operation will be described with reference to FIG.

  In this figure, Vg is the voltage of the gate line, Vs is the voltage of the source line 7, Vp is the voltage of the pixel electrode, Vg- is the voltage of the preceding gate line 81, and Vc is the voltage of the counter electrode.

  During normal image display, the voltage Vg of the gate line is changed until the pixel transistor is turned on, and the voltage Vs of the source line is charged to the transparent pixel electrode 21, the storage capacitor Cst, and the liquid crystal capacitor Clc. The voltage Vp of the transparent pixel electrode 21 becomes equal to the voltage Vs of the source line 7.

  When the pixel transistor is turned off, the potential Vp of the pixel electrode changes by the penetration voltage ΔVp3 calculated by (Equation 2-3) according to the voltage change ΔVg of the gate line. Further, when the potential Vg- of the preceding gate line, which is the electrode of the storage capacitor, is changed by ΔVg- while the pixel transistor is off, a penetration voltage ΔVp4 calculated by the equation (2-4) is generated at the pixel electrode. I do. In the case of the signal change shown in FIG. 27, by making ΔVp4 larger than ΔVp3, a potential higher than the potential Vs written from the source line can be given to the pixel electrode, and the potential difference Vpc between the pixel electrode and the counter electrode is reduced. And the transition time of the liquid crystal layer to the bend alignment can be shortened.

ΔVp3 = ΔVg * Cgd / (Cst + Clc + Cgd) (Equation 2-3)
ΔVp4 = ΔVg− * Cst / (Cst + Clc + Cgd) (Equation 2-4)
As shown in FIG. 26, the area ratio occupied by the pixel electrode in one pixel is as large as 61.9%. Therefore, it is very effective to apply a large potential difference between the pixel electrode and the counter electrode.

  The potential difference Vpc between Vc and Vp at the time of displaying a normal image in the liquid crystal panel having such a configuration is 0 V to 5 V. When a potential difference of 6 V or more is applied between the pixel electrode and the counter electrode by direct current for transition to the bend alignment, the transition state does not progress depending on the structure of the liquid crystal panel or the liquid crystal material, and the stuck liquid crystal element takes 10 seconds or more. Even if you do, you may not be able to transfer. In the case of such a panel or liquid crystal material condition, the voltage Vc of the counter electrode is brought close to the voltage Vs of the pixel electrode, and the potential difference Vpc applied to the liquid crystal layer is reduced to a second type of potential difference, so that the orientation of the liquid crystal element is initialized. By applying a high first-type potential difference again after returning, a potential difference is reapplied to the portion where the transition state is stuck, and as a result, it is possible to transition to the bend alignment in a short time over the entire panel.

  In the present embodiment, the storage capacitor is provided between the former stage gate line and the storage capacitor is provided between the latter stage gate line.

(2nd-5th Embodiment)
The operation in the second to fifth embodiments will be described with reference to the time chart of the electrode potential of the pixel shown in FIG. 28 and the connection diagram of FIG.

  In FIG. 28, a thick dotted line indicates a counter electrode potential, a thin dotted line indicates a gate line potential, a thin solid line indicates a source line potential, and a thick solid line indicates a pixel electrode potential. The lower Vpc indicates the fluctuation of the potential difference between the pixel electrode and the counter electrode. Tc is a normal video display period, T12 is a first step of applying a second type of potential difference, T11 is a step of applying a first type of potential difference, T22 is a step of applying a second type of potential difference, and T21 is a second time. This is a first type of potential difference applying step. The figure shows various pixel electrode potential fluctuation factors.

  In the figure, T12, T11, T22 and T21 are repeated in a repetitive control step. When the second type of potential difference applying step T12 of the first drive period for the liquid crystal layer bend alignment starts, the counter electrode potential is set to a second potential different from the normal video display period. The pixel electrode potential is connected to the counter electrode via the liquid crystal capacitor. At this moment, since the pixel transistor is off and no current is supplied, the change in the counter electrode potential ΔVcom is given by (2-5) The potential changes by the indicated ΔVp5 in the direction in which the counter electrode potential has changed as shown on the left side of the period T12 in the drawing.

ΔVp5 = ΔVcom * Clc / (Clc + Cst + Cgd) (Equation 2-5)
The potential variation ΔVg when the gate line potential changes the pixel transistor from on to off affects the pixel electrode is ΔVp6 shown in (2-6).

  When the source line potential is a potential obtained by adding ΔVp6 to the potential of the common electrode, and the pixel transistor is turned off, the potential of the pixel electrode decreases by ΔVp6 as shown by the fluctuation of the potential of the central gate electrode in the period T12 in FIG. Is a second type of potential difference of substantially zero.

ΔVp6 = ΔVg * Cgd / (Clc + Cst + Cgd) (Equation 2-6)
Thereafter, during the first second type of potential difference applying step T12, the potential difference between the pixel electrode potential and the counter electrode potential except during a small charging step in which the pixel transistor is turned on and the pixel electrode is charged with the source line potential. Becomes a second kind of potential difference of almost zero.

  When the process proceeds from the first-time second-type potential difference applying step T12 to the first-time first-type potential difference applying step T11, the potential difference between the pixel electrode potential and the common electrode potential is changed to the first type potential difference by the common electrode potential difference. Is changed to the first potential, and the pixel electrode potential changes in the direction in which the counter electrode potential has changed, like the counter electrode potential change shown on the left side of the period T11 in FIG.

  When the pixel transistor is turned on and off once in a small charging step, the source electrode potential is set to a potential obtained by adding .DELTA.Vp6 to the counter electrode potential, as in the first time of the second type of potential difference applying step T12. In the first type of potential difference application step, the potential difference between the pixel electrode potential and the counter electrode potential is sufficiently large for the liquid crystal layer to transition to the bend alignment. The counter electrode potential is set so as to have one type of potential difference. Thereafter, during the first type of first-type potential difference applying step T11, the first-type potential difference required for the transition of the liquid crystal layer to the bend alignment is given as the potential difference between the pixel electrode potential and the counter electrode potential. .

  When the second type second potential difference application step T22 starts, the potential of the pixel electrode changes due to the change of the potential of the counter electrode, so that the potential of the pixel electrode on the left side of the period T22 in FIG. T12), the potential changes in the direction in which the potential of the counter electrode changes. If the pixel transistor is turned on and off once in the small charging step, the pixel transistor is turned on and the pixel electrode is charged with the source line potential in the same manner as in the first type 2 potential difference applying step T12. The potential difference between the pixel electrode and the counter electrode is a second type of potential difference of substantially zero.

  When a transition is made from the second type of potential difference applying step T22 for the second time to the first type of potential difference applying step T21 for the second time, as in the first type of potential difference applying step of the first type, the potential difference between the pixel electrode and the counter electrode becomes equal to that of the liquid crystal. A first type of potential difference required for the transition of the layer to the bend orientation is provided.

  Thereafter, the second type of potential difference application step and the first type of potential difference application step are alternately repeated in the repetitive control step until the transition of the liquid crystal layer to the bend alignment is completed. The potential difference between the pixel electrode and the counter electrode is almost zero, the second type of potential difference, and the first type of potential difference until the pixel transistor is turned on and the pixel transistor is not turned on in a small charging step. In the application step, a sufficiently large first-type potential difference required for the liquid crystal layer to transition to the bend alignment is given between the pixel electrode and the counter electrode except during the period from the start of the period until the first pixel transistor is turned on. I have.

  A first type of potential difference applying step for increasing the potential difference between the pixel electrode and the counter electrode to generate a bend alignment nucleus and expanding a bend region; and reducing the potential difference between the pixel electrode and the counter electrode to bend alignment. A second type of potential difference applying step for alternately realigning the liquid crystal layer in a portion where no nucleus of the nucleus does not occur or the bend region is not enlarged is applied alternately, so that the entire surface of the panel is rapidly transitioned to the bend alignment. Can be.

  The second type potential difference between the pixel electrode and the counter electrode during the second type potential difference applying step is desirably zero, but if it is within ± 1 V as shown in FIG. Does not affect much. The storage capacitance Cst, the liquid crystal capacitance Clc, and the gate-drain capacitance Cgd vary depending on the film thickness and film quality both inside the panel and between the panels, and the variation ΔVp6 of the pixel electrode potential affected by the variation of the gate line potential. A variation occurs, but if the variation falls within ± 1 V, it is not necessary to adjust the source line potential in the second type of potential difference applying step for each of the pads 37, and a driving method in which the source line potential is fixed can be determined.

(2nd to 6th embodiments)
The operation of the sixth embodiment when the source line potential is changed in accordance with the ON / OFF timing of the pixel transistor in the second type potential difference applying step of the fifth embodiment with reference to FIGS. explain.

  FIG. 30 shows a time chart of the electrode potential of the pixel shown in FIG.

  In this figure, a thick dotted line indicates a counter electrode potential, a thin dotted line indicates a gate line potential, a thin solid line indicates a source line potential, and a thick solid line indicates a pixel electrode potential. The lower Vpc is the potential difference between the pixel electrode and the counter electrode, and Vsc is the potential difference between the source line and the counter electrode. Tc is a normal video display period, T12 is a first step of applying a second type of potential difference, T11 is a step of applying a first type of potential difference, T22 is a step of applying a second type of potential difference, and T21 is a second time. This is a first type of potential difference applying step. Also, various factors of the fluctuation of the pixel electrode potential are shown.

  In this figure, when the first type of second potential difference applying step T12 of the first drive period for bend alignment of the liquid crystal layer is started, the counter electrode potential is set to a second potential different from the normal video display period. Assuming that the change in the counter electrode potential is ΔVcom, the pixel electrode potential changes by ΔVp5 in the direction in which the counter electrode potential changes as shown in the counter electrode potential change in FIG. . When the source line potential is set to a potential obtained by adding ΔVp6 to the counter electrode potential, and the pixel transistor is turned on and off once in a small charging step, the pixel electrode potential decreases by ΔVp6 as shown in the gate electrode potential variation in FIG. The potential difference between the electrode and the electrode becomes a second kind of potential difference of substantially zero. The source line potential is substantially equal to the potential of the counter electrode while the pixel transistor is off, and is varied according to the ON / OFF timing of the pixel transistor in a small charging step, such as Vsc.

  Thereafter, during the first second-type potential difference applying step T12, the pixel transistor is turned on / off at the same timing as in the normal video display period, and the source line potential changes each time, and the pixel transistor is turned off. The potential difference between the pixel electrode / counter electrode and the pixel electrode / source line potential is a second type of potential difference of almost zero.

  When the potential difference between the source line potential and the counter electrode when the pixel transistor is off is within the range of ± 1 V, there is no change in the in-plane transition completion time. This is the same as that described in FIG. 29 in which the in-plane transition completion time is not significantly affected if the potential difference between the pixel electrode and the counter electrode is within ± 1 V in the fifth embodiment. .

  When the process proceeds from the first second-type potential difference applying step T12 to the first first-type potential difference applying step T11, the potential of the counter electrode is set to the first type in order to make the potential difference between the pixel electrode and the counter electrode a first type of potential difference. As a result, the pixel electrode potential changes by ΔVp5 in the direction in which the counter electrode potential changes, as shown by the change in the counter electrode potential on the left side of the period T11 in FIG. When the pixel transistor is once turned on and off in a small charging step as in the first time of the second type of potential difference applying step T12 by applying the source line potential to the counter electrode potential plus ΔVp6, the pixel electrode potential is changed to the second type of potential difference application. It becomes almost equal to the counter electrode potential of the step.

  Also in this first type potential difference applying step, the source line potential changes at the timing of turning on and off the pixel transistor. In the first type potential difference applying step, the source line potential between the pixel electrode and the counter electrode and between the source line and the counter electrode are changed. The potential difference is substantially equal to the potential difference between the counter electrode potential in the second type potential difference applying step and the counter electrode potential in the first type potential difference applying step. Therefore, the potential of the common electrode in each period is set so that the potential difference between the common electrode potential in the first type potential difference applying step and the common electrode potential in the second type potential difference applying step becomes the first type potential difference required for the liquid crystal layer transition. Set.

  When the second type of second potential difference applying step T22 starts, the counter electrode potential changes, so that the pixel electrode potential is shown by the counter electrode potential fluctuation on the left side of the period T22 in FIG. The potential changes in the direction in which the potential of the counter electrode changes as shown in FIG. In the subsequent charging operation by the pixel transistor, the pixel electrode potential changes in the same manner as in the first step of applying the second type of potential difference, and becomes substantially equal to the counter electrode potential.

  When the process proceeds from the second-time second-type potential difference applying step T22 to the second-time first-type potential difference applying step T21, the counter electrode potential changes in the same manner as in the first-time first type potential difference applying step. Also, when the pixel transistor is charged by the pixel transistor, a first type potential difference similar to that in the first type of first type potential difference applying step T11 is applied between the pixel electrode and the counter electrode.

  Thereafter, the second type of potential difference applying step and the first type of potential difference applying step are alternately repeated in the control step until the transition of the liquid crystal layer to the bend alignment is completed. The potential difference between the electrodes and between the source line and the counter electrode is almost zero, which is the second kind of potential difference. In the first kind of potential difference applying step, the liquid crystal layer is required to transition to the bend alignment between the pixel electrode and the counter electrode. A sufficiently large first-type potential difference is provided.

  In this example, in addition to the operation described in the fifth embodiment, during the second-type potential difference applying step, the potential difference between the pixel electrode and the source line occupying most of the area in the plane and the counter electrode is reduced to zero. Therefore, the transition to the bend alignment of the liquid crystal layer can be further accelerated as compared with the fifth embodiment, although there is the complexity of fluctuating the source line potential.

(2nd-7th embodiment)
31. Second and seventh embodiments in which the pixel electrode is charged by turning on the pixel transistor of the fifth embodiment once in the initial period of the drive period for bend alignment of the liquid crystal layer with reference to FIGS. Will be described.

FIG. 31 shows a time chart of the electrode potential of the pixel shown in FIG.
In FIG. 31, a thick dotted line indicates a counter electrode potential, a thin dotted line indicates a gate line potential, a thin solid line indicates a source line potential, and a thick solid line indicates a pixel electrode potential. The lower Vpc is a potential difference between the pixel electrode and the counter electrode. Tc is a normal video display period, T12 is a first type of second type potential difference applying step, T11 is a first type of first type potential difference applying step, T22 is a second type of second type potential difference applying step, and T21 is a second type of potential difference applying step. This is a first type of potential difference applying step. In addition, various factors of the fluctuation of the pixel electrode potential are also shown.

  In this figure, when the first type of second potential difference applying step T12 of the first drive period for bend alignment of the liquid crystal layer is started, the counter electrode potential is set to a second potential different from the normal video display period. The pixel electrode potential changes by ΔVp5 in the direction in which the counter electrode potential changes, as shown by the counter electrode potential change within the period T12 in the drawing, under the influence of the counter electrode potential change. When the source line potential is a potential obtained by adding ΔVp6 to the potential of the common electrode, and once the pixel transistor is turned on and off, the potential of the pixel electrode decreases by ΔVp6 as shown in the gate electrode potential variation in the figure, and is substantially equal to the potential of the common electrode. Become. Thereafter, during the first second type potential difference applying step T12, there is no change in the gate line potential, and the potential difference between the pixel electrode potential and the counter electrode potential 1 remains substantially the second type potential difference.

  When the process proceeds from the first-time second-type potential difference applying step T12 to the first-time first-type potential difference applying step T12, the counter electrode potential is set to the first type in order to make the potential difference between the pixel electrode and the counter electrode a first type potential difference. , And the pixel electrode potential changes by ΔVp5 in the direction in which the counter electrode potential has changed as shown by the left counter electrode potential fluctuation during the period T12 in FIG. Even if the process proceeds to the first type potential difference applying step, the pixel electrode is not charged by turning on the pixel transistor, so that the potential of the pixel electrode maintains the potential affected by the fluctuation of the counter electrode potential. The potential of the common electrode is set so that the potential difference between them becomes a sufficiently large first type potential difference required for the transition of the liquid crystal layer to the bend alignment.

  When the second type potential difference applying step T22 of the second time starts, the counter electrode potential changes to the second potential, so that the pixel electrode potential is influenced by the counter electrode potential shown in the transition portion from the period T12 to the period T22 in FIG. As shown by the potential fluctuation, the potential changes in the direction in which the potential of the common electrode has changed. The potential is equal to the potential of the pixel electrode due to the potential change of the gate electrode in the first-time second-type potential difference applying step T12. Is a second type of potential difference of substantially zero.

  When a transition is made from the second type of potential difference applying step T22 for the second time to the first type of potential difference applying step T21 for the second time, the counter electrode potential changes to the first potential as in the first type of potential difference applying step of the first type. However, even during this period, the pixel electrode is not charged, and a first type potential difference similar to that in the first first type potential difference application step is applied between the pixel electrode and the counter electrode.

  Thereafter, the second type of potential difference applying step and the first type of potential difference applying step are alternately repeated in the control step until the transition of the liquid crystal layer to the bend alignment is completed. The potential difference between the electrodes becomes a second type potential difference of almost zero. In the first type potential difference applying step, a sufficiently large first type potential difference required for the liquid crystal layer to transfer between the pixel electrode and the counter electrode is generated. Given.

  In this example, although it is complicated to change the on / off timing of the pixel transistor from the normal video display period, the number of times the pixel electrode is charged by turning on the pixel transistor during the second type potential difference applying step is smaller than the normal timing. The time during which the potential difference between the pixel electrode and the counter electrode is zero increases during the second type of potential difference application step, and the transition of the liquid crystal layer to the bend alignment can be performed faster than in the fifth embodiment.

  Note that when the pixel electrode is not sufficiently charged by one turn-on of the pixel transistor, or when the drive period for transitioning the liquid crystal layer to the bend alignment starts asynchronously with the normal video display period, the pixel transistor is turned on. When a margin of the number of times is necessary to surely turn on, it is effective to charge the pixel electrode several times instead of once by turning on the pixel transistor at the beginning of the driving period for shifting the liquid crystal layer to the bend alignment. Does not affect much.

  The first turning on of the pixel transistor is performed within one field period (normally 16.7 milliseconds) after switching from normal video display timing to driving for bend alignment of the liquid crystal layer is completed. .

(2-8th Embodiment)
32 and 13, a first-type potential difference applying step in a driving period for bend-aligning the liquid crystal layer by charging the pixel electrode by turning on the pixel transistor in the small charging step of the fifth embodiment; The operation of the eighth embodiment in the case of performing once at the beginning of each of the two potential difference applying steps will be described.

  FIG. 32 shows a time chart of the electrode potential of the pixel shown in FIG.

  In this figure, a thick dotted line indicates a counter electrode potential, a thin dotted line indicates a gate line potential, a thin solid line indicates a source line potential, and a thick solid line indicates a pixel electrode potential. The lower Vpc is a potential difference between the pixel electrode and the counter electrode. Tc is a normal video display period, T12 is a first step of applying a second type of potential difference, T11 is a first step of applying a first type of potential difference, T22 is a step of applying a second type of potential difference, and T21 is a second step of applying a second type of potential difference. This is a first type potential difference applying step. Also, various factors of the fluctuation of the pixel electrode potential are shown.

  In FIG. 32, when the second type of potential difference application step T12 of the first drive period for the liquid crystal layer bend alignment starts, the counter electrode potential is set to a second potential different from the normal video display period. The pixel electrode potential is affected by the change in the counter electrode potential, and the potential changes by ΔVp5 in the direction in which the counter electrode potential changes as indicated by the change in the counter electrode potential on the left side in the period T12 in the drawing.

  When the source line potential is set to a potential obtained by adding ΔVp6 to the counter electrode potential, and the pixel transistor is turned on and off once in a small charging step, the pixel electrode potential decreases by ΔVp6 as shown by the gate electrode potential variation at the center in the period T12. It becomes almost equal to the counter electrode potential. Thereafter, during the first second-type potential difference applying step T12, there is no change in the gate line potential, and the second-type potential difference between the pixel electrode and the counter electrode remains substantially zero.

  When the process proceeds from the first second-type potential difference applying step T12 to the first first-type potential difference applying step T11, the counter electrode potential is set to the first type in order to make the potential difference between the pixel electrode and the counter electrode a first type potential difference. , And the pixel electrode potential changes by ΔVp5 in the direction in which the counter electrode potential changes as shown by the left counter electrode potential fluctuation during the period T11. When the pixel transistor is once turned on and off in a small charging step as in the case of the first time of the second type of potential difference applying step T12 by adding ΔVp6 to the common electrode potential, the pixel electrode potential becomes the same as the gate electrode potential variation, as in the first type T2 of the second type of potential difference application. , The potential of the counter electrode in the second type potential difference applying step is substantially equal to the potential of the counter electrode.

  Thereafter, during the first type of first-type potential difference application step T11, the pixel electrode is not charged due to the pixel transistor being turned on, so that the pixel electrode potential does not change. Thus, in the first type of potential difference application step, the potential difference between the pixel electrode and the counter electrode is substantially equal to the potential difference between the counter electrode potential in the second type potential difference application step and the counter electrode potential in the first type potential difference application step. Therefore, the counter electrode potential in each period is set so that the potential difference between the counter electrode potential in the first type potential difference application step and the counter electrode potential in the second type potential difference application step becomes a potential difference required for transition of the liquid crystal layer to the bend alignment. Set.

  When the second type of second potential difference applying step T22 starts, the potential of the common electrode changes because the potential of the pixel electrode changes due to the influence of the potential of the common electrode, as shown by the change in the potential of the common electrode at the boundary between the periods T12 and T22. The potential changes in the changed direction. In the subsequent pixel electrode charging operation by turning on the pixel transistor, the potential becomes the pixel electrode potential in the first type of second potential difference application step, and the potential difference from the counter electrode potential becomes a second type potential difference of substantially zero.

  When the process proceeds from the second-time second type of potential difference applying step T22 to the second-time first type of potential difference applying step T21, the counter electrode potential changes in the same manner as in the first-time first type potential difference applying step. Also during the initial turning on of the pixel transistor, a first type potential difference similar to that in the first first type potential difference applying step is applied between the pixel electrode and the counter electrode.

  Thereafter, the second type of potential difference applying step and the first type of potential difference applying step are alternately repeated in the control step until the transition of the liquid crystal layer to the bend alignment is completed. The potential difference between the electrodes becomes a second type potential difference of almost zero. In the first type potential difference applying step, the potential difference between the pixel electrode and the counter electrode is a sufficiently large first type potential difference necessary for the liquid crystal layer to transfer. Is given.

  By charging the pixel electrode with the source line potential only once at the beginning of each period, the control of the pixel transistor on / off timing becomes more complicated than in the seventh embodiment. While reducing the time when the pixel transistor is turned on during the potential difference applying step and the potential difference between the pixel electrode and the counter electrode is not zero, the pixel electrode potential is determined at the beginning of each period to eliminate the influence of the fluctuation of the counter electrode potential, The transition to the bend alignment over the entire panel is faster than in the fifth and seventh embodiments.

  Similarly to the seventh embodiment, when the pixel electrode is not sufficiently charged by one turn-on of the pixel transistor, or when the driving period for shifting the liquid crystal layer to the bend alignment is longer than the normal video display period. If a margin is required to start the pixel transistor asynchronously and turn on the pixel transistor reliably, the effect of charging the pixel electrode by turning on the pixel transistor at the beginning of each period several times instead of once is not so large. do not do.

(2-9th Embodiment)
The operation of the ninth embodiment when the off-voltage of the gate line is set to DC during the drive period for bend-aligning the liquid crystal layer of the fifth embodiment will be described with reference to FIGS.

  FIG. 33 shows a time chart of the electrode potential of the pixel shown in FIG.

  In this drawing, the electrical operation timing during the drive period for bend-aligning the liquid crystal layer is the same as in the fifth embodiment. In the liquid crystal panel having the structure shown in FIG. 24, a storage capacitor Cst is formed between the gate line 81 and the transparent pixel electrode 21 in the preceding stage, and a potential difference is given between adjacent rows of pixels during the normal video display period. The potential of the previous gate line and the potential of the counter electrode are changed in the same direction. This operation is performed while the gate line selects the potential for turning off the pixel transistor, that is, the off voltage.

  If this operation continues even during the driving period for bend alignment of the liquid crystal layer, the pixel electrode potential fluctuates by ΔVp6 of the equation (6) due to the fluctuation of the off-state voltage of the preceding gate line. Therefore, a potential difference of several volts is generated even if it is desired to make the potential difference between the pixel electrode and the counter electrode a second-type potential difference of substantially zero. When the potential difference between the pixel electrode and the counter electrode in the second type of potential difference application step exceeds 1 volt as shown in FIG. 29, the transition completion time becomes longer.

  Therefore, during the drive period for bend alignment of the liquid crystal layer as shown in FIG. 33, the off voltage of the gate line is changed to DC in the step of holding the gate line off voltage DC, so that the pixel electrode in the second type potential difference applying step is changed. Can be avoided, and the transition to bend alignment over the entire panel can be speeded up.

(2nd to 10th embodiments)
The operation in the tenth embodiment will be described with reference to FIGS.

  FIG. 34 shows a time chart of the electrode potential of the pixel shown in FIG.

  In this figure, a thick dotted line indicates a counter electrode potential, a thin dotted line indicates a gate line potential, a thin solid line indicates a source line potential, and a thick solid line indicates a pixel electrode potential. The lower Vpc is a potential difference between the pixel electrode and the counter electrode, and Vsc is a potential difference between the source line and the counter electrode. Tc is a normal video display period, T12 is a first step of applying a second type of potential difference, T11 is a step of applying a first type of potential difference, T22 is a step of applying a second type of potential difference, and T21 is a second time. This is a first type of potential difference applying step. Also, various factors of the fluctuation of the pixel electrode potential are shown.

  In FIG. 34, when the second type of potential difference applying step T12 of the first driving period for the liquid crystal layer bend alignment is started, the counter electrode potential is set to a second potential different from the normal video display period. The pixel electrode potential 4 is connected to the counter electrode via the liquid crystal capacitance Clc. At this moment, the pixel transistor is turned off and there is no current supply. Therefore, for the change in the counter electrode potential ΔVcom, ΔVp5 in equation (5) is equal to T12. The potential changes in the direction in which the counter electrode potential changes, as indicated by the change in the counter electrode potential at the left end. When the source line potential is set to a potential obtained by adding ΔVp6 to the counter electrode potential, and the pixel transistor is turned on and off once in a small charging step, the pixel electrode potential decreases by ΔVp6 as shown by the gate electrode potential fluctuation at the center of the period T12. It becomes almost equal to the counter electrode potential.

  When the process proceeds from the first second-type potential difference applying step T12 to the first first-type potential difference applying step T11, the potential difference between the pixel electrode and the counter electrode is changed to the first type potential difference. 1 and the pixel electrode potential changes by ΔVp5 in the direction in which the counter electrode potential changes as shown by the change in the counter electrode potential at the boundary between the periods T11 and T12. When the pixel transistor is once turned on and off in a small charging step as the potential of the counter electrode plus ΔVp6 as in the first time of the second type of potential difference applying step T12, the pixel electrode potential becomes the gate electrode potential in the period T11. As in the case of the fluctuation, the voltage decreases due to the influence of the potential fluctuation of the gate line potential.

  In the first-type potential difference applying step, the transition to the bend alignment of the liquid crystal layer can be accelerated as the potential difference between the pixel electrode and the counter electrode increases, so that the second-type potential difference applying step is changed to the first-type potential difference applying step. The source line potential is changed in a direction opposite to the change in the counter electrode potential. The counter electrode potential is set so that the potential difference from the pixel electrode potential is a first type potential difference required for transition of the liquid crystal layer to bend alignment.

  When the second type second potential difference applying step T22 starts, the potential of the common electrode changes because the potential of the common electrode changes due to the change in the potential of the common electrode as shown in the variation of the common electrode potential at the boundary between the periods T12 and T22. The potential changes in the changed direction. In the subsequent pixel electrode charging operation by turning on the pixel transistor, the potential becomes the pixel electrode potential in the first type of second potential difference application step, and the potential difference with the counter electrode potential becomes a second type potential difference of substantially zero.

  When the process proceeds from the second-time second type of potential difference applying step T22 to the second-time first type of potential difference applying step T21, the counter electrode potential changes in the same manner as in the first-time first type potential difference applying step. Even during the charging of the pixel electrode by turning on the pixel transistor, the same first-type potential difference as in the first-time first-type potential difference applying step is applied between the pixel electrode and the counter electrode.

  Thereafter, the second type of potential difference application step and the first type of potential difference application step are alternately repeated in the repetitive control step until the transition of the liquid crystal layer to the bend alignment is completed. Unless the pixel transistor is turned on and the pixel electrode is charged in the small charging step until the second pixel transistor is turned on, the potential difference between the pixel electrode and the counter electrode becomes a second type potential difference of almost zero, In one type of potential difference application step, a sufficiently large first type potential difference necessary for the liquid crystal layer to transition to the bend alignment is applied between the pixel electrode and the counter electrode except during the period from the start of the period until the first turn on of the pixel transistor. Can be

  By varying the source line potential between the second type potential difference applying step and the first type potential difference applying step, the first type potential difference applying step increases the first type potential difference between the pixel electrode and the counter electrode in the first type potential difference applying step. Therefore, the transition of the liquid crystal layer to the bend alignment can be accelerated.

  FIG. 35 shows the case where the driving period for bend-aligning the liquid crystal layer in the fifth and sixth embodiments is started from the first type of potential difference applying step, and the case where the driving period is changed from the second type of potential difference applying step. The measurement result of the time required until the transfer is completed in the case of starting is shown.

  The horizontal axis shows the first type of potential difference between the pixel electrode and the counter electrode in the first type of potential difference application step. The greater the potential difference, the shorter the transition completion time. When the process is started from the potential difference applying step, the transition to the bend orientation is completed earlier.

(Embodiment 2-11)
The operation in the eleventh embodiment will be described with reference to FIG. 36 and FIG.

  In FIG. 36, a thick dotted line indicates a counter electrode potential, a thin dotted line indicates a gate line potential, a thin solid line indicates a source line potential, and a thick dotted line indicates a pixel electrode potential. Vpc is a potential difference between the pixel electrode and the counter electrode. Three Tc are a normal image display period, T12 is a first type of second type potential difference applying step, T11 is a first type of first type potential difference applying step, T22 is a second type of second type potential difference applying step, and T21 is a second type of potential difference applying step. This is the second type of potential difference application step of the first type. Also, various factors of the fluctuation of the pixel electrode potential are shown.

  In this figure, when the first type of second potential difference applying step T12 of the first drive period for bend alignment of the liquid crystal layer is started, the counter electrode potential is set to a second potential different from the normal video display period. The pixel electrode potential is connected to the counter electrode via the liquid crystal capacitance Clc. At this moment, since the pixel transistor is off and no current is supplied, the pixel electrode potential is shown at the left end of T12 by ΔVp5 with respect to the counter electrode potential variation ΔVcom. Thus, the potential changes in the direction in which the potential of the counter electrode changes.

  When the source line potential is set to a potential obtained by adding ΔVp6 to the potential of the common electrode, and the pixel transistor is once turned on and off in a small charging step, the potential of the pixel electrode decreases by ΔVp6 as shown in the center of the present T12, and becomes substantially equal to the potential of the common electrode. Become equal. Thereafter, during the first second-type potential difference applying step, the potential difference between the pixel electrode potential and the counter electrode potential is not except when the pixel transistor is turned on in the small charging step and the pixel electrode is charged with the source line potential. A second type of potential difference of almost zero results.

  When the process proceeds from the first-time second-type potential difference applying step T12 to the first-time first-type potential difference applying step T11, the potential difference between the pixel electrode potential and the common electrode potential is changed to the first type potential difference by the common electrode potential difference. Is changed to the first potential, and the pixel electrode potential changes by ΔVp5 in the direction in which the counter electrode potential changes under the influence of the first potential. When the pixel transistor is once turned on and off in a small charging step as a potential obtained by adding ΔVp6 to the counter electrode potential as in the case of the first-time second type potential difference applying step T12 of the second type of potential difference applying step T12, the pixel electrode potential is changed in the potential of the gate line potential. In the first type of potential difference application step, the potential difference between the pixel electrode potential and the counter electrode potential changes to the bend alignment of the liquid crystal layer, although the potential drops to almost the same potential as the counter electrode potential in the second type potential difference application step due to the influence of The potential of the counter electrode is set so as to be a sufficiently large first-type potential difference necessary for the operation. Thereafter, during the first type of first-type potential difference applying step T11, the first-type potential difference required for the transition of the liquid crystal layer to the bend alignment is given as the potential difference between the pixel electrode potential and the counter electrode potential. .

  When the second-time second type potential difference applying step T22 starts, the counter electrode potential changes, so that the pixel electrode potential is influenced by the potential in the direction in which the counter electrode potential changes as indicated by the first counter electrode potential change in T22. However, when the pixel transistor is turned on and off once, the pixel transistor is turned on and the pixel is charged except when the source electrode potential is charged to the pixel electrode, as in the first type T2 of the second type of potential difference application. The potential difference between the electrode and the counter electrode is a second type of potential difference of substantially zero.

  When the process proceeds from the second-time second-type potential difference applying step T22 to the second-time first-type potential difference applying step T21, the counter electrode potential changes in the same manner as in the first-time first type potential difference applying step. Is turned on and the pixel electrode is charged with the source line potential and the pixel transistor is turned off, the potential difference between the pixel electrode potential and the counter electrode potential is necessary for the transition of the liquid crystal layer to the bend alignment. A first type of potential difference is provided.

  Thereafter, the second type of potential difference applying step and the first type of potential difference applying step are alternately repeated in the repetitive control step until the transition of the liquid crystal layer is substantially completed, and in the second type of potential difference applying step, the first pixel after the start of the period Until the transistor is turned on and when the pixel transistor is not turned on, the potential difference between the pixel electrode and the counter electrode becomes a second type potential difference of almost zero, and in the first type potential difference applying step, the potential difference is 1 after the start of the period. A sufficiently large first-type potential difference necessary for the liquid crystal layer to transition to the bend alignment is given between the pixel electrode and the counter electrode except during the period until the second pixel transistor is turned on.

  When the transition to the bend alignment of the liquid crystal layer is almost completed and before the transition to the normal video display period Tc, video information having a large potential difference between the pixel electrode and the counter electrode in the transition high potential difference applying step (usually black or white). Is displayed in one field, the enlargement of the bend alignment region of the liquid crystal layer is completed, and thereafter, the process shifts to the next normal video display period Tc for displaying the original input video information.

  Usually, the first type of potential difference application step and the second type of potential difference application step are often several fields or more and several hundred milliseconds or more in time, and are required to complete the transition to the bend alignment of the liquid crystal layer. When one type of potential difference applying step or the second type of potential difference applying step is added once, the transition completion time increases in units of several hundred milliseconds. When the transition is completed only by expanding the bend area without generating a new bend nucleus, displaying video information with a large potential difference between the pixel electrode and the counter electrode can be added by adding several tens of milliseconds. In addition, the transfer completion time can be shortened.

<< Third invention group >>
The present invention relates to control of startup of each unit when power is turned on.

  Hereinafter, the third invention group will be described based on the embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS. 37 and 38. The present invention has only one embodiment.

  In FIG. 37, Vg is a gate line potential. Vs is the potential of the source line. Vp is the potential of the pixel electrode. Vpc is a potential difference between the pixel electrode and the counter electrode. To is a power-off period, and T12 is a first type of second potential difference applying step. T11 is a first type of potential difference application step of the first type, and Tc is a display period of a normal image. Also, various factors of the fluctuation of the pixel electrode potential are shown.

  38, reference numeral 3801 denotes a main power supply, 3802 denotes a power supply circuit controller, 3803 denotes various power supply voltage generation circuits, 3804 denotes a liquid crystal panel controller, and 3805 denotes a liquid crystal panel. A start switch 3810 is connected to the main power supply 3801 and the liquid crystal panel controller 3804 from outside. The start switch 3810 is connected to a counter 3811 inside the liquid crystal panel controller 3804 and a switching means A of 3812 following the counter 3811. After the power is supplied to the liquid crystal panel controller 3804 after the start, a predetermined period is set by the counter. After counting, the video signal from the normal video signal generation unit 3813 is applied to the liquid crystal panel 3805. While the predetermined period is being counted, the voltage generation means 1 of 3814 and the voltage generation means 2 of 3815 are switched by the switching means B 3817 at a predetermined cycle set by the cycle counter 3816.

  In the circuit of FIG. 38, all signals input to the liquid crystal panel are undefined during the power-off period To. When the start switch 3810 is turned on to turn on the power, first, power is supplied only to the power supply circuit controller 3802, and the controller 3802 sequentially controls various power supply voltage generation circuits to start the operation of the liquid crystal panel controller. By adopting such a circuit configuration having a liquid crystal layer stable holding start-up control step, it becomes possible to immediately set the voltage of the second type potential difference application step after turning on a signal input to the liquid crystal panel, The transition period of the liquid crystal layer to the bend alignment can be started without breaking the alignment state of the liquid crystal layer in the state where no voltage is applied, and the transition completion time after turning on the power can be shortened.

  When no voltage is applied, the liquid crystal layer is aligned in the splay alignment state along the rubbing groove of the substrate. However, when any potential difference is applied, the liquid crystal elements which are liable to transition to the bend alignment start in order. If a liquid crystal element that remains in splay alignment and a liquid crystal element that is about to shift to bend alignment are randomly mixed in the liquid crystal panel surface, even if a large potential difference is applied to those liquid crystal elements at the same time, the transition to lubricious bend alignment will occur. May not be done. In this embodiment mode, the occurrence of a liquid crystal element which starts transition to bend alignment by applying a random potential difference immediately after the power of the liquid crystal device is turned on is suppressed, and the transition to bend alignment with respect to the liquid crystal element in which the entire surface is in a splay alignment state is suppressed. It is intended to start driving for.

    Table 1 shows an example of an experimental result by the driving method according to the present embodiment.

本実施の形態の駆動方式とは、電源投入後、液晶パネルに入力する対向電極電位、ゲート線電位、ソース線電位が全て、第２種の電位差印加ステップで出力されるべき電圧を出力するものである。一方、第２種の電位差印加ステップ前に通常の映像の表示期間がある従来の方式では、電源投入後各種電源電圧発生回路が無制御のまま立ちあがり、第２種の電位差印加ステップの前に通常映像表示期間と同様の電圧が対向電極電位、ゲート線電位、ソース線電位に出力される。これら２方式で第２種の電位差印加ステップの所要時間を変えて転移完了状態を観測すると、本実施の形態の駆動方式のほうが短時間で転移が完了することがわかった。

The driving method according to the present embodiment refers to a method in which, after power is turned on, a counter electrode potential, a gate line potential, and a source line potential input to a liquid crystal panel all output voltages to be output in a second type of potential difference applying step. It is. On the other hand, in the conventional method in which there is a normal video display period before the second type of potential difference applying step, various power supply voltage generating circuits start up without power control after the power is turned on, and usually before the second type of potential difference applying step. The same voltage as in the video display period is output to the common electrode potential, the gate line potential, and the source line potential. Observing the transition completion state by changing the time required for the second type potential difference applying step in these two methods, it was found that the transition was completed in a shorter time in the driving method of the present embodiment.

  In the embodiments of the second invention group and the present invention group, the source line potential does not need to be similarly changed between the first type of potential difference applying step and the second type of potential difference applying step, and differs in each period. There is no problem if the timing changes at different potentials.

  As described above, the present invention has been described based on some embodiments, but it is needless to say that the present invention is not limited to these embodiments. That is, for example, the following may be performed.

  1) The liquid crystal device is not a liquid crystal display device but a liquid crystal plasma display, an organic EL or the like.

  2) The liquid crystal display device is of a reflection type, that is, a so-called ROCB.

3) The liquid crystal device is an optical switch, an optical logic element, or the like.

It is a figure which shows the mode of the splay alignment (1), (2), and the bend alignment (3) of a liquid crystal element. FIG. 7 is a diagram showing a plane and a cross section of a structure of a main part for one pixel of a conventional liquid crystal panel. FIG. 7 is a diagram schematically illustrating a conventional liquid crystal panel and a capacitive load between a gate line electrode and a counter electrode in some embodiments. FIG. 2 is a diagram illustrating a configuration for one pixel of the liquid crystal panel according to the first embodiment. It is a figure showing composition for one pixel of a liquid crystal panel of a 1-2th embodiment. FIG. 14 is a diagram illustrating a configuration for one pixel of a liquid crystal panel according to a first to third embodiments. FIG. 11 is a diagram illustrating a configuration for one pixel of a liquid crystal panel according to a first to fourth embodiments. FIG. 9 is a diagram illustrating a configuration for one pixel of a liquid crystal panel according to a first to fifth embodiments. FIG. 15 is a diagram illustrating a configuration for one pixel of a liquid crystal panel according to a first to sixth embodiments. It is sectional drawing of the liquid crystal device of 1-7th Embodiment. It is sectional drawing of the liquid crystal device of 1-8th Embodiment. It is sectional drawing of the liquid crystal device of 1-9th Embodiment. FIG. 3 is a diagram illustrating a circuit configuration of a pixel of a liquid crystal device according to Embodiment 2-1 and the like. FIG. 3 is a diagram showing the structure of a pixel in the same manner. FIG. 3 is a diagram showing dimensions of a pixel in the same manner. FIG. 3 is a diagram illustrating a state and an action of a voltage applied to or added to each unit between pixels. It is the figure which showed the mode of voltage application of 2nd Embodiment, and the effect | action. FIG. 3 is a configuration diagram of a control unit of the liquid crystal device according to the embodiment. It is a figure which shows the correlation of the duty ratio of the 1st kind of electric potential difference application step and transition completion time in 2nd Embodiment. Similarly, FIG. 9 is a diagram showing times tr and tf required for changing a potential difference Vpc between a pixel electrode and a counter electrode. FIG. 3 is a diagram illustrating a specific configuration of the circuit. It is the figure which showed the mode of voltage application and operation | movement of 2nd Embodiment. FIG. 9 is a diagram showing a modification of the embodiment. FIG. 14 is a diagram illustrating a circuit configuration of a pixel according to a second to fourth embodiments. FIG. 3 is a diagram illustrating a structure of a pixel according to the embodiment. FIG. 3 is a diagram illustrating dimensions of pixels according to the embodiment. It is a figure showing operation of a 2-4th embodiment. It is a time chart of the electrode potential of the pixel of the 2-5th Embodiment. FIG. 9 is a diagram illustrating a measurement result of a relationship between a potential difference and a transition completion time when a potential difference between a pixel electrode and a counter electrode changes. It is a time chart of the electrode potential of the pixel of the 2-6th Embodiment. It is a time chart of the electrode potential of the pixel of 2-7th Embodiment. It is a time chart of the electrode potential of the pixel of the 2-8th Embodiment. It is a time chart of the electrode potential of the pixel of 2-9th Embodiment. It is a time chart of the electrode potential of the pixel of a 2-10th embodiment. In the second to fifth embodiments, the driving period for bend alignment of the liquid crystal layer is started from the first type of potential difference applying step, and is started from the second type of potential difference applying step. It is a figure which shows the transfer completion time measured value in the case of having done. It is a time chart of the electrode potential of the pixel of the 2-11th Embodiment. It is a time chart of the embodiment 3-1. It is a figure showing composition of a circuit of the above-mentioned embodiment, etc.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 1st board | substrate 2 2nd board | substrate 3 Pixel electrode 21 Transparent pixel electrode 5 Liquid crystal layer 6 Pixel transistor 7 Source line, source line electrode 70 Source line forming metal film 71 Source line 8 Gate line, gate line electrode 81 Gate before Line 9 Counter electrode 10 Common electrode 11 Black matrix 12 Color filter 64 Channel protective film 65 a-Si layer 66 n + a-Si layer 76 Insulating film between source line electrode and liquid crystal layer 86 Insulation between gate line electrode and a-Si layer Film 87 Insulating film Vcc Common electrode potential Vc Counter electrode potential Vg Gate line potential Vs Source line potential Vp Pixel electrode potential Vpc Potential difference between pixel electrode and counter electrode Tc Normal video display period Cgd Gate line and pixel Interelectrode capacitance Cst Storage capacitance between pixel electrode and common electrode Clc Liquid crystal capacitance between pixel electrode and counter electrode Cg s Capacitance between gate line and source line 204 Liquid crystal panel controller 205 Liquid crystal panel

Claims (13)

A first substrate on which thin film transistors, pixel electrodes, and the like are formed in a matrix, a second substrate on which a counter electrode is formed, and a liquid crystal device for forming a splay-aligned liquid crystal layer between the two substrates into bend alignment In the driving method of
A high electric field application start-up step is provided between the gate line of the first substrate and the counter electrode of the second substrate to provide a higher electric field intensity than that applied to the liquid crystal layer during the normal image display period. A method for driving a liquid crystal device, comprising: A first substrate on which thin film transistors, pixel electrodes, gate lines, and the like are formed in a matrix, a second substrate on which a counter electrode is formed, and a splay-aligned liquid crystal layer between both substrates to bend alignment. In the liquid crystal device of
A liquid crystal device having a period between the gate line of the first substrate and the counter electrode of the second substrate for applying a higher electric field intensity than a voltage applied to the liquid crystal layer during a normal video display period. . The liquid crystal device according to claim 2,
The gate line of the first substrate is
A liquid crystal device characterized by being a strong electric field application type gate line having a thin insulating film in a portion where there is no other metal film or semiconductor layer between the liquid crystal layer and the liquid crystal layer. The liquid crystal device according to claim 2,
An insulating film between the gate line of the first substrate and the liquid crystal layer,
A liquid crystal device characterized by being an insulating film made of a high relative dielectric constant material using a material having a high relative dielectric constant. The liquid crystal device according to claim 2,
The gate line of the first substrate is
A liquid crystal device, characterized in that a portion having no metal film or semiconductor layer between itself and the liquid crystal layer is a predetermined-portion thick film type gate line in which the thickness of a metal to be formed is increased. The liquid crystal device according to claim 2,
The gate line of the first substrate is
In a portion where there is no other metal film or semiconductor layer between the liquid crystal layer and the liquid crystal layer, the source line forming metal is a partially contacting gate line which is electrically contacted with the gate line forming metal and laminated. Liquid crystal device. The liquid crystal device according to claim 2,
The gate line of the first substrate is
In a portion where there is no other metal film or semiconductor layer between the liquid crystal layer and the liquid crystal layer, the source line forming metal is a non-contact type gate line laminated without being in electrical contact with the gate line forming metal. Liquid crystal device. The liquid crystal device according to claim 2,
The counter electrode on the second substrate is
A liquid crystal device comprising a divided counter electrode divided into a portion facing the gate line of the first substrate and another portion. The liquid crystal device according to claim 2,
The counter electrode on the second substrate is:
The liquid crystal device according to claim 1, wherein a portion of the first substrate facing the gate line is a thick film counter electrode facing the portion, which is formed thicker than a portion not facing the gate line. The liquid crystal device according to claim 2,
On the second substrate,
A liquid crystal device comprising a color filter formed by laminating a resin on a portion of the first substrate facing the gate line. A color filter formed by laminating with resin on a portion facing the gate line,
The liquid crystal device according to claim 54, wherein the liquid crystal device is a color filter formed by laminating peripheral portions of a plurality of color filters having different colors. The liquid crystal device according to claim 2,
On the second substrate,
A liquid crystal device comprising a columnar spacer formed on a portion of the first substrate facing the gate line and facing the gate line with the liquid crystal layer interposed therebetween. The columnar spacer,
At least the liquid crystal layer side is a conductive columnar spacer,
13. The liquid crystal device according to claim 12, further comprising a columnar spacer potential applying means for applying a potential facing the gate line to the columnar spacer when the liquid crystal device is started.

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