JP2004281970A - Electrically erasable programmable logic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrically erasable programmable logic device having a small chip area and a simple structure. <P>SOLUTION: The electrically erasable programmable logic device comprises a P type semiconductor substrate, an N type well formed on the P type semiconductor substrate, a first PMOS transistor formed on the N type well and including a floating gate electrode , a first P<SP>+</SP>doping region and a P<SP>-</SP>doping region surrounding the an N<SP>+</SP>doping region being used for erasing the first PMOS transistor, and a second PMOS transistor formed on the N type well, connected in series with the first PMOS transistor through the first P<SP>+</SP>doping region being shared as the source electrode of the second PMOS transistor and including a select gate electrode and a second P<SP>+</SP>doping region. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and an operation method, and more particularly to an electrically erasable programmable logic device in single-layer polycrystalline silicon having advantages such as high density, low power consumption, high write / erase efficiency, and rewritability.
[0002]
[Prior art]
An electrically erasable programmable read only memory (EEPROM) or a flash electrically erasable programmable read only memory (Flash EEPROM) has the advantage of maintaining the contents of the memory even when the power is turned off, and allows data to be rewritten. It is effective and has a high transmission speed, so its application range is very wide. 2. Description of the Related Art In various information, communication and consumer electronics, non-volatile memory has become an indispensable device. As the demand for small mobile electronic products such as PDAs and mobile phones increases, so does the demand for embedded IC chips or system-on-chip (SOC) including EEPROM and logic circuits. . EEPROMs are always compatible with the CMOS process, and are being developed in the direction of low power consumption, high writing efficiency, low cost, and high integration density, which will meet future product requirements.
[0003]
FIG. 1 is a cross-sectional view of an EEPROM cell (10) according to the prior art. As shown in FIG. 1, a conventional EEPROM cell (10) includes an NMOS transistor (28) and a PMOS transistor (30), and the NMOS transistor (28) and the PMOS transistor (30) are insulated field oxide films (24). ). The NMOS transistor (28) is formed on a P-type substrate (12) and includes a first floating gate electrode (32), an N ⁺ source electrode doping region (14), and an N ⁺ drain electrode doping region (16). The PMOS transistor (30) is formed on the N-type ion well (18) and includes a second floating gate electrode (34), a P ⁺ source electrode doping region (20), and a P ⁺ drain electrode doping region (22). . In addition, a heavily doped N-type channel stopper (38) is buried next to the P ⁺ source electrode doping region (20), and the N-type channel stopper (38) serves as the second floating gate electrode (34). Is below. The first floating gate electrode (32) and the second floating gate electrode (34) are connected to each other via a floating gate conductor (36), and the first floating gate electrode (32) and the second floating gate electrode (34) are the same. The potential is maintained. The second floating gate electrode (34) is connected to the first floating gate electrode (32) by a floating gate conductor (36) when the first floating gate electrode (32) generates a corresponding potential according to the voltage of the control gate electrode. Therefore, the second floating gate electrode (34) also has the same potential as the first floating gate electrode (32), and further has a hot potential generated from the depletion region of the P ⁺ source electrode doping region (20) and the N-type channel stopper (38). The electrons are bound into the second floating gate electrode (34) by absorbing the electrons.
[0004]
The prior art EEPROM cell (10) has the following disadvantages. First, the conventional EEPROM cell (10) includes a PMOS transistor (30) and an NMOS transistor (28), and thus occupies a relatively large chip area. Next, the prior art EEPROM cell (10) requires another N-type channel stopper (38). And in the EEPROM cell (10) according to the prior art, the first floating gate electrode (32) and the second floating gate electrode (34) are always electrically connected by the floating gate conductor (36). Further, it is necessary to separate the NMOS transistor (28) and the PMOS transistor (30) by the field oxide film region (24). As described above, the electrically erasable programmable logic device according to the prior art has an excessively large chip area and a complicated structure, thereby increasing the production cost and difficulty.
[Problems to be solved by the invention]
An object of the present invention is to provide an electrically erasable programmable logic device having a small chip area and a simple structure.
[0005]
[Means for Solving the Problems]
The inventor of the present invention has conducted intensive studies in view of the drawbacks of the prior art, and as a result, has found that the electrically erasing including the P-type semiconductor substrate, the N-type well, the first PMOS transistor, and the second PMOS transistor can be performed. The present inventors have focused on the point that the problem can be solved by the structure of a programmable logic device, and completed the present invention based on such knowledge.
[0006]
Hereinafter, the present invention will be described specifically.
The electrically erasable programmable logic device according to claim 1, comprising a P-type semiconductor substrate, an N-type well, a first PMOS transistor, and a second PMOS transistor, wherein the N-type well comprises: The first PMOS transistor is formed on a P-type semiconductor substrate, and the first PMOS transistor is formed on the N-type well and has a floating gate electrode and a first P ⁺ doping region serving as a drain electrode of the first PMOS transistor. A P ^- doping region surrounding an N ⁺ doping region used for erasing a memory of the first PMOS transistor, wherein the second PMOS transistor is formed on the N-type well, and the second PMOS transistor is formed on the N-type well. The source electrode of the transistor, the second PMOS transistor being shared with the drain of the first PMOS transistor. Through the P ⁺ doping region, connected to the first PMOS transistor and the series, further includes a select gate electrode and a second P ⁺ doped region is a drain electrode of the second PMOS transistor.
[0007]
Electrically erasable programmable logic device as in claim 2, the first PMOS transistor of claim 1, further wherein the N ⁺ doped region and also the P ^- formed in the doped region, said N ⁺ doping Including a third P ⁺ doping region that does not overlap with the region.
[0008]
An electrically erasable programmable logic device according to claim 3, wherein the third P ⁺ doping region and the N ⁺ doping region in claim 2 are separated from each other by an insulating layer.
[0009]
5. The electrically erasable programmable logic device according to claim 4, wherein the first P ⁺ -doped region, the N ⁺ -doped region and the second P ⁺ -doped region according to claim 1 have a metal silicide. Can be covered.
[0010]
An electrically erasable programmable logic device according to claim 5, wherein the floating gate electrode obtains a low voltage due to a capacitance coupling effect under the predetermined drain electrode bias Vd according to claim 1. Since the P-type channel of the first PMOS transistor is opened, a current near the maximum value of the gate electrode is generated, and a write operation is performed.
[0011]
An electrically erasable programmable logic device according to claim 6, wherein the predetermined bias in claim 5 is about 5V.
[0012]
In the electrically erasable programmable logic device according to the seventh aspect, no control gate electrode is provided on the floating gate electrode in the first aspect.
[0013]
In the electrically erasable programmable logic device according to claim 8, the floating gate electrode in claim 1 is a single-layer polycrystalline silicon.
[0014]
10. The electrically erasable programmable logic device according to claim 9, wherein the second P ⁺ doping region according to claim 1 is electrically connected to a bit line, wherein the bit line of the electrically erasable programmable logic device is provided. Provide a signal.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
An electrically erasable programmable logic device includes an N-type well formed on a P-type semiconductor substrate, a floating gate electrode formed on the N-type well, and a drain electrode of the first PMOS transistor. and a first P ⁺ doped region which is, P surrounds the N ⁺ doped region which is used to erase the memory in the first PMOS transistor ^- a first PMOS transistor including a doped region, said N-type well A source electrode of a second PMOS transistor formed thereon, connected in series with the first PMOS transistor via the first P ⁺ doping region shared with a drain electrode of the first PMOS transistor, Furthermore the second P is a selected gate electrode, a drain electrode of the second PMOS transistor And a second PMOS transistor and a doped region.
In order to describe the structure and features of such an electrically erasable programmable logic device in detail, a specific embodiment will be described below with reference to the drawings.
[0016]
【Example】
Please refer to FIG. 2 and FIG. FIG. 2 is a plan view illustrating a portion of an electrically erasable programmable logic device (100) according to the present invention. FIG. 3 is a cross-sectional view taken along line AA ′ disclosed in the electrically erasable programmable logic device (100) of FIG. As disclosed in FIG. 2, the electrically erasable programmable logic device (100) comprises a PMOS transistor (101) and a PMOS transistor (102) connected in series to the PMOS transistor (101) via a shared doping region. And A PMOS transistor (101) and a PMOS transistor (102) are formed on the N-type well (110). The PMOS transistor (101) is a floating gate electrode transistor and includes a floating gate electrode (122), a P ⁺ doping region (132), and an N ⁺ doping region (134). N ⁺ doped region (134) is P ^- formed in the doping region (140) is used to erase the information stored in the floating gate electrode (122). The P ^- doping region 140 partially overlaps the floating gate electrode 122 and can be formed by a method such as a gradient ion implantation or a thermal drive-in technique. The floating gate electrode (122) according to the present invention is formed of single-layer polycrystalline silicon, and has no or need for a control electrode above. Other, P ^- in the doping region (140), there are ^{P +} doped region (142), also P ^- field oxide region and the ^{N +} doped region (134) formed in the doping region (140) (150) or separated by a shallow trench insulating layer. As previously mentioned, the PMOS transistor (101) and the PMOS transistor (102) share a P ⁺ doping region (132), thereby forming both transistors in series. The PMOS transistor (102) includes a select gate electrode (124), a P ⁺ doping region (132) shared with the PMOS transistor (101), and a P ⁺ doping region (136). Alternatively, one can choose to form a metal silicide layer (not shown) over the N ⁺ doping region (134) and the P ⁺ doping region (142).
[0017]
As shown in FIG. 3, the PMOS transistor (101) further includes a floating gate electrode oxide layer (122a) provided below the floating gate electrode (122). The PMOS transistor (102) further includes a gate electrode oxide layer (124a). A P ⁺ doping region (136) connects to the bit line via a contact plug formed in the dielectric layer (162), thereby providing a bit line signal to the electrically erasable programmable logic device (100). I do. Since the electrically erasable programmable logic device (100) according to the present invention is operated at low voltage, the thickness of the floating gate electrode oxide layer (122a) and the gate electrode oxide layer (124a) are in the logic circuit. It can be the same as the gate electrode oxide layer, but the thickness can be increased depending on the situation. In either case, the structure of the electrically erasable programmable logic device (100) according to the present invention is compatible with standard CMOS semiconductor processing.
[0018]
Please refer to FIG. FIG. 4 is an explanatory diagram in which the electrically erasable programmable logic device (100) according to the present invention performs a write operation. As shown in FIG. 4, when a write operation occurs, a voltage of bit line voltage (V ₁ ) = 0 is applied to the P ⁺ drain electrode doping region (136) of the PMOS transistor (102) to select the select gate electrode (124). ) Is applied with a word line voltage (V ₂ ) (for example, V ₂ = −2 V) having at least one threshold voltage lower than the bit line voltage (V ₁ ), so that P is located below the select gate electrode (124). The channel is opened, and the P ⁺ drain electrode doping region (132) and the P ⁺ drain electrode doping region (136) are brought to the same potential. That is, it is 0V. When a well voltage (V ₅ ) = 5 V is applied to the N-type well (110), the floating gate electrode (122) of the PMOS transistor (101) enters a floating state, and the N ⁺ doping region (134) and the P ⁺ source electrode doping region The erase voltage (V ₃ ) = 5 V and the source electrode line voltage (V ₄ ) = 5 V are applied to (142), respectively, so that the P ⁻ doping region (140) and the N-type well (110) have the same potential. Under the above-described conditions, the floating gate electrode (122) can obtain a low voltage (for example, 3 to 4 V) by the capacitance coupling effect. A certain P-type channel is opened, and hot electrons are generated by collision with channel holes, accelerated via an electric field in a depletion region, and exceed the floating gate electrode oxide layer (122a) to be in the floating gate electrode (122). Is captured by
[0019]
Please refer to FIG. FIG. 5 is an explanatory diagram showing the relationship between the floating gate electrode and the gate current under various bias conditions (Vd = V ₁ -V ₅ ) applied to the drain electrode of the PMOS transistor (101) and the N-type well (110). It is. As disclosed in FIG. 5, under the condition that the bias voltage (Vd) is −5 V, the floating gate electrode 122 obtains a low voltage of about −1 to −2 V due to the capacitance coupling effect. At this time, the channel of the PMOS transistor (101) has just opened, and the gate current approaches the maximum value. In other words, in the operation mode according to the present invention, since the ratio (Ig / Id) of the gate current to the drain current is relatively large, a relatively good effect can be obtained when a write operation is performed.
[0020]
Please refer to FIG. FIG. 6 is an explanatory diagram in which the electrically erasable programmable logic device (100) according to the present invention causes an erasing operation. As shown in FIG. 6, when an erasing operation is performed, a voltage of bit line voltage (V ₁ ) = 0 V is applied to the P ⁺ drain electrode doping region (136) of the PMOS transistor (102) to select the selection gate electrode (124). ) to the word line voltage _(V 2) = by adding 0V, it does not open the P-channel at the bottom of the selection gate electrode (124). When a well voltage (V ₅ ) = 0 V is applied to the N-type well (110), the floating gate electrode (122) of the PMOS transistor (101) enters a floating state, and the N ⁺ doping region (134) and the P ⁺ doping region (142) ), The erasing voltage (V ₃ ) = 5 V and the source electrode line voltage (V ₄ ) = − 3 V, respectively, bias the N ⁺ doping region (134) and the P ⁺ doping region (142) to generate a depletion region. . Under the conditions described above, electron-hole pairs are generated in the depletion region, and holes are generated in the floating gate electrode oxide layer (122a) via band-to-band tunneling. Crossing the energy barrier, it enters the floating gate electrode (122) and neutralizes the trapped electrons.
[0021]
Please refer to FIG. FIG. 7 is a diagram illustrating a read operation performed by the electrically erasable programmable logic device (100) according to the present invention. As shown in FIG. 7, when a read operation is performed, a voltage of bit line voltage (V ₁ ) = V _DD −V _X is applied to the P ⁺ drain electrode doping region (136) of the PMOS transistor (102), and V _{When X} is greater than 0 V, there is a voltage difference between the bit line and the source electrode line, and by applying the word line voltage (V2) = 0 to the select gate electrode (124), the P-channel is provided below the select gate electrode (124). Opens. A well voltage (V ₅ ) = (V _DD ) is applied to the N-type well (110), and the floating gate electrode (122) of the PMOS transistor (101) enters a floating state, and the N ⁺ doping region (134) and the P ⁺ source An erasing voltage (V ₃ ) = (V _DD ) and a source electrode line voltage (V ₄ ) = (V _DD ) are applied to the electrode doping region (142), respectively.
[0022]
The above is a preferred embodiment of the present invention, and does not limit the scope of the present invention. Therefore, any modification or alteration that can be made by those skilled in the art and that is made in the spirit of the present invention and that has an equivalent effect on the present invention shall fall within the scope of the claims of the present invention. I do.
[0023]
【The invention's effect】
Compared with the prior art, the electrically erasable programmable logic device according to the present invention can operate at a low voltage, and the unique design according to the present invention allows the PMOS transistor (101) to operate when the channel is just opened. , The gate current (Ig) already approaches the maximum value. Under the operation mode according to the present invention, the ratio of the gate current to the drain current (Ig / Id) is relatively large, so that it has the advantages of power saving and energy saving, and obtains a relatively good effect when a write operation is performed. Saves time for write operations. In addition, the erase operation is performed with the inter-band transition tunneling holes efficiently in the memory using the erase N ⁺ doping region (134). Further, since the present invention connects both the PMOS transistors in series, the use area of the chip can be greatly reduced and the operation can be performed in a high density memory area. In addition, since the structure according to the present invention is simple and compatible with the conventional CMOS logic process, the manufacturing cost is reduced, and it is suitable for application in the area of system-on-a-chip (SOC).
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a conventional EEPROM cell.
FIG. 2 is a plan view illustrating a portion of an electrically erasable programmable logic device according to the present invention.
3 is a cross-sectional view of the electrically erasable programmable logic device disclosed in FIG. 2, taken along the line AA.
FIG. 4 is an explanatory diagram in which an electrically erasable programmable logic device according to the present invention causes a write operation.
FIG. 5 is an explanatory diagram showing a relationship between a floating gate voltage and a gate current under various bias conditions (Vd = V ₁ -V ₅ ) applied to a drain electrode and an N-type well of a PMOS transistor.
FIG. 6 is an explanatory diagram in which an electrically erasable programmable logic device according to the present invention causes an erasing operation.
FIG. 7 is a diagram illustrating a read operation performed by the electrically erasable programmable logic device according to the present invention.
[Explanation of symbols]
10 EEPROM cell 12 P-type substrate 14 N ⁺ source electrode doping region 16 N ⁺ drain electrode doping region 18 N-type ion well 20 P ⁺ source electrode doping region 22 P ⁺ drain electrode doping region 24 field oxide film region 28 NMOS transistor 30 101, 102 PMOS transistor 32 First floating gate electrode 34 Second floating gate electrode 36 Floating gate conductor 38 N-type channel stopper 100 Electrically erasable programmable logic device 110 N-type well 122 Floating gate electrode 122a Floating gate electrode oxide layer 124 selection gate electrode 124a gate electrode oxide layers 132, 136, 142 P ⁺ doping region 134, 144N ⁺ doping region 1 40 P ^- doping region 150 oxide layer region 162 dielectric layer V ₁ bit voltage V ₂ word voltage V ₃ erase voltage V ₄ source electrode line voltage V ₅ well voltage

Claims (9)

An electrically erasable programmable logic device comprising a P-type semiconductor substrate, an N-type well, a first PMOS transistor, and a second PMOS transistor.
The N-type well is formed on the P-type semiconductor substrate;
The first PMOS transistor is formed on the N-type well, and erases a floating gate electrode, a first P ⁺ doping region serving as a drain electrode of the first PMOS transistor, and erases a memory of the first PMOS transistor. And a P ^- doping region surrounding the N ⁺ doping region,
The second PMOS transistor is formed on the N-type well, serves as a source electrode of the second PMOS transistor, and via the first P ⁺ doping region shared with a drain of the first PMOS transistor. An electrically erasable programmable logic connected in series with the first PMOS transistor and further including a select gate electrode and a second P ⁺ doping region serving as a drain electrode of the second PMOS transistor. device. The first PMOS transistor further the N ⁺ doped region and also the P ^- formed in the doped region, claim 1, characterized in that it comprises a third P ⁺ doped region which does not overlap with the N ⁺ doped region 3. The electrically erasable programmable logic device according to claim 1. The electrically erasable programmable logic device of claim 2, wherein the third P ⁺ doping region and the N ⁺ doping region are separated from each other by an insulating layer. The electrically erasable device according to claim 1, wherein a metal silicide can be overlaid on the first P ⁺ doping region, the N ⁺ doping region, and the second P ⁺ doping region. Programmable logic device. Under the predetermined drain electrode bias Vd, the floating gate electrode can obtain a low voltage due to the capacitance coupling effect, and the P-type channel of the first PMOS transistor opens, so that the gate close to the maximum value can be obtained. 2. The electrically erasable programmable logic device according to claim 1, wherein a current is applied to the electrode to cause a write operation. The electrically erasable programmable logic device of claim 5, wherein said predetermined bias is about 5V. The electrically erasable programmable logic device according to claim 1, wherein a control gate electrode is not provided on the floating gate electrode. 2. The electrically erasable programmable logic device according to claim 1, wherein the floating gate electrode is a single-layer polycrystalline silicon. The electrically erasable of claim 1, wherein the second P ⁺ doping region is electrically connected to a bit line to provide a bit line signal of the electrically erasable programmable logic device. Programmable logic device.

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