JP2004274578A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus capable of being compatible with requirements of downsizing, the increased number of pixels, and low power consumption. <P>SOLUTION: The solid-state imaging apparatus is provided with: a board; photodiodes PD formed on the board in a way of forming rows and columns at a prescribed arrangement interval wherein adjacent rows and adjacent columns are laid out while being relatively deviated; control circuits (Ta, Tb, Tc, and TL) for detecting signal electric charges stored in the photodiodes PD and transmitting an image signal resulting from amplifying the signal electric charges; signal lines VL provided to each of rows or columns comprising the photodiodes PD, and converters ADC provided corresponding respectively to the signal lines VL and converting the image signal. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a solid-state imaging device.
[0002]
[Prior art]
Semiconductor image sensors such as MOS image sensors and CCD image sensors are used in imaging devices such as mobile phones with cameras, digital cameras, facsimiles, and scanners. MOS image sensors are frequently used in mobile phones and the like because they are superior in that they consume less power and can be made smaller than CCD image sensors.
[0003]
FIG. 8 is a circuit diagram of a conventional amplification type CMOS image sensor. The imaging region C (hereinafter, also referred to as a pixel) includes four transistors Ta, Tb, Tc, and Td and a photodiode PD. These transistors Ta, Tb, Tc and Td are controlled by a pulse selector.
[0004]
The imaging region C is formed in a matrix on a semiconductor substrate (not shown). A vertical signal line VL is provided for each column of the imaging region C. An imaging region C in a certain column is connected to a vertical signal line VL along the column. The vertical signal lines VL are respectively connected to AD converters provided for each column of the imaging region C.
[0005]
The photodiode PD converts the received light into a signal charge. The signal charge is sent to the detection node DN via the transistor Td. Thereby, the gate voltage of the transistor Tb changes. The transistor Tb and the transistor TL form a source follower circuit, and transmit a change in the gate voltage of the transistor Tb to the vertical signal line VL. The vertical signal line VL carries this voltage signal (hereinafter, referred to as an image signal) to an AD converter. The AD converter converts the image signal into a digital value and sends the digital value to the horizontal shift register at a predetermined timing.
[0006]
Thus, the amplification type CMOS image sensor can transfer the light received by the photodiode PD as an image signal.
[0007]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2002-164527 [Patent Document 2]
JP-A-9-98349 [Patent Document 3]
JP-A-10-136391
[Problems to be solved by the invention]
Image sensors are required to be further miniaturized and have more pixels. However, when the area of the photodiode PD is reduced, its sensitivity is reduced. Further, when the number of the photodiodes PD is increased to increase the number of the vertical signal lines, there is a problem that the power consumption of the image sensor increases.
[0009]
Therefore, an object of the present invention is to provide a solid-state imaging device that can meet demands for miniaturization, increase in pixels, and low power consumption.
[0010]
[Means for Solving the Problems]
The solid-state imaging device according to the embodiment of the present invention is formed on the substrate so as to form rows and columns at a predetermined arrangement interval, and is arranged relatively offset in adjacent rows and columns. A photodiode, a control circuit for amplifying signal charges accumulated in the photodiode and sending the amplified image as an image signal, and a control circuit provided for each row or column composed of the photodiode, for carrying the image signal from the control circuit. A signal line; and a converter provided to correspond to each of the signal lines and converting the image signal.
[0011]
A solid-state imaging device according to another embodiment according to the present invention is formed on the substrate so as to form rows and columns at predetermined arrangement intervals, and is relatively shifted in adjacent rows and columns. A photodiode disposed, a control circuit for transmitting an image signal based on signal charges accumulated in the photodiode, and a control circuit provided for each of a plurality of rows or a plurality of columns of the photodiode, A signal line that carries the image signal from a circuit; and a converter that is provided corresponding to each of the signal lines and converts the image signal.
[0012]
Preferably, the control circuit detects the signal charge and sends an image signal obtained by amplifying the signal charge.
[0013]
Preferably, the control circuit includes a source follower circuit.
[0014]
Preferably, the solid-state imaging device further includes an interpolation processing circuit that interpolates an image signal in an area where the photodiode is not provided with an image signal from the photodiode provided in the vicinity of the area.
[0015]
Preferably, one control circuit is provided for each of the plurality of photodiodes.
[0016]
Preferably, rows or columns of the photodiodes adjacent to each other are relatively displaced by about の of the arrangement interval.
[0017]
Preferably, the converter and the signal line are provided every two rows or every two columns of the photodiode.
[0018]
Preferably, the control circuit is a switching element, and the signal charge is used as a substrate bias of the switching element, and modulates a threshold of the switching element.
[0019]
Preferably, the control circuit and the signal line transfer the signal charge as the image signal.
[0020]
Preferably, the vertical signal line is formed along the photodiode, and is bent in parentheses for each row of the photodiode.
[0021]
Preferably, the vertical signal line has a shape in which S-shapes are continuously connected.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. These embodiments do not limit the present invention.
[0023]
In the CMOS image sensor according to the embodiment of the present invention, the photodiodes are arranged relatively shifted in rows and columns, and an interpolation processing circuit interpolates between pixels with signals of peripheral pixels. This makes it possible to increase the apparent number of pixels while reducing the power consumption of the image sensor. Further, by providing a vertical signal line for each of a plurality of columns of photodiodes, the number of AD converters can be reduced. Thus, the power consumption of the image sensor can be reduced, and the size of the image sensor can be reduced.
[0024]
(First Embodiment)
FIG. 1 is a circuit diagram of an amplification type CMOS image sensor 100 (hereinafter, also referred to as sensor 100) according to a first embodiment of the present invention. The sensor 100 includes photodiodes PD formed on a semiconductor substrate so as to form rows and columns at a certain arrangement interval. The photodiodes PD are arranged in a zigzag manner so as to be relatively displaced by の pitch of the arrangement interval of the photodiodes PD in adjacent rows and columns. Hereinafter, the row and column of the photodiode PD are simply referred to as “row” and “column”, respectively.
[0025]
One imaging region C, that is, one pixel includes a photodiode PD and transistors Ta, Tb, Tc, and Td. The power supply VDD is connected via transistors Ta and Tb to a vertical signal line VL provided for each column. The gate of the transistor Tb is connected to the phototransistor PD via the transistor Td. The power supply VDD is connected to the detection node DN between the gate of the transistor Tb and the transistor Td via the transistor Tc. The gate of the transistor Ta, the gate of Tc, and the gate of Td are connected to an address line (ΦADRES), a reset line (ΦRESET), and a lead line (ΦREAD), respectively. Therefore, the transistor Ta is a row selection transistor, the transistor Tc is a reset transistor, and the transistor Td is a read transistor.
[0026]
A transistor Tb in a certain column is connected to a vertical signal line VL provided along the column. An AD converter ADC is provided for each of the vertical signal lines VL. The AD converter ADC is connected to and controlled by a timing generation circuit and a horizontal shift register. The output of the AD converter ADC is connected to an interpolation processing circuit. Each of the AD converters ADC has a comparator CMP, a latch circuit LAT, and a switching circuit SW. Note that the imaging area C and the AD converter ADC are indicated by broken lines in FIG.
[0027]
The address line (ΦADRES), the reset line (ΦRESET), and the lead line (ΦREAD) are connected to a pulse selector. This pulse selector is connected to the timing generation circuit and the vertical shift registers VR1 and VR2, and selects a signal to be transmitted to the imaging region C. The pulse selector selects any one of the imaging regions C and transmits a signal.
[0028]
Further, a transistor TL is provided between each vertical signal line VL and the ground GND. The bias generation circuit is connected to the gate of the transistor TL so as to control the transistor TL. The transistor TL and the transistor Tb form a so-called source follower circuit. This source follower circuit allows a constant current to flow from the power supply VDD to the ground GND. The transistor Tb is used for amplifying signal charges, and the transistor TL is used as a load for flowing a constant current from the power supply VDD to the ground GND.
[0029]
The number of elements such as the imaging region C, the vertical signal line VL, and the AD converter ADC shown in FIG. 1 is not particularly limited.
[0030]
The operation of the sensor 100 will be described. For example, when the sensor 100 is operated in the VGA system of 30 Hz, a signal ΦVR of 30 Hz, a signal ΦES of 30 Hz, a signal ΦHP of 15.7 KHz, and a signal ΦCK of 24 MHz are input to the sensor 100.
[0031]
The timing generation circuit inputs the input signals ESR and VCK to the vertical shift register VR1, and inputs the input signals VRRS and VCK to the vertical shift register VR2. When reading out the signal charges stored in the photodiode PD, the vertical shift register VR2 starts operating in response to the signal VRRS, and sequentially selects one of the rows in the image area C in accordance with the input signal VCK. Similarly, the vertical shift register VR1 starts operating in response to the input signal ESRS, and sequentially selects any row in the image area C using the input signal VCK.
[0032]
The signal charges in the selected row are amplified by the transistor Tb and transmitted to the AD converter ADC as an image signal. The comparator CMP in the AD converter ADC removes noise from the image signal during a certain horizontal scanning period, compares the noise with the RAMP waveform from the timing generation circuit, and converts it into a digital signal (for example, a 10-bit digital signal). . The latch circuit LATCH temporarily stores a digital signal. In the next horizontal scanning period, the horizontal shift register sequentially operates the switches SW and outputs the digital signal in the latch circuit LATCH to the interpolation processing circuit. Here, the horizontal scanning period refers to a period in which the horizontal shift register sequentially operates all the switches SW one by one.
[0033]
The operation in the imaging region C will be described.
Upon receiving light, the photodiode PD performs photoelectric conversion and accumulates signal charges. To read this signal charge, first, the address signal ΦADRES is transmitted to the row containing the photodiode PD. Thereby, the transistor Ta in that row is turned on.
[0034]
Next, the source follower circuit including the amplifying transistor Tb and the load transistor TL is operated. As a result, a constant current flows from the power supply VDD to the ground GND.
[0035]
Next, a reset signal ΦRESET is supplied to the transistor Tc via the reset line to turn on the transistor Tc. As a result, the voltage of the detection node DN becomes the voltage of the power supply VDD. The voltage of the power supply VDD is used as a reference voltage.
[0036]
After turning off the transistor Tc, a read signal ΦREAD is supplied to the transistor Td via a lead line, and the transistor Td is turned on. As a result, the signal charges stored in the photodiode PD are read out to the detection node DN.
[0037]
By reading the signal charge to the detection node DN, the gate voltage of the transistor Tb changes from the reference voltage. At this time, a voltage change equivalent to a change in the gate voltage of the transistor Tb occurs on the vertical signal line VL, and this voltage change propagates to the AD converter ADC. At the source of the transistor Tb, a signal current is generated by amplifying the signal current (signal charge) of the gate. That is, the transistor Tb performs a source follower operation.
[0038]
The interpolation process will be described.
FIG. 2A is a diagram schematically illustrating the arrangement of the imaging region C in the sensor 100. FIG. FIG. 2B is a diagram schematically illustrating an arrangement of an imaging region C in a conventional image sensor. 2A and 2B, the density of the imaging region C in the present embodiment is １ ／ of that of the related art. These broken frames indicate unit areas.
[0039]
FIG. 2C is a diagram schematically illustrating the pixel after the interpolation processing by the interpolation processing circuit in the sensor 100. The interpolation processing circuit interpolates an image signal in a region where the imaging region C is not provided with an image signal from the imaging region C provided near the region. For example, the interpolation processing circuit, from the imaging area C ₁ with the signal of the C _4, generates a signal P ₁ to the imaging area C is not provided. Signal P ₁ can be a mean of the digital values of the _{C 4} from the imaging area _{C 1.} Likewise, the interpolation processing circuit, from the imaging area C ₃ using signals C _6, to generate a signal P ₂ by the imaging region C is not provided. Signal P ₂ may be the average of the imaging area _{C 3} of the digital values of _{C 6.} In this way, the interpolation processing circuit can interpolate the image signal in the area where the imaging area C is not provided.
[0040]
The sensor 100 according to the present embodiment can obtain the same resolution as the conventional sensor, although the number of the imaging regions C is half. For example, a sampling point of 340,000 pixels corresponding to VGA can be obtained with the number of pixels of 170,000 pixels.
[0041]
Further, in the present embodiment, since the density of the imaging region C is lower than that of a conventional sensor, the number of vertical signal lines is reduced. Therefore, according to the present embodiment, power consumption is lower than that of a conventional image sensor.
[0042]
FIG. 3A is a layout diagram of the microlenses in the present embodiment. FIG. 3B is a layout diagram of a microlens in a conventional example. The microlenses in the conventional example have a square arrangement. The microlenses in the present embodiment have an inclined arrangement inclined by about 45 degrees with respect to the horizontal shift register or the vertical shift register in order to match the zigzag arrangement of the photodiodes.
[0043]
The conventional arrangement interval (so-called pixel pitch) is P (for example, P = 3.8 μm), which is the same as the arrangement interval of the present embodiment. However, the length of one side of the pixel in the present embodiment is ^21/2 times that of the conventional example. For example, when P = 3.8 μm, the length of one side of the pixel in the conventional example is 3.8 μm, but the length of one side of the pixel in the present embodiment is P * 2 ^1/2 = 5. 4 μm. Therefore, the pixel area of the present embodiment is twice as large as that of the conventional example, and the sensitivity is also doubled. Since the pixel area is larger than before, the signal charges are less likely to be saturated, and the dynamic range can be increased. Furthermore, when the image sensor 100 according to the present embodiment is used in a digital camera, a relatively inexpensive optical lens can be applied since the pixel area is larger than in the related art. Further, in the present embodiment, since the pixels are arranged obliquely, the pixels overlap in the horizontal and vertical directions, and as a result, moire can be reduced.
[0044]
On the other hand, when the pixel area of the present embodiment is the same as that of the conventional example (not shown), in order to obtain the same resolution, the pixel density of the present embodiment is の of that of the conventional example. Is enough. This is because the interpolation processing circuit performs interpolation between pixels. As a result, the capacity of the image becomes half that of the conventional example. When the image sensor 100 according to the present embodiment is used in a digital camera, the number of pixels can be relatively small, so that the optical lens is downsized and the price is low. Further, since the depth of focus of the optical lens may be small, the thickness of the camera module is reduced. Further, since the number of pixels is relatively small, the area of the image sensor 100 is relatively small, and the manufacturing cost is reduced.
[0045]
FIG. 4 is a circuit diagram of an amplification type CMOS image sensor 200 (hereinafter, also referred to as sensor 200) according to a second embodiment of the present invention. The sensor 200 of the present embodiment is different from the first embodiment in that a vertical signal line VL and an AD converter ADC are provided for each of a plurality of columns of the imaging region C. In the sensor 200, the imaging regions C in two columns share one vertical signal line VL and one AD converter ADC.
[0046]
In the present embodiment, the same effect as in the first embodiment can be obtained.
[0047]
Further, according to the present embodiment, the number of circuits of the AD converter ADC can be reduced to half of that of the conventional example and the first embodiment. Thereby, the power consumption and the area of the AD converter ADC are reduced to about 1/2.
[0048]
According to the present embodiment, the number of vertical signal lines VL and the number of transistors TL are 比較 of those of the conventional example and the first embodiment. As a result, the constant current flowing through the source follower circuit becomes about 1/2. Therefore, the power consumption of the source follower circuit is reduced to about 1/2.
[0049]
FIG. 5 is a circuit diagram of an amplification type CMOS image sensor 300 (hereinafter, also referred to as sensor 300) according to a third embodiment of the present invention. This embodiment is different from the second embodiment in that transistors Ta, Tb and Tc are provided for each of the plurality of photodiodes PD. In this embodiment, the photodiode PD in a row where the transistors Ta, Tb and Tc are not provided uses the transistors Ta, Tb and Tc provided in a row adjacent thereto. That is, the photodiodes PD of two adjacent rows share one control circuit.
[0050]
More specifically, only the transistor Td is provided in the imaging region Cb of a certain row, and the transistors Ta, Tb, and Tc are not provided. On the other hand, transistors Ta, Tb, Tc, and Td are provided in an imaging area Ca included in a row adjacent to the row including the imaging area Cb. One end of the transistor Td in the imaging region Cb is connected to a detection node DN in the imaging region Ca.
[0051]
The pair of imaging areas Ca and Cb commonly use the address signal ΦADRES and the reset signal ΦRESET. When selectively reading out the signal charges of either the pair of imaging regions Ca or Cb, the pulse selector may transmit the read signal ΦREAD to the lead connected to the selected imaging region.
[0052]
In the present embodiment, the same effects as in the second embodiment can be obtained.
[0053]
Further, according to the present embodiment, the number of wirings for reading from the pulse selector is smaller than that of the conventional example and other embodiments. Therefore, in this embodiment, the layout in circuit design is easier than in the conventional example and other embodiments.
[0054]
In the second and third embodiments, similarly to the first embodiment, the microlens shown in FIG. 3A can be used.
[0055]
FIG. 6 is an enlarged plan view of the second embodiment shown in FIG. The distance between the photodiodes shown in FIG. 4 looks wider than that shown in FIG. 6, but is actually designed at the distance shown in FIG.
[0056]
A read transistor Td having a read wiring READ as a gate is provided between the photodiode PD and the detection node DN. A reset transistor Tc having the reset wiring RESET as a gate is provided between the detection node DN and the power supply VDD.
[0057]
The detection node DN is connected to the gate electrode of the amplification transistor Tb by an aluminum wiring or the like. The transistor Tb is connected to the power supply VDD via the row selection transistor Ta.
[0058]
The vertical signal line VL is formed so as to be bent along the photodiode PD for each row of the photodiode PD. More specifically, the vertical signal line VL has a shape in which S-shaped characters are continuously connected every two rows, and is formed in a zigzag wiring. As a result, the number of AD converter ADCs is reduced to half that of the conventional ADC, and the power consumption is reduced.
[0059]
FIG. 7 is an enlarged plan view of the third embodiment shown in FIG. Photodiodes PD are arranged in zigzag. Although the spacing between the photodiodes shown in FIG. 7 appears to be narrower than that shown in FIG. 5, it is actually designed with the spacing shown in FIG. Thereby, the device according to the present embodiment is downsized.
[0060]
This embodiment includes transistors Ta, Tb, Tc, and Td as in the embodiment shown in FIG. However, the transistors Ta, Tb, and Td are not provided in the imaging region C of one of the two adjacent rows, and only the read transistor Tc is provided.
[0061]
As in the embodiment shown in FIG. 6, the vertical signal line VL has a shape in which S-shaped characters are continuously connected every two rows, and is formed in a zigzag wiring. As a result, the number of AD converter ADCs is reduced to half that of the conventional ADC, and the power consumption is reduced.
[0062]
Further, according to the present embodiment, by arranging photodiodes PD in an L-shape, the area of the photodiodes can be increased. Thereby, the saturation charge amount of the photodiode PD can be increased.
[0063]
According to this embodiment, the number of wirings is smaller than that of the embodiment shown in FIG. Therefore, this embodiment can be manufactured relatively easily and is excellent in miniaturization.
[0064]
Although all of the above embodiments relate to a source follower type CMOS image sensor, the present invention is not limited to these, and can be applied to other solid-state imaging devices. For example, the present invention can be applied to a threshold modulation type CMOS image sensor using the charge accumulated in a photodiode as a substrate bias of a transistor. Further, the present invention can be applied to a CCD sensor.
[0065]
【The invention's effect】
The solid-state imaging device according to the present invention can respond to demands for miniaturization, increase in pixels, and low power consumption.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a sensor 100 according to a first embodiment of the present invention.
FIG. 2 is a diagram schematically illustrating an arrangement of an imaging region C and a diagram schematically illustrating pixels after an interpolation process.
FIG. 3 is a layout diagram of a micro lens.
FIG. 4 is a circuit diagram of a sensor 200 according to a second embodiment of the present invention.
FIG. 5 is a circuit diagram of a sensor 300 according to a third embodiment of the present invention.
FIG. 6 is an enlarged plan view of the second embodiment.
FIG. 7 is an enlarged plan view of the third embodiment.
FIG. 8 is a circuit diagram of a conventional image sensor.
[Explanation of symbols]
100, 200, 300 Image sensor PD Photodiodes Ta, Tb, Tc, Td and TL Transistor C Imaging region VDD Power supply VL Vertical signal line DN Detection node ADRES Address line RESET Reset line READ Lead line ADC AD converter CMP Comparator LAT Latch circuit SW Switching circuit VR1, VR2 Vertical shift register ΦADRES Address pulse signal ΦRESET Reset pulse signal ΦREAD Read pulse signal

Claims (12)

Board and
A photodiode formed on the substrate so as to form a row and a column at a predetermined arrangement interval, and being relatively displaced in a row and a column adjacent to each other;
A control circuit that amplifies the signal charge accumulated in the photodiode and sends the image charge as an image signal;
A signal line that is provided for each row or column that includes the photodiode and that carries the image signal from the control circuit;
A solid-state imaging device, comprising: a converter provided for each of the signal lines to convert the image signal. Board and
A photodiode formed on the substrate so as to form a row and a column at a predetermined arrangement interval, and being relatively displaced in a row and a column adjacent to each other;
A control circuit for sending an image signal based on the signal charges stored in the photodiode,
A signal line that is provided for each of a plurality of rows or a plurality of columns of the photodiodes and carries the image signal from the control circuit,
A solid-state imaging device, comprising: a converter provided for each of the signal lines to convert the image signal. The solid-state imaging device according to claim 2, wherein the control circuit detects the signal charge and sends an image signal obtained by amplifying the signal charge. The solid-state imaging device according to claim 1, wherein the control circuit includes a source follower circuit. 2. The image processing apparatus according to claim 1, further comprising an interpolation processing circuit for interpolating an image signal in an area where the photodiode is not provided with an image signal from the photodiode provided in the vicinity of the area. Item 3. The solid-state imaging device according to Item 2. The solid-state imaging device according to claim 1, wherein the control circuit is provided one for each of a plurality of photodiodes. The solid-state imaging device according to claim 1, wherein rows or columns of the photodiodes adjacent to each other are relatively shifted by about 約 of the arrangement interval. The solid-state imaging device according to claim 1, wherein the converter and the signal line are provided for every two rows or every two columns of the photodiode. The control circuit is a switching element,
The solid-state imaging device according to claim 1, wherein the signal charge is used as a substrate bias of the switching element, and modulates a threshold value of the switching element. The solid-state imaging device according to claim 2, wherein the control circuit and the signal line transfer the signal charge as the image signal. The solid-state imaging device according to claim 1, wherein the vertical signal line is formed along the photodiode, and is bent in a bracket shape for each row of the photodiode. 12. The solid-state imaging device according to claim 11, wherein the vertical signal line has a shape in which S-shapes are continuously connected.

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