JP2004253780A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, when a film having no hygroscopic block resistance exists on an interlayer film having an Si-H coupling or Cu wiring, the capacitance between the wiring or the resistances of via holes are raised by moisture absorption. <P>SOLUTION: In a semiconductor device, a silicon carbonitride film is formed on an insulating film having an Si-H coupling and Cu wiring. This silicon carbonitride film prevents deterioration of its underlying insulating film and Cu film caused by moisture absorption by playing the role of a hygroscopic block. Particularly, the effect becomes extremely high when the nitrogen concentration in the silicon carbonitride film is ≥10 atm% and <35 atm%. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and more particularly to a semiconductor device having a highly reliable wiring structure using a low dielectric constant interlayer insulating film and a low dielectric constant barrier insulating film, and a method for manufacturing the same.

  In recent years, demands for high-speed LSI signal processing have been increasing year by year. The signal processing speed of the LSI is mainly determined by the operation speed of the transistor itself and the magnitude of the signal propagation delay time in the wiring. Conventionally, the operating speed of a transistor, which has had a great influence, has been improved by reducing the size of the transistor. However, in an LSI having a design rule smaller than 0.25 μm, the influence of the latter wiring on the signal propagation delay has begun to appear significantly. In particular, the effect is great in an LSI device having a multilayer wiring layer.

  Therefore, as a method of improving the signal propagation delay of the wiring, the aluminum wiring which has been conventionally used has been replaced with a copper wiring. In addition, studies are being made to replace a conventionally used silicon oxide film with a low dielectric constant interlayer insulating film. Among the low dielectric constant films, one of the films capable of realizing a relative dielectric constant of 3.0 or less has been mass-produced for aluminum wiring, and mass production of Cu wiring has been studied. Among them, L-Ox (ladder oxide, trade name: Ladder Oxide), which is a ladder-type hydrogenated polysiloxane, has a Si-H bond in a part of a Si-O skeleton and is made of an inorganic material. It has better adhesion to wiring metal than organic materials, and since it is a ladder type, it has excellent resistance to plasma ashing and organic stripping liquid after processing, and does not form a deteriorated layer such as a moisture absorbing layer on the processed surface.

  On the other hand, a barrier insulating film which functions as a stopper film for Cu diffusion prevention and etching for the Cu damascene process is also required to have a low dielectric constant, which is lower than that of a conventional silicon nitride film having a relative dielectric constant of about 7.0. Consideration has been given to replacement with a silicon carbide film (hereinafter, referred to as a SiC film) based dielectric film having a dielectric constant of 5.0 or less. As an example, an example in which a film is formed by plasma CVD using trimethylsilane and an inert gas has been reported. In particular, if the reliability of the miniaturized Cu / Low-k (low dielectric constant interlayer insulating film) structure can be guaranteed, mass production is realized only after the combination of the low dielectric constant interlayer insulating film and the barrier insulating film can be optimized. it can.

Next, an example of the structure of a conventional semiconductor device using a low dielectric constant interlayer insulating film and a barrier insulating film will be described with reference to the drawings. As shown in FIG. 14, a zero barrier insulating film 502 functioning as a Cu diffusion prevention and etching stopper film is formed on a lower insulating film 501, and a first low dielectric constant film 503 is formed thereon. Is formed. Further, a first SiO ₂ film 504 is formed thereon. A wiring groove is formed in the interlayer insulating film in which the zero barrier insulating film 502, the first low dielectric constant film 503, and the first SiO ₂ film 504 are laminated, and the wiring groove is formed in the interlayer insulating film. A first barrier metal film 505 is formed. A first Cu wiring is buried inside the first Cu film 506. A first barrier insulating film 507 is formed on the Cu wiring, and a second low dielectric constant film 508 and a second SiO ₂ film 509 are similarly formed thereon.

A via groove is formed in the interlayer insulating film formed by laminating the first barrier insulating film 507, the second low dielectric constant film 508, and the second SiO ₂ film 509. Similarly to the above-mentioned Cu wiring, a second barrier metal film 510 is formed, and a second Cu film 511 is buried therein. Further, a second barrier insulating film 512 is formed on the via, and a third low dielectric constant film 513 and a third SiO ₂ film 514 are similarly formed thereon. Similarly, a third barrier metal film 515 is provided in a wiring interlayer insulating film formed by laminating the second barrier insulating film 512, a third low dielectric constant film 513, and a third SiO ₂ film 514, and a third barrier metal film 515 is provided inside the third barrier metal film 515. The third Cu film 516 is buried to form a second Cu wiring. A third barrier insulating film 517 is formed on the second Cu wiring. This structure is further repeated as necessary, and on the uppermost layer wiring (corresponding to the second Cu trench wiring in this embodiment) and the uppermost layer L-Ox film (corresponding to the third low dielectric constant film in this embodiment). A barrier insulating film is formed. An aluminum bonding pad 520 (having upper and lower TiN layers 519 and 521) formed in the SiO ₂ film 518 is connected to the uppermost wiring through an opening provided in the barrier insulating film. Except for a part of 520, it is covered with a cover film 523 (SiON film or SiN film) having a moisture absorption blocking property via the SiO ₂ film 522 to form a multilayer wiring structure.

Next, a method for manufacturing the above-described conventional semiconductor device will be described with reference to FIGS. First, a 0-th barrier insulating film 602 having a thickness of 50 nm to 100 nm was formed over a lower insulating film 601 formed over a semiconductor substrate including a transistor by a plasma CVD method. Subsequently, the first low-dielectric-constant film 603 was applied and fired to form a film having a thickness of 150 nm to 350 nm. A first SiO ₂ film 604 was formed thereon by a plasma CVD method of 50 nm to 200 nm (FIG. 15A).

An ARC film 605 as an anti-reflection film was applied on the structure using a photolithography technique having a minimum dimension of 0.14 μm, and then a patterned photoresist mask 606 was formed (FIG. 15B). Using this as a mask, the ARC film 605, the first SiO ₂ film 604, and the first low dielectric constant film 603 were etched with a gas containing a fluorocarbon-based gas, and stopped on the 0th barrier insulating film 602. .

  Then, after removing the photoresist mask by oxygen plasma ashing, the residue and the like were completely removed with an organic stripping solution of a weak amine or the like. After that, the 0th barrier insulating film 602 was removed by overall etch back. Further, the residue was removed by washing with an organic stripper. As a result, a groove pattern for the first wiring was formed (FIG. 15C).

  Next, after performing degassing and RF etching with Ar ions using a sputtering apparatus, a first barrier metal film 607 was formed to about 30 nm, and a Cu seed film (not shown) was formed to about 100 nm without breaking vacuum. . Next, a Cu plating film 609 was formed to a thickness of about 600 nm by Cu plating. Thereafter, baking was performed at 200 to 400 ° C. by vertical furnace annealing (FIG. 16A).

Next, using a metal CMP technique, the metal other than the groove was removed to form a first Cu groove wiring 609 (FIG. 16B). Next, a first to 100 nm thick barrier insulating film 610 was formed by a plasma CVD apparatus. Subsequently, a second low dielectric constant film 611 and a second SiO ₂ film 612 were sequentially formed. A second photoresist mask 614 was formed on the second ARC film 613 as a via pattern using a photolithography technique for forming the first via (FIG. 16C).

Using this as a mask, the second ARC film 613, the second SiO ₂ film 612, and the second low dielectric constant film 611 are etched, and the etch stop is performed on the first barrier insulating film 610, and the first via A groove was opened. Then, after removing the photoresist mask by oxygen plasma ashing, the residue and the like were completely removed with an amine-based organic stripping solution or the like.

  After that, the first barrier insulating film 610 at the bottom of the first via groove was removed, and the entire surface was etched back in order to establish electrical conduction with the first Cu groove wiring. Further, the residue was removed by washing with an organic stripping solution to form a first via groove pattern. Subsequently, after performing degassing with a sputtering apparatus, performing RF etching with Ar ions, a second barrier metal film 615 is formed to about 30 nm, and a Cu seed film (not shown) is formed without breaking vacuum. 100 nm was formed. Next, about 300 nm of a copper film 617 was formed by Cu plating. Thereafter, firing was performed at 200 to 400 ° C. by vertical furnace annealing. Next, using a metal CMP technique, a metal other than the via portion was removed to form a via 617 (FIG. 17A).

Next, a second barrier insulating film 618 having a thickness of 50 to 100 nm was formed by a plasma CVD apparatus. Subsequently, a third low dielectric constant film 619 and a third SiO ₂ film 620 were sequentially formed (FIG. 17B).

  After applying the third ARC film 621, a patterned third photoresist mask 622 was formed on this structure using a photolithography technique of a minimum L / S = 0.14 / 0.14 μm level (FIG. 18 (a)).

Using this as a mask, the third ARC film 621, the third SiO ₂ film 620, and the third low dielectric constant film 619 are etched with an etching gas containing a fluorocarbon-based gas, and And the groove pattern for the second wiring was opened. Then, after removing the photoresist mask by oxygen plasma ashing, the residue and the like were completely removed with an amine-based organic stripping solution or the like.

  After that, the second barrier insulating film 618 at the bottom of the second wiring groove was removed by etch back on the entire surface. Further, the residue was removed by washing with an organic stripper. As a result, a second trench wiring pattern was formed. Next, after performing a degassing process using a sputtering apparatus and performing an RF etch using Ar ions in the same manner as the first wiring, a third barrier metal film 623 is formed to a thickness of about 30 nm. 100 nm was formed. Next, a Cu film 624 was formed to a thickness of about 600 nm by Cu plating. Thereafter, firing was performed at 200 to 400 ° C. by vertical furnace annealing. Thereafter, metal CMP is performed to form a second Cu trench wiring, and a third barrier insulating film 625 is formed on the second Cu trench wiring (FIG. 18B).

Thereafter, an SiO ₂ interlayer insulating film having a thickness of 300 to 500 nm is formed on the third barrier insulating film 625 by a plasma CVD method, and a _second Cu trench wiring is formed on the third barrier insulating film 625 and the SiO ₂ interlayer insulating film by using a photolithography technique. A photoresist mask for forming an opening thereon was formed. Subsequently, the exposed SiO ₂ interlayer insulating film and the third barrier insulating film 625 were etched to form an opening for connecting the second Cu trench wiring and the bonding pad. After removing the photoresist mask, a TiN film 519 was formed to a thickness of 100 to 200 nm, an Al—Cu (0.5%) film 520 was formed to a thickness of 800 to 1000 nm, and a TiN film 521 was formed to a thickness of 50 to 100 nm by sputtering. Subsequently, a photoresist mask for forming a bonding pad was formed using a photolithography technique, and after the bonding pad was formed by an etching process, the photoresist mask was removed. Then, 100 to 200 nm of SiO ₂ film 522 to cover the TiN film 521 on the bonding pads, sequentially forming a SiON film 523 by 100 to 200 nm plasma CVD method, a SiON film on the bonding pad by a photolithography technique, SiO ₂ A predetermined region of the film and the TiN film 521 was opened to expose the bonding pad, and the semiconductor device of FIG. 14 was obtained.

The above-described conventional method for manufacturing a semiconductor device is an example of a single damascene method, but a manufacturing method using a dual damascene method is also known. Patent Document 1 discloses a semiconductor device having a dual damascene structure using silicon glass (FSG) doped with fluorine as a low dielectric constant interlayer insulating film and using a SiC film as a low dielectric constant barrier film. Patent Document 2 discloses a semiconductor device using carbon-doped silicon oxide as a low dielectric constant interlayer insulating film and an amorphous material containing silicon, carbon, nitrogen, and hydrogen as a barrier film also serving as an etching stopper. ing.
JP 2002-526916 A U.S. Pat. No. 6,417,092

  In manufacturing the semiconductor device having the above-described two-layer wiring structure, the present inventor used an L-Ox film as an interlayer insulating film having a low dielectric constant and an SiC film as a barrier insulating film. As a result, a problem occurred in the electrical characteristics. Further, regardless of the type of the insulating film, the surface and the interface of the Cu wiring were oxidized. In particular, there is a problem that the via resistance increases and the capacitance between wirings increases.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which an increase in capacitance between wirings and oxidation of Cu wirings and the like are suppressed even when a long manufacturing process is required, and a method for manufacturing the same.

  The semiconductor device of the present invention is characterized in that an interlayer insulating film having a Si-H bond is provided on a base including a semiconductor substrate, and a silicon carbonitride film is formed on the interlayer insulating film. In addition, an interlayer insulating film having a Si—H bond is provided over a base including a semiconductor substrate, and a conductive film containing Cu as a main constituent element is buried in a groove formed in the interlayer insulating film. A silicon carbonitride film is formed on the film. A plurality of interlayer insulating films and conductive films are formed, and the silicon carbonitride film is formed so as to cover the uppermost conductive film and interlayer insulating film, respectively. The nitrogen concentration of this silicon carbonitride film is 10 atm% or more and less than 35 atm%, and more preferably 15 atm% or more and less than 30 atm%. %, And H is preferably in the range of 35 atm% to 45 atm%. Further, the silicon carbonitride film is characterized by further containing O at 0.5 atm% or more and less than 5 atm%. The interlayer insulating film having a Si—H bond is characterized in that the siloxane hydride is a ladder-type hydrogenated siloxane or a porous ladder-type hydrogenated siloxane. A metal nitride film is provided between the interlayer insulating film having the Si-H bond and the conductive film containing Cu as a main constituent element, and between the conductive film containing Cu as a main constituent element and the metal nitride film. Preferably has a metal film. The conductive film containing Cu as a main constituent element includes Cu containing at least one of Al, Si, Ag, W, Mg, Bi, Zn, Pd, Cd, Au, Hg, Be, Pt, Zr, Ti, and Sn. It is an alloy film. Further, the conductive film containing Cu as a main constituent element is a Cu alloy film containing Si, wherein the Si concentration is the highest on the upper surface of the conductive film and decreases as the depth increases in the bottom direction.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming an interlayer insulating film having a Si—H bond on a semiconductor substrate, and a step of forming a silicon carbonitride film on the interlayer insulating film. It is characterized by. A first step of forming an interlayer insulating film having a Si—H bond on the semiconductor substrate; a second step of processing the interlayer insulating film; and a third step of forming a barrier metal film. , A fourth step of forming a conductive film containing Cu as a main constituent element, and a fifth step of forming a silicon carbonitride film on the conductive film. The second step is a step of processing a groove in the interlayer insulating film, the third step is a step of forming a barrier metal film on a side wall and a bottom surface of the groove, and the fourth step Is a step of burying the conductive film in a groove in which the barrier metal film is formed, and the fifth step is a step of forming a silicon carbonitride film on the interlayer insulating film and the conductive film. There is a feature. The conductive film containing Cu as a main constituent element is a Si-containing film obtained by subjecting a Cu film to a silane treatment.

The present inventor pursued a cause of an increase in inter-wiring capacitance and an oxidation of Cu wiring generated when a conventional semiconductor device was manufactured by a long-term manufacturing process, and as a result, an L-Ox film constituting the conventional semiconductor device was obtained. It has been found that neither the SiO ₂ film nor the SiC film has a blocking property against moisture absorption. That is, it was found that the moisture absorption caused an increase in the capacitance between wirings and oxidation of the Cu wirings. In the present invention, a silicon carbonitride film is used as an upper layer of an interlayer insulating film having an Si-H bond such as hydrogenated polysiloxane represented by an L-Ox film. Since this silicon carbonitride film has a moisture-absorbing property, even if a film having no moisture resistance such as hydrogenated polysiloxane exists in the lower layer, moisture can penetrate from outside into the moisture-absorbing film. , And an increase in inter-wiring capacitance can be suppressed. This silicon carbonitride film is formed on a conductive film containing Cu as a main constituent element. Since the surface of the conductive film is covered with the moisture-resistant film, oxidation of the conductive film is suppressed. Further, there is no problem such as an increase in via resistance. The above effect is remarkably recognized as the number of Si—H bonds in the interlayer insulating film increases. Therefore, when an interlayer insulating film having a Si—H bond is used as a low dielectric constant film, it is highly reliable to use a combination of a silicon carbonitride film as a barrier insulating film without deteriorating electrical characteristics due to humidity. It is suitable for providing a semiconductor device having a property. The silicon carbonitride film is preferably formed so as to cover the uppermost conductive film and the interlayer insulating film having a Si—H bond.

Next, embodiments of the semiconductor device of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a first embodiment of a semiconductor device of the present invention. As shown in FIG. 1, a zeroth silicon carbonitride film (an insulating film containing Si, C, N, and H as a main constituent element) 102 is formed on a lower insulating film 101 as a barrier insulating film also serving as an etching stopper. A first L-Ox film 103, which is a ladder-type hydrogenated polysiloxane, is formed thereon. A first SiO ₂ film 104 is formed thereon. The 0th silicon carbide nitride film 102, the first L-Ox film 103, the first wiring groove formed in the first SiO ₂ film 104 Ta film 106 / TaN as the first barrier metal film A laminated film of the film 105 (the upper layer is a Ta film and the lower layer is a TaN film) is formed. The first Cu film 107 is buried inside thereof to form a Cu wiring. A first silicon carbonitride film 108 serving as a barrier insulating film is formed on the first Cu trench wiring, and a second L-Ox film 109 and a second SiO ₂ film 110 are formed on the first silicon carbonitride film 108 in the same manner. In these, via grooves are opened.

Similarly, a via is formed by burying a Ta film 112 / TaN film 111 as a second barrier metal film in the via portion and a second Cu film 113 inside thereof. Further, a second silicon carbonitride film 114 as a barrier insulating film is formed on the via, and a third L-Ox film 115 and a third SiO ₂ film 116 are similarly formed on the second silicon carbonitride film 114. Similarly, the second wiring groove formed in the second silicon carbonitride film 114, the third L-Ox film 115, and the third SiO ₂ film 116 has a Ta film 118 / as a third barrier metal film. A TaN film 117, a third Cu film 119 is buried inside the TaN film 117, and a second Cu trench wiring is formed. A third silicon carbonitride film 120 is formed on the second Cu trench wiring. This structure is further repeated as necessary, and the uppermost layer wiring (corresponding to the second Cu trench wiring in this embodiment) and the uppermost layer L-Ox film (corresponding to the third L-Ox film in this embodiment) A silicon carbonitride film is formed thereon. An aluminum bonding pad 123 is connected to the uppermost layer wiring through an opening provided in the silicon carbonitride film. The aluminum bonding pad 123 (for example, has TiN layers 122 and 124 above and below aluminum as barrier metal films) The structure is illustrated, but the structure is not limited to this.) Except for a part of the structure, a cover film 126 (SiON film or SiN film) having a moisture absorption blocking property is covered via a SiO ₂ film 125 to form a multilayer wiring. A structure is formed. In the obtained semiconductor device, the increase in the capacitance between wirings and the increase in the via resistance, which were observed in the conventional semiconductor device, were not observed.

FIG. 2 shows the structure of the semiconductor device according to the second embodiment. The difference from the first embodiment is that the via interlayer insulating film is a single layer of SiO ₂ . This structure has an advantage in stabilization of electrical characteristics and stability of reliability when the manufactured TAT is very long. It is presumed that the reason is that moisture absorption in the via process affects electrical characteristics and reliability.

In this semiconductor device, a zeroth silicon carbonitride film 202 is formed on a lower insulating film 201, and a first L-Ox film 203, which is a ladder-type hydrogenated polysiloxane, is formed thereon. A first SiO ₂ film 204 is formed thereon. A laminated film of a Ta film 206 / TaN film 205 as a first barrier metal film is formed in a wiring groove formed in the 0th silicon carbonitride film 202, the first L-Ox film 203, and the first SiO ₂ film 204. (The upper layer is a Ta film and the lower layer is a TaN film). A first Cu trench wiring 207 in which a Cu film is embedded is formed inside. A first silicon carbon nitride film 208 as a barrier insulating film is formed on the first Cu trench wiring, and a second SiO ₂ film 209 is formed thereon. Via grooves are formed in the first silicon carbonitride film 208 and the second SiO ₂ film 209, and similarly, a Ta film 211 / TaN film 210 is formed in the via portion as a second barrier metal film, and inside thereof is formed. The via is formed by burying the second Cu film 212.

Further, a second silicon carbon nitride film 213 as a barrier insulating film is formed on the via, and a third L-Ox film 214 and a third SiO ₂ film 215 are similarly formed on the second silicon carbon nitride film 213. Similarly, a Ta film 217 / TaN film 216 as a third barrier metal film is formed on the second silicon carbonitride film 213, the third L-Ox film 214, the third SiO ₂ film 215, and a third Cu The film 218 is buried to form a second Cu trench wiring. A third silicon carbonitride film 219 is formed on the second Cu trench wiring. This structure is further repeated as necessary, and the uppermost layer wiring (corresponding to the second Cu trench wiring in this embodiment) and the uppermost layer L-Ox film (corresponding to the third L-Ox film in this embodiment) A silicon carbonitride film is formed thereon. An aluminum bonding pad 222 is connected to the uppermost wiring through an opening provided in the silicon carbonitride film. The aluminum bonding pad 222 (for example, has TiN layers 221 and 223 as barrier metal films above and below aluminum, for example) The structure is illustrated, but the structure is not limited to this.) Except for a part of the structure, a cover film 225 (SiON film or SiN film) having a moisture absorbing property is coated via the SiO ₂ film 224 to form a multilayer wiring. A structure is formed. In the obtained semiconductor device, the increase in the capacitance between wirings and the increase in the via resistance, which were observed in the conventional semiconductor device, were not observed.

FIG. 3 shows a semiconductor device according to the third embodiment. Unlike the first embodiment, a dual damascene wiring structure is employed. By using this structure, the number of manufacturing steps can be reduced, and the cost of the product can be reduced. Further, since the CMP of the via can be eliminated, there is a great cost merit that a very high CMP step can be reduced. In this semiconductor device, a zeroth silicon carbonitride film 302 is formed on a lower insulating film 301, and a first L-Ox film 303, which is a ladder-type hydrogenated polysiloxane, is formed thereon. Further, a first SiO ₂ film 304 is formed thereon. A first wiring groove is formed in the zeroth silicon carbonitride film 302, the first L-Ox film 303, and the first SiO ₂ film 304, and a Ta film as a first barrier metal film is formed in this wiring groove. A laminated film of 306 / TaN film 305 (the upper layer is a Ta film and the lower layer is a TaN film) is formed.

A first Cu film 307 is buried in the inside thereof to form a first Cu trench wiring. A first silicon carbonitride film 308 serving as a barrier insulating film is formed on the first Cu trench wiring, and a second L-Ox film 309 and a second SiO ₂ film 310 are formed thereon. . Further, a second silicon carbonitride film 311 is formed thereon as an etching stopper for the second wiring groove, and a third L-Ox film 312 and a third SiO ₂ film 313 are formed thereon. The via for electrically connecting to the first Cu trench wiring and the second Cu wiring are integrated, and a second Ta film 315 is formed on the second TaN film 314, and a second Cu film is formed inside the second Ta film 315. A via and a second Cu trench wiring are formed integrally with the film 316 embedded therein, and a third silicon carbonitride film 317 is formed on the second Cu trench wiring. This structure is further repeated as necessary, and the uppermost layer wiring (corresponding to the second Cu trench wiring in this embodiment) and the uppermost layer L-Ox film (corresponding to the third L-Ox film in this embodiment) A silicon carbonitride film is formed thereon. An aluminum bonding pad 320 is connected to the uppermost layer wiring through an opening provided in the silicon carbonitride film. This aluminum bonding pad 320 (for example, has TiN layers 319 and 321 as barrier metal films above and below aluminum) Except for a part of the structure, the structure is not limited to this.) A multi-layer wiring covered with a cover film 323 (SiON film or SiN film) having a moisture absorbing property via the SiO ₂ film 322 except for a part thereof A structure is formed. In the obtained semiconductor device, the increase in the capacitance between wirings and the increase in the via resistance, which were observed in the conventional semiconductor device, were not observed.

In the first to third embodiments, the Cu film is used for the wiring and the via, but Al, Si, Ag, W, Mg, Bi, Zn, Pd, Cd, Au, Hg, Be, Pt, When a Cu alloy film containing at least one of Zr, Ti or Sn is used, the wettability is better than that of Cu, and thus there is an advantage in using a Cu alloy film. In particular, when Si is contained, the effect is great if the distribution is such that the adhesion to the silicon carbonitride film is excellent, and the Si concentration is highest on the upper surface of the conductive film, and decreases as the depth increases in the bottom direction. Such a distribution can be obtained, for example, by performing a treatment at 250 to 400 ° C. with a plasma CVD apparatus using an inorganic silane gas such as SiH ₄ , Si ₂ H ₆ , or SiH ₂ Cl ₂ as a raw material gas for a Cu film.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. First, a 0-th silicon carbide nitride film 402 with a thickness of 50 nm to 100 nm was formed over a lower insulating film 401 including a semiconductor substrate over which a transistor was formed by a plasma CVD method. Subsequently, the first L-Ox film 403 was applied and fired to form a film having a thickness of 150 nm to 350 nm. A first SiO ₂ film 404 was formed thereon by a plasma CVD method to a thickness of 50 nm to 200 nm (FIG. 4A). After applying a first ARC film 405 as an anti-reflection film on this structure, a first photoresist mask 406 patterned using a photolithography technique of a minimum L / S = 0.14 / 0.14 μm level is formed. It was formed (FIG. 4B).

Using this as a mask, the first ARC film 405, the first SiO ₂ film 404, and the first L-Ox film 403 are sequentially etched by an etching gas containing a fluorocarbon-based gas to form a zeroth silicon carbonitride film. A first wiring groove was opened so as to stop on 402. Then, after removing the photoresist mask by oxygen plasma ashing, the residue and the like were completely removed with an amine-based organic stripping solution or the like. Thereafter, the zeroth silicon carbonitride film at the bottom of the first wiring groove was removed by etch back on the entire surface. Further, the residue was removed by washing with an organic stripper. As a result, a first wiring groove pattern was formed (FIG. 4C).

Next, a TaN film 407 is formed as a first barrier metal film with a thickness of about 10 nm as a first barrier metal film after performing a degassing process and RF etching with Ar ions in a sputtering apparatus. Was formed on the surface of the substrate (first SiO ₂ film 404). A Cu seed film (not shown) was formed to a thickness of about 100 nm without breaking the vacuum. Next, a copper film 409 was formed to a thickness of about 600 nm by Cu plating (FIG. 5A).

Thereafter, firing was performed at 200 to 400 ° C. by vertical furnace annealing. Next, using a metal CMP technique, a metal other than the groove was removed to form a first Cu groove wiring in which Cu was buried in the groove (FIG. 5B). Next, a first silicon carbonitride film 410 having a thickness of 50 to 1000 nm was formed by a plasma CVD apparatus. Subsequently, a second L-Ox film 411 having a thickness of 150 to 350 nm and a second SiO ₂ film 412 having a thickness of 50 to 200 nm were sequentially formed. Using a photolithography technique for forming the first via, a second photoresist mask 414 was formed on the second ARC film 413 as a pattern of vias having a diameter of 0.14 μm (FIG. 5C).

Using this as a mask, the second ARC film 413, the second SiO ₂ film 412, and the second L-Ox film 411 are sequentially etched to form a via-etched stop on the first silicon carbonitride film 410. The groove was opened. Next, the photoresist mask and the second ARC film were removed by plasma ashing, and residues were removed with an organic stripper. After that, the first silicon carbonitride film 410 at the bottom of the via groove was removed and the entire surface was etched back in order to obtain electrical conduction with the first Cu trench wiring. Thereafter, an organic stripper was used to remove the residue. Subsequently, after degassing is performed by a sputtering apparatus, RF etching is performed using Ar ions, and then a second surface of the substrate (second SiO ₂ film 412) including the inside of the via groove (side wall and bottom surface) is formed. A Ta film 416 was formed to a thickness of about 10 nm as a barrier metal film, a Ta film 416 was formed to a thickness of 20 nm, and a Cu seed film (not shown) was formed to a thickness of about 100 nm without breaking vacuum. Next, about 300 nm of a copper film 417 was formed by Cu plating. Thereafter, firing was performed at 200 to 400 ° C. by vertical furnace annealing. Next, using a metal CMP technique, the metal other than the via was removed to form a via in which Cu was embedded in the groove (FIG. 6A).

Next, a second silicon carbonitride film 418 having a thickness of 50 to 100 nm was formed by a plasma CVD apparatus. Subsequently, a third L-Ox film 419 having a thickness of 150 to 350 nm and a third SiO ₂ film 420 having a thickness of 50 to 200 nm were sequentially formed (FIG. 6B).

  After applying a third ARC film 421 as an anti-reflection film on this structure, a third photoresist mask 422 patterned using a photolithography technique with a minimum L / S = 0.14 / 0.14 μm level is formed. (FIG. 7A).

Using this as a mask, the third ARC film 421, the third SiO ₂ film 420, and the third L-Ox film 419 are sequentially etched with an etching gas containing a fluorocarbon-based gas to form a second silicon carbonitride film 418. A second wiring groove was opened so as to stop at the top. Then, after removing the photoresist mask by oxygen plasma ashing, the residue and the like were completely removed with an amine-based organic stripping solution or the like. Thereafter, the second silicon carbonitride film 418 at the bottom of the second wiring groove was removed by overall etch back. Further, the residue was removed by washing with an organic stripper. Subsequently, after performing degassing with a sputtering apparatus, performing RF etching with Ar ions, forming a TaN film 423 as a third barrier metal film with a thickness of about 10 nm, forming a Ta film 424 with a thickness of 20 nm, and forming a vacuum. , A Cu seed film (not shown) was formed to a thickness of about 100 nm. Next, a copper film 425 was formed to a thickness of about 600 nm by Cu plating. Thereafter, firing was performed at 200 to 400 ° C. by vertical furnace annealing. Next, using a metal CMP technique, the metal other than the groove was removed to form a second Cu groove wiring in which Cu was embedded in the groove. Next, a third silicon carbonitride film 426 having a thickness of 50 to 100 nm was formed by a plasma CVD apparatus (FIG. 7B).

Thereafter, an SiO ₂ interlayer insulating film 121 having a thickness of 300 to 500 nm is formed on the third silicon carbonitride film 426 (corresponding to the third silicon carbonitride film 120 in FIG. 1) by a plasma CVD method. A photoresist mask for forming an opening on the second Cu trench wiring was formed in the film 426 and the SiO ₂ interlayer insulating film 121 by using a photolithography technique. Subsequently, the exposed SiO ₂ interlayer insulating film 121 and the third silicon carbonitride film 426 were etched to form openings for connecting the second Cu trench wiring and the bonding pads. After the removal of the photoresist mask, a TiN film 122 having a thickness of 100 to 200 nm, an Al—Cu (0.5%) film 123 having a thickness of 800 to 1000 nm, and a TiN film 124 having a thickness of 50 to 100 nm were sequentially formed by a sputtering method. Subsequently, a photoresist mask for forming a bonding pad was formed using a photolithography technique, and after the bonding pad was formed by an etching process, the photoresist mask was removed. Then, 100 to 200 nm of SiO ₂ film 125 to cover the TiN film 124 on the bonding pads, the 100 to 200 nm of SiON film 126 are sequentially formed by plasma CVD method, an SiON film 126 on bonding pad 123 by a photolithography technique Then, a predetermined region of the SiO ₂ film 125 was opened to expose the bonding pad.

  Thus, the semiconductor device having the two-layer wiring structure shown in FIG. 1 was obtained. In forming this two-layer wiring structure, no peeling occurs by CMP, the measured inter-wiring capacitance in the 0.14 μm space can be obtained as desired, the via resistance does not deteriorate, and the via resistance does not deteriorate. No increase in resistance occurred.

  Further, the inventors' experiments have found that the nitrogen concentration of the silicon carbonitride film used on the Cu wiring and the Cu via is a key to the blocking property of moisture absorption. FIG. 8 shows the nitrogen concentration measured by RBS (Backscattering Spectroscopy) in the silicon carbonitride film on the horizontal axis, and the line / space in the case of using the first embodiment = 0.14 / 0.14 μm interval. The relationship between the two values is shown with the value of the capacitance between wirings at the vertical axis as the vertical axis. As the nitrogen concentration in the silicon carbonitride film increases, the capacitance between wirings decreases, and is saturated at a nitrogen concentration of about 10 atm% (atomic%) or more. When the nitrogen concentration was 0, it was confirmed that the inter-wiring capacitance was larger by about 15% as compared with the case where the nitrogen concentration was 10 atm% or more.

  Further, as shown in FIG. 9, the relative permittivity of the silicon oxynitride film having a nitrogen concentration of about 35 atm% or more in the composition of the film is sharply increased to 5.8 or more, and the value of the dielectric constant of the film is 5% or less. The advantage of lowering the dielectric constant in the region of 0.0 or less disappears. As described above, the nitrogen concentration of the silicon carbonitride film is preferably 10 atm% or more and less than 35 atm%, and more preferably 15 atm% or more and 30 atm% or less from the viewpoint of film quality stability.

  It has been confirmed that the composition other than the nitrogen concentration in the silicon carbonitride film is good in a film in the range of 22 to 27 atm% of Si, 20 to 25 atm% of C, and 35 to 45 atm% of H. Within this range, it is considered that the above relationship is satisfied (RBS other than H concentration, H is measured by HFS (Hydrogen Front Scattering Spectroscopy)).

  FIG. 10 shows the resistance to the lower Cu wiring. The horizontal axis represents the nitrogen concentration in the silicon carbonitride film, and the vertical axis represents the via chain resistance value in the third embodiment, and shows the correlation between the two. As the nitrogen concentration in the silicon carbonitride film increases, the resistance value decreases, and it is confirmed that the resistance value of the via enters the saturation region at a nitrogen concentration of about 10 atm% or more. In the case where the nitrogen concentration was 0 atm%, peeling occurred and the yield of the via chain was poor as compared with the case where the nitrogen concentration was 10 atm% or more, and it was confirmed that although the via was not open, the average value was about 30% higher in the average value. .

Here, hydrogenated polysiloxane is used. However, although the increase in the inter-wiring capacitance could not be clearly confirmed even when the SiO ₂ interlayer insulating film was used, the increase in the via resistance could be confirmed. It was also confirmed that when a silicon carbonitride film was present on the wiring, the reliability tended to decrease as the nitrogen concentration in the film decreased. It has been confirmed that the composition other than the nitrogen concentration in the silicon carbonitride film is good in a film in the range of 22 to 27 atm% of Si, 20 to 25 atm% of C, and 35 to 45 atm% of H. It is considered that the above relationship is satisfied within this range.

  From the viewpoint of lowering the dielectric constant, it is preferable that the present insulating film further contains oxygen. O is 1 atm%, and the relative dielectric constant can be reduced to about 0.2 as compared with the case without O. It has been confirmed that when O is less than 5 atm%, there is no difference in the effect of suppressing the increase in the capacitance between wirings. However, when the content is 5 atm% or more, the above effect is sharply reduced. Therefore, the O content is preferably less than 5 atm%, and more preferably in the range of 0.5 atm% to 2 atm%. In terms of hydrogen concentration, the presence of hydrogen has the effect of reducing the Cu oxide film and has the effect of preventing oxidation of the Cu wiring. When the hydrogen concentration is less than 35 atm%, a Cu oxide film is easily formed, and the resistance value tends to increase.

  In order to confirm that the effect of having the silicon carbonitride film is due to the moisture blocking property of the film, a test of the moisture absorbing block property of the film was performed. As a sample, a silicon carbonitride film was formed on a PSG (Phospho-Silicate Glass) film formed on the entire surface. If moisture absorption cannot be blocked, the infrared absorption peak of the P = O bond in the lower PSG film disappears by checking the FTIR spectrum. As a test of the film's ability to block moisture absorption, FTIR (Fourier Transform Infrared Spectroscopy) spectra before and after storage under PCT (Pressure Cooker Test) conditions of 125 ° C., 2 atm, and 100% humidity were compared.

For reference, as shown in FIG. 11, FTIR spectra before and after PCT of a sample in which an SiO ₂ film was formed on a PSG film by a plasma CVD method having no apparent moisture absorption blocking property were compared. The P ＝ O bond existing at a wavenumber of about 1330 cm ⁻¹ was confirmed before PCT, but disappeared in the FTIR spectrum after 96 hours of PCT, and could not be confirmed. That is, it was confirmed that the moisture absorption blocking property can be confirmed by this method.

  Using a sample in which a silicon carbonitride film was formed on a PSG film by this method, a test was performed when the nitrogen concentration was changed. FIG. 12 is a spectrum comparison before and after PCT in the SiC / PSG structure, that is, when the nitrogen concentration is 0 atm%. The P = O bonds present before PCT have disappeared after 96 hours of PCT. That is, there is no moisture absorption blocking property. FIG. 13 shows the results of a silicon carbonitride film / PSG structure (the upper layer is a silicon carbonitride film and the lower layer is PSG). The nitrogen concentration of this silicon carbonitride film was 13.8 atm%. At this time, it was confirmed that almost all P ＝ O bonds existing before PCT remained even after PCT, that is, the moisture absorption blocking property was confirmed.

  Table 1 shows the nitrogen concentration in the silicon carbonitride film and the results of determination as to whether or not P = O bonds exist after PCT. When the nitrogen concentration is 10 atm%, P ＝ O bonds almost remain, and it can be determined that there is a moisture absorption blocking property in this region. At about 8 atm%, the peak of the P = O bond was slightly reduced, but it was confirmed that it was present. At a nitrogen concentration level lower than that, no P = O bond could be confirmed after PCT. That is, there is no moisture absorption blocking property.

  The results of the moisture absorption blocking property and the electrical characteristics correspond to each other, that is, it can be inferred that the moisture absorption blocking property of the silicon carbonitride film controls the electrical properties.

  Next, the relationship between the barrier metal film and the hydrogenated polysiloxane, which is a low dielectric constant film, will be described. Table 2 shows that when Ta / TaN (Ta: 20 nm for the upper layer, TaN: 10 nm for the lower layer) is used as the barrier metal film, the nitrogen concentration of TaN, the presence or absence of peeling by metal CMP, and the dust inspection at the time of TaN sputtering. The relationship with the number of defects was shown.

In a film having a nitrogen concentration of about 10 atm% or more obtained by TaN XPS (X-ray Photoelectron Spectroscopy), peeling did not occur in the case of the third embodiment, but not more than that. In this case, the Cu film was peeled off by CMP. In particular, in the case of a film of 5 atm% or less, peeling was confirmed visually. Although about 8 atm% could not be confirmed visually, peeling could be confirmed by an optical microscope. Incidentally, in the case where the interlayer insulating film is SiO ₂ , it is presumed that hydrogen of the hydrogenated polysiloxane is occluded in TaN, since peeling does not occur in TaN of any nitrogen concentration. Also, the number of dust counts on an 8-inch wafer when TaN is sputtered is shown. Particles having a particle size of 0.18 μm or more were counted. When the nitrogen concentration of TaN was less than 40 atm%, the number was 20 or less, but when it exceeded 40 atm%, the number was 20,000 or more, and overflow occurred.

  Table 3 shows the relationship between the embedding property of Cu into a via having a diameter of 0.14 μm and a height of 0.4 μm and peeling during metal CMP, depending on the structure of the barrier metal.

  A 100-nm Cu seed layer was formed on a 30-nm Ta single layer, and a 300-nm Cu plating layer was buried thereon. As an accelerated test, embedding when overheating at 450 ° C. for 12 hours was confirmed. I could not confirm. Although there was no problem in the case of Ta (20 nm) / TaN (10 nm) (Cu on top of the same condition), a burying defect was confirmed in a TaN single layer of 30 nm. The cause can be explained by the dependence of the wettability of the Cu film on the underlayer. The wettability of the Cu film to the Ta film is good, but the wettability of the Cu film to TaN is poor. This seems to have some relationship between Cu wettability and nitrogen. There was no problem in the peeling of the via Cu by CMP in the case of the TaN single layer and in the case of the Ta / TaN lamination, but in the case of the Ta single layer, the peeling was confirmed. It is presumed that the cause of this is that hydrogen of the hydrogenated polysiloxane is occluded in Ta and the metal is brittle. It is considered that when nitrogen is contained in Ta, the occlusion of hydrogen is suppressed and barrier metal embrittlement can be prevented.

  The barrier metal film is not limited to the stacked structure of Ta / TaN. The interlayer insulating film may have a structure in which H of the interlayer insulating film having a Si—H bond is not absorbed into the barrier metal film and does not weaken the metal. That is, when an interlayer insulating film having a Si-H bond and a barrier metal film having a hydrogen absorbing property are used, a layer for suppressing occlusion of H of the interlayer insulating film into the barrier metal film may be provided therebetween. . Examples of barimatal having hydrogen storage properties include Ti in addition to Ta. It is considered that TiN, like TaN, suppresses the absorption of hydrogen and can prevent the barrier metal from becoming brittle. Therefore, a combination of Ta / TiN, Ti / TaN, and Ti / TiN other than Ta / TaN is also possible.

In the above embodiment, the example in which L-Ox, which is a ladder-type hydrogenated polysiloxane, is used as the low dielectric constant interlayer insulating film has been described. However, a cage-type hydrogenated silsesquide, which is one type of cage-type hydrogenated polysiloxane, is shown. Oxane may be used. However, the effect of interposing the hydrogen absorption suppressing layer is slightly smaller than when the ladder-type hydrogenated polysiloxane is used. The same effect was confirmed when a porous ladder-type hydrogenated polysiloxane (porous L-Ox) having a relative dielectric constant of 2.4 was used. It is preferably a ladder-type hydrogenated polysiloxane or a porous ladder-type hydrogenated polysiloxane. The effect is also lower than that of hydrogenated polysiloxane, but is a hydrogenated organopolysiloxane formed by a CVD method, that is, an insulating film having both a Si—H bond and a Si—CH ₃ bond (this bond is confirmed by an FTIR spectrum or the like). Can be). For example, similar names can be obtained for Black Diamond (trade name), Coral (trade name), Aurora (trade name), and the like. Similar results were obtained with MHSQ and the like formed by the coating method. It is considered that the difference in the degree of the effect is due to the fact that H of the Si—CH ₃ bond is less likely to dissociate than H of the Si—H bond. In other words, the effect of interposing the hydrogen absorption suppressing layer was larger as the insulating film material having more Si-H bonds was used.

  According to the present invention, the first to third aspects of the present invention are realized by a combination of a low dielectric constant interlayer insulating film having a Si—H bond having good adhesion to a wiring and a barrier metal film and a silicon oxynitride film having a preferable composition. Even if the multilayer wiring structure of the nine-layer wiring structure of the embodiment was manufactured for 10 months, the capacitance between wirings did not increase. In addition, it was possible to manufacture without increasing the via resistance and without peeling off the film.

FIG. 1 is a diagram illustrating a semiconductor device according to a first embodiment of the present invention. FIG. 4 is a diagram illustrating a semiconductor device according to a second embodiment of the present invention. FIG. 9 is a diagram illustrating a semiconductor device according to a third embodiment of the present invention. FIG. 4 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a diagram showing a relationship between a nitrogen concentration of a silicon carbonitride film and an inter-wiring capacitance according to the first embodiment of the present invention. FIG. 3 is a diagram showing a relationship between a nitrogen concentration of a silicon carbonitride film and a relative dielectric constant. FIG. 11 is a diagram showing a relationship between a nitrogen concentration of a silicon carbonitride film and a via resistance according to a third embodiment of the present invention. Is a diagram illustrating the FTIR spectra before and after the PCT SiO ₂ film / PSG film. FIG. 4 is a diagram showing FTIR spectra of a SiC film / PSG film before and after PCT. FIG. 4 is a diagram showing FTIR spectra of a silicon carbonitride film / PSG film before and after PCT. FIG. 14 is a diagram showing a semiconductor device according to a conventional embodiment. FIG. 11 is a diagram illustrating a manufacturing process of the semiconductor device according to the conventional embodiment. FIG. 11 is a diagram illustrating a manufacturing process of the semiconductor device according to the conventional embodiment. FIG. 11 is a diagram illustrating a manufacturing process of the semiconductor device according to the conventional embodiment. FIG. 11 is a diagram illustrating a manufacturing process of the semiconductor device according to the conventional embodiment.

Explanation of reference numerals

101 ... underlying insulating films 102, 108, 114, 120, 202, 208, 213, 219, 302, 308, 311, 317, 402, 410, 418, 426 ... silicon carbonitride films 103, 109, 115 , 203, 214, 303, 309, 312, 403, 411, 419 ... L-Ox films 104, 110, 116, 121, 125, 204, 209, 215, 304, 310, 313, 404, 412, 420 , 504,509,514,604,612,620 ··· SiO ₂ film 105,111,117,205,210,216,305,314,407,415,423 ··· TaN film 106,112,118, 206, 211, 217, 306, 315, 408, 416, 424 ... Ta films 107, 113, 11 9, 207, 211, 218, 307, 316, 409, 417, 425, 506, 511, 516, 609, 617, 624: Cu film 122, 124: TiN film 123: Al-Cu film 126 SiON films 502, 507, 512, 517, 602, 609, 616, 623 barrier insulating films 503, 508, 513, 603, 611, 619 low dielectric constant films 505, 510, 515 , 607, 615, 623 ... barrier metal film

Claims (23)

A semiconductor device having an interlayer insulating film having a Si-H bond over a base including a semiconductor substrate, and a silicon carbonitride film formed on the interlayer insulating film. An interlayer insulating film having a Si-H bond is provided over a base including a semiconductor substrate, and a conductive film containing Cu as a main constituent element is buried in a groove formed in the interlayer insulating film. And a silicon carbonitride film is formed on the semiconductor device. 3. The semiconductor device according to claim 2, wherein a silicon carbonitride film is formed on said interlayer insulating film. 3. The semiconductor device according to claim 2, wherein the interlayer insulating film and the conductive film are formed in a plurality of layers, respectively, and the silicon carbonitride film is formed so as to cover the uppermost conductive film and the interlayer insulating film, respectively. Or the semiconductor device according to 3. The semiconductor device according to claim 1, wherein a nitrogen concentration of the silicon carbonitride film is not less than 10 atm% and less than 35 atm%. 6. The semiconductor device according to claim 5, wherein a nitrogen concentration of the silicon carbonitride film is 15 atm% or more and 30 atm% or less. 7. The silicon carbonitride film according to claim 5, wherein Si is in a range of 22 to 27 atm%, C is in a range of 20 to 25 atm%, and H is in a range of 35 to 45 atm%. 8. Semiconductor device. The semiconductor device according to claim 5, wherein the silicon carbonitride film further contains O as a constituent element of 0.5 atm% or more and less than 5 atm%. The semiconductor device according to claim 1, wherein the interlayer insulating film having the Si—H bond is a ladder-type hydrogenated polysiloxane film or a porous ladder-type hydrogenated polysiloxane film. A metal nitride film is provided between the interlayer insulating film and the conductive film containing Cu as a main constituent element, and a metal film is provided between the conductive film containing Cu as a main constituent element and the metal nitride film. 4. The semiconductor device according to claim 2, wherein: The conductive film containing Cu as a main constituent element includes at least one of Al, Si, Ag, W, Mg, Bi, Zn, Pd, Cd, Au, Hg, Be, Pt, Zr, Ti, and Sn. 11. The semiconductor device according to claim 2, wherein the semiconductor device is a Cu alloy film. The conductive film containing Cu as a main constituent element is a Cu alloy film containing Si, and the Si concentration is highest on the upper surface of the conductive film and decreases as the depth increases in the bottom direction. 11. The semiconductor device according to any one of claims 10 to 10. A method for manufacturing a semiconductor device, comprising: a step of forming an interlayer insulating film having a Si—H bond on a semiconductor substrate; and a step of forming a silicon carbonitride film on the interlayer insulating film. A first step of forming an interlayer insulating film having a Si—H bond on a semiconductor substrate;
A second step of processing the interlayer insulating film;
A third step of forming a barrier metal film;
A fourth step of forming a conductive film containing Cu as a main constituent element,
A fifth step of forming a silicon carbonitride film on the conductive film;
A method for manufacturing a semiconductor device, comprising: The second step is a step of processing a groove in the interlayer insulating film,
The third step is a step of forming a barrier metal film on a side wall and a bottom surface of the groove.
The fourth step is a step of burying the conductive film in a groove in which the barrier metal is formed,
The method according to claim 14, wherein the fifth step is a step of forming a silicon carbonitride film on the interlayer insulating film and the conductive film. The method according to claim 13, wherein a nitrogen concentration of the silicon carbonitride film is 10 atm% or more and less than 35 atm%. 17. The method according to claim 16, wherein a nitrogen concentration of the silicon carbonitride film is 15 atm% or more and 30 atm% or less. 18. The silicon carbonitride film according to claim 16, wherein Si is in a range of 22 atm% to 27 atm%, C is in a range of 20 atm% to 25 atm%, and H is in a range of 35 atm% to 45 atm%. Manufacturing method of a semiconductor device. 19. The method of manufacturing a semiconductor device according to claim 16, wherein the silicon carbonitride film further contains O as a constituent element of 0.5 atm% or more and less than 5 atm%. 20. The semiconductor device according to claim 13, wherein the interlayer insulating film having a Si-H bond is a ladder-type hydrogenated polysiloxane film or a porous ladder-type hydrogenated polysiloxane film. Method. 16. The method according to claim 15, wherein in the third step, a barrier metal film is formed on a side wall and a bottom surface of the trench such that the metal nitride film is on the side of the interlayer insulating film. . The conductive film containing Cu as a main constituent element includes at least one of Al, Si, Ag, W, Mg, Bi, Zn, Pd, Cd, Au, Hg, Be, Pt, Zr, Ti, and Sn. 22. The method according to claim 14, wherein the method is a Cu alloy film. 22. The method of manufacturing a semiconductor device according to claim 14, wherein the conductive film containing Cu as a main constituent element is a Si-containing film obtained by subjecting a Cu film to a silane treatment.

Images