JP2004247536A - Device provided with thin film transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve current driving force and long-term reliability while reducing an off-leak current in a device provided with a thin film transistor. <P>SOLUTION: At least one thin film transistor comprises a semiconductor layer having a low concentration impurity area 16 held between a channel area 12 and at least one of a source/drain area 15, and comprises also a 1st gate electrode 14a formed on a 1st insulating layer 13 on the semiconductor layer, a 2nd insulating layer 17 formed on the 1st gate electrode 14a, a source/drain electrode 19 respectively electrically connected to both of the source/drain area 15 on the 2nd insulating layer 17, and a 2nd gate electrode 14b electrically connected to the 1st gate electrode 14a on the 2nd insulating layer 17. At least a part of an area which is not superposed to the 1st gate electrode 14a out of the 2nd gate electrode 14b is superposed at least to a part of the low concentration impurity area 16. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a device including a thin film transistor and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, liquid crystal display devices have been widely used because of their advantages such as light weight, thinness, and low power consumption. In particular, when an active matrix liquid crystal display device is used, the number of pixels can be increased and the contrast is improved as compared with a passive matrix liquid crystal display device, so that high-quality display can be performed.
[0003]
In an active matrix type liquid crystal display device, each pixel is provided with a switching element such as a thin film transistor (hereinafter sometimes referred to as “TFT”). In this specification, a substrate on which a switching element is formed is referred to as an “active matrix substrate”. A typical active matrix liquid crystal display device includes an active matrix substrate, a counter substrate, and a liquid crystal layer provided therebetween. The active matrix substrate is provided with a pixel electrode for each pixel which is one unit of image display, and each pixel electrode is connected to a switching element arranged corresponding to each pixel electrode. By controlling the on / off of the switching element connected to each pixel electrode, a voltage is applied to the liquid crystal layer by the pixel electrode and the counter electrode formed on the counter substrate to change the alignment state of the liquid crystal layer. Display is performed by
[0004]
Conventionally, a TFT using an amorphous silicon thin film has been widely used as a switching element of an active matrix type liquid crystal display device. Recently, a TFT using a crystalline silicon thin film (polysilicon thin film) has also attracted attention. Since the field effect mobility of the crystalline silicon film is higher than the field effect mobility of the amorphous silicon thin film, various functional circuits can be formed using the polysilicon thin film. For example, when a polysilicon thin film is used, not only a TFT for a pixel but also a TFT for a driving circuit which requires high-speed operation can be formed.
[0005]
The main characteristics required for forming various functional circuits using TFTs are that the TFTs have a large current driving force, a small off-leak current, and a high long-term reliability. Here, one of the factors that hinder long-term reliability of a TFT is deterioration due to hot carriers. “Degradation due to hot carriers” means that some of the hot carriers generated by the electric field concentration near the drain are injected into the gate insulating film or defect levels are formed in the silicon film. Fluctuates.
[0006]
A conventional N-channel TFT having a single drain structure has a relatively large current driving force. In addition, since the number of manufacturing steps is small due to the simple structure, there is an advantage that manufacturing can be performed at low cost. On the other hand, since deterioration due to hot carriers is likely to occur, the driving voltage must be limited to a low voltage of several volts in order to ensure long-term reliability. In addition, there is a problem that the off-leak current is large.
[0007]
As a structure of a TFT that solves these problems, a lightly doped drain region (hereinafter sometimes abbreviated as “LDD region”) is formed in at least one of a channel region and a source region / drain region of the TFT. Known structures are known. Such a structure is called “LDD structure”. The LDD region can reduce the electric field concentration near the drain, so that the hot carrier deterioration resistance (that is, long-term reliability) and the off-leak current can be improved as compared with the single drain structure TFT. On the other hand, since the LDD region serves as a resistor, the current driving force is lower than that of the TFT having the single drain structure.
[0008]
If the impurity concentration in the LDD region is reduced in order to further enhance the resistance to hot carrier deterioration, the resistance of the LDD region increases, so that the current driving force of the TFT further decreases. Conversely, when the impurity concentration in the LDD region is increased to increase the current driving force, the electric field concentration is not sufficiently relaxed, and the resistance to hot carrier deterioration is reduced. Therefore, it is difficult for the TFT having the LDD structure to increase the current driving force while improving the long-term reliability by increasing the hot carrier deterioration resistance.
[0009]
As a TFT structure for solving this problem, a structure in which a gate electrode overlaps an LDD region is known. Such a structure is called “GOLD (Gate-drain Overlapped LDD) structure”. In a TFT having a GOLD structure, when a voltage is applied to a gate electrode, electrons serving as carriers are accumulated in an LDD region overlapping the gate electrode. Therefore, the resistance of the LDD region can be reduced without increasing the impurity concentration of the LDD region, so that a decrease in the current driving force of the TFT can be suppressed and the hot carrier deterioration resistance, that is, long-term reliability can be improved. .
[0010]
However, a TFT having a GOLD structure has a disadvantage that an off-leak current is larger than a TFT having an LDD structure (a structure in which a gate electrode and an LDD region do not overlap) as described above. It is considered that this is because the inversion layer is formed in the LDD region overlapping the gate electrode even when the TFT is off. In the GOLD structure, a gate / drain overlap capacitance occurs because the gate electrode and the LDD region overlap. As a result, it is necessary to increase the gate capacitance. If the gate capacitance increases, the load capacitance during operation of the circuit including the TFT increases, which may adversely affect the circuit operation. This adverse effect is particularly remarkable when the channel length of the TFT is short.
[0011]
As described above, each of the conventional TFT structures has advantages and disadvantages, and any TFT having any structure satisfies all the requirements for high current driving force, low off-leak current characteristics, and long-term reliability. It is difficult. Therefore, attempts have been made to obtain desired circuit characteristics by combining TFTs having different structures. However, since TFTs having different structures are formed on the same substrate, the manufacturing process becomes complicated.
[0012]
On the other hand, for the purpose of improving TFT characteristics, Patent Documents 1 to 3 propose a TFT structure in which a gate electrode has a two-layer structure of a main gate electrode and a sub-gate electrode.
[0013]
Patent Literature 1 describes a top-gate TFT structure in which a sub-gate electrode is formed at least above a gate electrode or below a channel region with an insulating film interposed therebetween. In this structure, an offset region is provided between the drain and the channel region, and the offset region overlaps with the sub-gate electrode. By applying a negative voltage approximately equal to the drain voltage to the sub-gate electrode, the off-leak current is suppressed.
[0014]
Patent Documents 2 and 3 disclose a structure in which a sub-gate electrode having the same potential as the main gate electrode is provided over the main gate electrode via an insulating film. Since the sub-gate electrode overlaps the offset region or LDD region located at the end of the main gate electrode, an effect similar to that of the GOLD structure, that is, a high current driving force can be obtained. Further, since the sub-gate electrode is provided on the main gate electrode with an insulating film interposed therebetween, the thickness of the insulating film on the LDD region is larger than the thickness of the gate insulating film on the channel portion. Therefore, an effect similar to that of the LDD structure in which the off-leak current can be suppressed can be obtained.
[0015]
[Patent Document 1]
JP-A-5-90586
[Patent Document 2]
JP-A-6-13407
[Patent Document 3]
JP-A-6-310724
[0016]
[Problems to be solved by the invention]
Even the TFT having the above-described structure has various problems as follows.
[0017]
The TFT structure of Patent Document 1 has a four-terminal structure when the sub-gate electrode is not set to the same potential as the drain voltage, so that wiring in a circuit is complicated. When the sub-gate electrode is set to the same potential as the drain, the current drivability as a static characteristic of the transistor increases, but the drain voltage fluctuates during circuit operation. It greatly decreases.
In the TFT structures disclosed in Patent Documents 2 and 3, the sub-gate electrode is formed of a third electrode layer different from the main gate electrode and the source / drain electrodes. Therefore, the manufacturing process of the TFT having the structure disclosed in these patent documents is more complicated than the manufacturing process of the TFT having no sub-gate electrode. Further, in the TFT structure of Patent Document 2, the LDD region cannot be formed in a self-aligned manner. Therefore, in order to secure the minimum LDD length (length of the LDD region in the channel direction), an LDD region having an LDD length longer than the necessary minimum LDD length in consideration of mask alignment accuracy in a photolithography process. Need to be formed. As a result, the gate / drain overlap capacitance increases, which may adversely affect circuit operation.
[0018]
The present invention has been made in view of the above circumstances, and a main object of the present invention is to improve current driving capability, low off-leak current characteristics, and long-term reliability of a thin film transistor in a device including the thin film transistor. Another object of the present invention is to provide a method for easily manufacturing such an apparatus without complicating the manufacturing process.
[0019]
[Means for Solving the Problems]
An apparatus according to the present invention is an apparatus including a plurality of thin film transistors, wherein at least one of the plurality of thin film transistors is a semiconductor layer having a channel region, a source region, and a drain region, and the channel region and the source region. Alternatively, a semiconductor layer having a low-concentration impurity region sandwiched between at least one of the drain region and having an impurity concentration lower than that of the source region and the drain region; and a first layer formed on the semiconductor layer. An insulating layer, a first gate electrode provided on the first insulating layer, a second insulating layer formed on the first gate electrode, and a second insulating layer on the second insulating layer. A source electrode and a drain electrode formed of a conductive layer provided on the second substrate and electrically connected to the source region and the drain region, respectively; A second gate electrode formed from a conductive layer provided on the first layer and electrically connected to the first gate electrode, wherein the first gate electrode and the second gate electrode At least a portion of the non-overlapping region and at least a portion of the low-concentration impurity region overlap, thereby achieving the above object.
[0020]
In a preferred embodiment, the low-concentration impurity region is formed in a self-aligned manner with respect to the first gate electrode.
[0021]
In a preferred embodiment, an area of a portion of the second gate electrode that does not overlap with the first gate electrode and an area of the low-concentration impurity region overlap with each other has an area smaller than an area of the low-concentration impurity region. It is 1/4 or more and 4/5 or less.
[0022]
In a preferred embodiment, the thickness of the portion of the second insulating layer where the second gate electrode is provided is the same as the thickness of the portion of the second insulating layer where the source electrode or the drain electrode is provided. It is smaller than the thickness of the part where it is.
[0023]
The plurality of thin film transistors include another thin film transistor different from the at least one thin film transistor, wherein the at least one thin film transistor and the other thin film transistor are formed on the same support, and a gate of the other thin film transistor is formed. The electrode may be provided under the second insulating layer of the at least one thin film transistor.
[0024]
The manufacturing method of the present invention is a method of manufacturing a device including a thin film transistor, comprising: (a) forming a first insulating layer on a semiconductor layer; and (b) forming a first insulating layer on the first insulating layer. Providing a first gate electrode; and (c) forming a source region, a drain region, and a low-concentration impurity region having an impurity concentration lower than those of the source region and the drain region in the semiconductor layer, respectively. (D) forming a second insulating layer on the first gate electrode; and (e) forming the first gate electrode, the source region, and the second insulating layer on the second insulating layer. Forming first, second, and third contact holes respectively reaching the respective surfaces of the drain region; and (f) inside the first, second, and third contact holes and on the second insulating layer. To provide a conductive layer (G) a source electrode and a drain electrode electrically connected to the source region and the drain region, respectively; and a second gate electrode electrically connected to the first gate electrode, from the conductive layer. Forming at least a part of a region of the second gate electrode that does not overlap with the first gate electrode, at least partially with the low concentration impurity region. Which achieves the above object.
[0025]
In a preferred embodiment, the step (c) includes a step of forming the low-concentration impurity region by doping the semiconductor layer with an impurity using the first gate electrode as a mask.
[0026]
The step (c) includes: (c-1) doping the semiconductor layer with an impurity at a first dose using the first gate electrode as a mask; and (c-2) the first insulating layer. Is covered with a photoresist, and the semiconductor layer is doped with an impurity at a second dose using the first gate electrode and the photoresist as a mask, wherein the second dose is And a step higher than the first dose.
[0027]
The step (b) includes a step of forming a first electrode layer constituting a part of the first gate electrode, and a step of forming another part of the first gate electrode on the first electrode layer. Forming a second electrode layer to be formed, wherein the second electrode layer has a width in a channel direction smaller than a width of the first electrode layer in a channel direction. -1) may include doping an impurity in a region of the semiconductor layer covered by the first electrode layer, which is not covered by the second electrode layer.
[0028]
The step (b) is a step of providing a first gate electrode having a first shape on the semiconductor layer, and the step (c) is (c1) a first gate electrode having the first shape. (C2) etching the first gate electrode having the first shape with the first gate electrode having the second shape by etching the first gate electrode having the first shape. (C3) forming an electrode, wherein the width of the first gate electrode having the second shape in the channel direction is smaller than the width of the first gate electrode having the first shape in the channel direction; A) doping the semiconductor layer with an impurity at a fourth dose using the first gate electrode having the second shape as a mask, wherein the fourth dose is greater than the third dose; Including low process Good.
[0029]
The step (d) includes: (d-1) forming a first layer constituting a part of the second insulating layer on the first gate electrode; and (d-2) forming the first layer. Forming the second layer constituting another part of the second insulating layer on one layer.
[0030]
In the step (d-2), the second layer is formed so as to cover a part of the first layer, and in the step (g), the source electrode and the drain electrode are formed of the second and third electrodes. The gate electrode is formed from the inside of the contact hole and the conductive layer formed on the second layer, and the gate electrode is formed from the inside of the first contact hole and the conductive layer formed on the first layer. Is also good.
[0031]
The manufacturing method according to the present invention is a method for manufacturing a device including a first thin film transistor and a second thin film transistor, comprising: (a) a first transistor forming region where the first thin film transistor is formed; Forming a first insulating layer on the semiconductor layer in each of the second transistor forming regions where the thin film transistors are formed; and (b) providing a first gate electrode on the first insulating layer (C) forming a source region, a drain region, and a low-concentration impurity region having an impurity concentration lower than those of the source region and the drain region in the semiconductor layer; Forming a second insulating layer on the first gate electrode; and (e) forming the first gate electrode on the second insulating layer in the first transistor formation region. First, second, and third contact holes reaching respective surfaces of the source region and the drain region are respectively formed. In the second transistor formation region, the source region and the drain region are formed in the second insulating layer. And (f) forming a conductive layer inside the first, second, and third contact holes and on the second insulating layer, respectively. And (g1) in the first transistor formation region, a source electrode and a drain electrode electrically connected to the source region and the drain region, respectively, and an electrical connection with the first gate electrode from the conductive layer. Forming a second gate electrode connected to the first gate electrode, wherein the second gate electrode overlaps with the first gate electrode of the second gate electrode. (G2) electrically connecting the source region and the drain region to the source region and the drain region, respectively, from the conductive layer in the second transistor formation region. Forming a source electrode and a drain electrode respectively connected to the semiconductor device, thereby achieving the object described above.
[0032]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of a device including a thin film transistor according to the present invention will be described with reference to the drawings. In this specification, the “device including a thin film transistor” widely includes a semiconductor device such as an active matrix substrate, a liquid crystal display device, an organic EL display device, and the like.
[0033]
The device of each embodiment of the present invention includes a plurality of thin film transistors. 1 to 4 are schematic cross-sectional views illustrating a manufacturing process and a structure of a thin film transistor in the device of each embodiment. Note that the device of each embodiment may include at least one thin film transistor shown in FIGS. Although one thin film transistor is shown in each of FIGS. 1 to 4, a plurality of thin film transistors can be formed simultaneously on the same support by the illustrated method.
[0034]
(1st Embodiment)
The device of the present embodiment includes an N-channel thin film transistor 1 shown in FIG. The thin film transistor 1 has a semiconductor layer supported on a substrate 11 having an insulating surface. In the semiconductor layer, a channel region 12, a source region and a drain region 15, and an LDD region (low-concentration impurity region) 16 having an impurity concentration lower than that of the source region and the drain region 15 are formed. In the present embodiment, the LDD region 16 is formed between the channel region 12 and the drain region 15. Note that when the source side and the drain side of the thin film transistor 1 are sometimes used interchangeably, it is preferable to provide the LDD regions 16 between the channel region 12 and the source and drain regions 15, respectively. When the source side and the drain side of the thin film transistor 1 are not interchanged, it is preferable to form the LDD region 16 only between the channel region 12 and the drain region 15 in order to suppress a reduction in current driving force.
[0035]
On the semiconductor layer, a main gate electrode 14a is provided via a gate insulating film 13. The main gate electrode 14a is covered with an insulating layer. The insulating layer is, for example, an interlayer insulating film 17 (first and second interlayer insulating films 17a and 17b) having a two-layer structure. This interlayer insulating film 17 may have a single-layer structure or a multilayer structure of two or more layers. In the first and second interlayer insulating films 17a and 17b, contact holes 18s, 18d and 18g reaching the source and drain regions 15 of the semiconductor layer and the main gate electrode 14a, respectively, are formed. By adjusting the thickness of the first and second interlayer insulating films 17a and 17b or by partially laminating the first and second interlayer insulating films 17a and 17b, the thickness of the portion where the sub-gate electrode 14b is provided can be reduced to provide the source electrode or the drain electrode 19. It can be smaller than the thickness of the part.
[0036]
From the conductive layer formed on the second interlayer insulating film 17b (including the inside of the contact holes 18s, 18d, and 18g), the source and drain electrodes 19 and the sub-gate electrode 14b are respectively formed. Therefore, the source and drain electrodes 19 are electrically connected to the source and drain regions 15 of the semiconductor layer, respectively, and the sub-gate electrode 14b is electrically connected to the main gate electrode 14a. At least a part of the sub-gate electrode 14b that does not overlap with the main gate electrode 14a and at least a part of the LDD region 16 overlap.
[0037]
Next, a method for manufacturing the thin film transistor 1 will be described with reference to FIGS.
[0038]
First, the substrate 11 is prepared. The substrate 11 only needs to have an insulating surface on which the thin film transistor 1 is formed, and may be a Si substrate or a metal substrate whose surface is covered with an insulating layer other than a quartz substrate or a glass substrate. In the present embodiment, as the substrate 11, a SiN film as a movable ion prevention film on a glass substrate, and SiO 2 as a stress relaxation layer on the SiN film. ₂ A film formed by a CVD method or a sputtering method is used. SiN film and SiO ₂ The thickness of each of the films is, for example, 50 nm or more and 100 nm or less.
[0039]
Next, a semiconductor layer is formed on the substrate 11. The semiconductor layer is, for example, a crystalline silicon film having a thickness of 40 nm or more and 100 nm or less. The crystalline silicon film can be manufactured by the following method. First, an amorphous silicon film is deposited on the substrate 11 by the CVD method. Thereafter, the amorphous silicon film is crystallized by irradiating a laser beam. As the laser beam, a pulse oscillation type or continuous oscillation type excimer laser beam is desirable, but a continuous oscillation type argon laser beam may be used. Alternatively, after a catalytic element for promoting crystallization, such as Ni, is attached to the surface of the amorphous silicon film, the amorphous silicon film may be crystallized by heat treatment (eg, laser irradiation).
[0040]
On the crystalline silicon film, for example, 100 nm of SiO ₂ A gate insulating film 13 made of a film is formed by a chemical vapor deposition method (CVD method) or the like. Thereafter, a main gate electrode 14a is formed on the gate insulating film 13. The main gate electrode 14a can be formed by, for example, forming a tungsten (W) film by a sputtering method, forming a photoresist on the W film, and etching the W film using the photoresist as a mask. Note that, before forming the main gate electrode 14a, channel doping for adjusting the threshold voltage of the transistor may be performed. Further, the main gate electrode may be composed of a single layer formed using a W film or the like, or may have a laminated structure of two or more layers formed by laminating a TaN film and a W film, for example. Is also good.
[0041]
Next, as shown in FIG. 1A, the semiconductor layer is doped with an impurity (for example, phosphorus) using the main gate electrode 14a as a mask. Thus, an LDD region 16 is formed in a region of the semiconductor layer that does not overlap with the main gate electrode 14a. When the acceleration voltage for implanting phosphorus ions is 50 kV, the dose of phosphorus is 1 × 10 ^Thirteen atoms / cm ² 8 × 10 or more ^Thirteen atoms / cm ² The following is preferred. A region of the semiconductor layer overlapping the main gate electrode 14a becomes the channel region 12. Accordingly, the length of the channel region 12 in the channel direction (channel length) is substantially equal to the length of the main gate electrode 14a in the channel direction. The length of the main gate electrode 14a in the channel direction and the channel length of the channel region are, for example, 4 μm.
[0042]
Thereafter, as shown in FIG. 1B, a photoresist 10 is formed by, for example, a photolithography method. Using the photoresist 10 as a mask, a source region and a drain region 15 are formed in a region of the semiconductor layer which does not overlap with the photoresist 10 by doping impurities such as phosphorus. When the acceleration voltage for implanting phosphorus ions is 50 kV, the dose of phosphorus is 1 × 10 ^Fifteen atoms / cm ² 8 × 10 or more ^Fifteen atoms / cm ² The following is preferred. On the other hand, the region of the semiconductor layer overlapping with the photoresist 10 remains as the LDD region 16. Therefore, the length of the LDD region 16 in the channel direction is determined by the length of the photoresist 10 in the channel direction. The optimal length of the LDD region 16 in the channel direction depends on the power supply voltage used and the alignment accuracy during photolithography. In this embodiment, an LDD region 16 having a length in the channel direction of 2 μm is formed between the channel region and the drain region. Note that, as described above, the LDD regions 16 may be formed on both sides (the source side and the drain side) of the channel region, or may be formed only on the drain side as in the present embodiment.
[0043]
Next, as shown in FIG. 1C, after an interlayer insulating film 17 is formed so as to cover the main gate electrode 14a, contact holes 18s, 18d, and 18g are formed in the interlayer insulating film 17. The interlayer insulating film 17 includes a first interlayer insulating film 17a made of a SiN film and a SiO 2 film formed on the first interlayer insulating film 17a. ₂ It is preferable to have a second interlayer insulating film 17b made of a film. The reason why such an interlayer insulating film is preferable is as follows. The SiN film of the first interlayer insulating film 17a is advantageously increased in hydrogen content at the time of film formation, so that a crystal defect portion of the crystalline Si film can be terminated with hydrogen by a subsequent heat treatment. However, when the interlayer insulating film 17 is composed of only the SiN film, the relative dielectric constant of the SiN film is SiO 2 ₂ Is approximately twice as large as the above, the capacitance between the electrodes sandwiching the interlayer insulating film is increased, and as a result, the load of the circuit operation including the TFT is increased. In the case of the interlayer insulating film 17 composed of only the SiN film, it is difficult to prevent disconnection of the electrode formed thereon by flattening the step of the main gate electrode 14a. Therefore, as shown in the figure, a SiON film is formed on the first interlayer insulating film 17a of the SiN film. ₂ By forming the second interlayer insulating film 17b, the capacitance between the electrodes can be reduced and the upper surface of the interlayer insulating film 17 can be flattened. The thicknesses of the first interlayer insulating film 17a and the second interlayer insulating film are, for example, 300 nm and 700 nm, respectively. The structure of the interlayer insulating film 17 is not limited to this, and may be, for example, SiO 2 ₂ The film may have a single-layer structure. In this case, SiO ₂ After the film is formed, by performing a heat treatment in a hydrogen atmosphere of 3 to 100%, the crystal defect portion of the crystalline Si film can be terminated with hydrogen. After the formation of the interlayer insulating film 17, contact holes 18g, 18s, and 18d reaching the main gate electrode 14a, the source region, and the drain region 15, respectively, are formed by, for example, photolithography and etching.
[0044]
Subsequently, a conductive film is formed on the interlayer insulating film 17 (including the inside of the contact holes 18s, 18d, and 18g) by, for example, a sputtering method. From this conductive film, a source electrode and a drain electrode 19 having a desired shape are formed by photolithography and etching, and at the same time, a sub-gate electrode 14b is formed (FIG. 1D). In this embodiment, a stacked film of TiN / Al / TiN / Ti is formed from the upper layer as the conductive film. When the source electrode or the drain electrode 19 is formed using such a laminated film, it is possible to prevent hillocks due to diffusion of the electrode material into the Si film and stress migration. Note that the conductive film may be a single-layer film of Al, Cu, or the like. The sub-gate electrode 14b may completely overlap the LDD region 16 or only partially overlap it. The area of the portion where the sub-gate electrode 14b overlaps the LDD region 16 is preferably at least 1/4 of the area of the entire LDD region 16, and more preferably at least 3/4. If it is 1/4 or more, the current driving force and hot carrier deterioration resistance of the TFT can be improved. If it is 3/4 or more, the same high characteristics as those in the case where the LDD region 16 completely overlaps ( This is because current driving force and hot carrier deterioration resistance can be obtained. On the other hand, the area of the overlapping portion is preferably not more than ／ of the area of the entire LDD region 16. This is because if it is 4/5 or less, the same characteristics as the GOLD structure can be obtained, and the overlap capacity can be reduced. In the present embodiment, the overlap between the LDD region 16 and the sub-gate electrode 14b is about 1.5 μm with respect to the length of the LDD region 16 of 2 μm, so that the sub-gate electrode 14b is の of the area of the LDD region 16. The areas overlap. As a result, the TFT of the present embodiment can obtain almost the same high transistor characteristics as the TFT having the configuration in which the sub-gate electrode 14b completely covers the LDD region 16 (overlapping 2 μm). Further, even if the overlap between the LDD region 16 and the sub-gate electrode 14b is 0.5 μm (１ ／ of the area of the LDD region), a TFT having a structure in which the sub-gate electrode does not overlap with the LDD region 16 (conventional LDD structure) is used. In comparison, the current mobility and the resistance to hot carrier deterioration can be improved.
[0045]
Although FIG. 1 illustrates an example of an N-channel thin film transistor, a P-channel thin film transistor can be formed in a similar manner. In the case of a P-channel thin film transistor, the LDD region 16, the source region, and the drain region 15 can be formed by doping the semiconductor layer with boron or the like instead of phosphorus as an impurity. After the doping, heat treatment is preferably performed to reduce the resistance of the source region and the drain region 15. Furnace annealing, laser annealing, and lamp annealing can be performed as the heat treatment.
[0046]
The device of the present embodiment may be one in which the above-mentioned thin film transistor 1 and another thin film transistor different from the thin film transistor 1 are formed on the same support. Other thin film transistors can have the same configuration as the thin film transistor 1 except that, for example, no sub-gate electrode is provided. Such a device can be manufactured by a process similar to the manufacturing process of the thin film transistor 1. For example, in FIG. 1D, of the plurality of main gate electrodes 14a, a sub-gate electrode is provided only on the main gate electrode 14a forming the thin film transistor 1, and a sub-gate electrode is formed on the main gate electrode 14a forming another thin film transistor. By omitting the electrodes, the thin film transistor 1 and another thin film transistor can be formed on the same substrate 11. In this case, the gate electrode of the other thin film transistor is constituted only by the main gate electrode provided under the interlayer insulating films 17a and 17b of the thin film transistor 1.
[0047]
Since the device including the thin film transistor of the present embodiment has the above-described configuration, it is possible to improve the current driving force and the hot carrier deterioration resistance while suppressing the off-leak current.
[0048]
When a device including the thin film transistor of this embodiment is manufactured by the above-described process, a sub-gate electrode, a drain electrode, and a source electrode are formed from the same conductive film, so that the number of manufacturing steps can be reduced. Further, even when TFTs having different structures are formed over the same substrate, a TFT having a desired structure can be easily formed in a desired region on the substrate without increasing the number of steps.
[0049]
(Second embodiment)
Next, a second embodiment of the device according to the present invention will be described.
[0050]
First, a semiconductor layer and a gate insulating film 23 are formed on a substrate 21 by the same steps as in the first embodiment. Thereafter, an electrode film such as a W film is formed on the gate insulating film 23 by a sputtering method. Next, a photoresist 20 is formed on the electrode film by a photolithography method or the like. Using this photoresist 20 as an etching mask, a first main gate electrode etching is performed to obtain a main gate electrode 24a '. In the first main gate electrode etching, the main gate electrode 24a 'having a tapered portion is obtained as shown in FIG. After the first main gate electrode etching, using the main gate electrode 24a 'as a mask, a high dose (for example, 1 × 10 ^Fifteen atoms / cm ² 8 × 10 or more ^Fifteen atoms / cm ² The source region and the drain region 25 are formed in the semiconductor layer by doping impurities such as phosphorus in the following (FIG. 2A).
[0051]
Next, as shown in FIG. 2B, a second main gate electrode is etched to form a main gate electrode 24a having a desired shape. For example, by removing a part of the tapered portion of the main gate electrode 24a ', a main gate electrode 24a having a length in the channel direction shorter than the length of the main gate electrode 24a' in the channel direction is formed. Thereafter, in order to form the LDD region 26, a low dose (for example, 1 × 10 ^Thirteen atoms / cm ² 8 × 10 or more ^Thirteen atoms / cm ² In the following, the semiconductor layer is doped with an impurity such as phosphorus. Thus, the LDD region 26 is formed in a region of the semiconductor layer that overlaps with the main gate electrode 24a 'but does not overlap with the main gate electrode 24a. The preferable length of the LDD region 26 in the channel direction differs depending on the power supply voltage of the device. For example, when the power supply voltage is 5 V or less, if the length of the LDD region 16 in the channel direction is 0.3 μm or more and 0.5 μm or less, deterioration due to hot carriers is effectively prevented while suppressing a decrease in current driving force. can do. For the same reason, when the power supply voltage is more than 5 V and less than 10 V, the length of the LDD region in the channel direction is preferably 0.5 μm or more and 1 μm or less. It is preferable that the length in the channel direction of 26 be 1 μm or more and 2 μm or less. A portion of the semiconductor layer overlapping with the main gate electrode 24a becomes a channel region. The length of the channel region in the channel direction (channel length) is appropriately selected depending on the power supply voltage, the circuit configuration, and the like. For example, when the power supply voltage is 8 V, the length of the LDD region 26 in the channel direction is preferably 0.5 μm or more and 1 μm or less, and the channel length is preferably 2 μm or more. On the other hand, in order to cope with the shortening of the channel, the channel length is preferably set to 4 μm or less. The main gate electrode 24a has a single-layer structure made of a W film in the present embodiment, but may have a multi-layer structure. Since the etching of the main gate electrode 24a may be performed a plurality of times so that the LDD region 26 can be formed in a self-aligned manner, the etching is performed twice in the present embodiment, but may be performed three or more times. Further, the main gate electrode 24a 'having a substantially rectangular cross section can be formed by the first main gate electrode etching. In this case, isotropic etching such as wet etching may be performed as the second main gate electrode etching to form the main gate electrode 24a having a shorter length in the channel direction than the main gate electrode 24a '.
[0052]
Next, as shown in FIGS. 2C and 2D, the first and second interlayer insulating films 27a and 27b are formed by the same method as in the first embodiment, and the second interlayer insulating film 27b is formed. A source / drain electrode 29 and a sub-gate electrode 24b are formed from the conductive film provided above. The sub-gate electrode 24b is formed so as to overlap at least a part of the LDD region 26 that does not overlap with the main gate electrode 24a. When the length of the LDD region in the channel direction is 0.5 μm or more and 1 μm or less, the length in the channel direction (overlap dimension) of the portion where the sub-gate electrode 24 b and the LDD region 26 overlap is 0.5 μm or more and 1 μm or less. It is preferable that
[0053]
After the LDD region 26 is formed on both sides (source side and drain side) of the channel region, a photolithography process and a high dose phosphorus doping process are performed to increase the phosphorus concentration of the LDD region 26 on the source side to increase the source concentration. It can also be changed to the area 25. Thus, a TFT in which the LDD region 26 is formed only on the drain side can be manufactured.
[0054]
In this embodiment, since the LDD region 26 of the thin film transistor 2 is manufactured by a self-alignment method, it is not necessary to consider the mask alignment accuracy in the photolithography process. Therefore, the length of the LDD region 26 in the channel direction can be shorter than the length of the LDD region 16 in the channel direction (for example, 2 μm) in the first embodiment. As a result, the ratio of the load resistance of the LDD region 16 can be reduced, leading to an increase in current driving force. Also, by reducing the length of the LDD region 26 in the channel direction, the length of the channel region (channel length) can be reduced. It is advantageous to shorten the channel length because the operation speed of the TFT can be improved.
[0055]
(Third embodiment)
Next, a third embodiment of the device according to the present invention will be described. In the present embodiment, the main gate electrode 34a has a two-layer structure including a main gate electrode lower layer 34c and a main gate electrode upper layer 34d.
[0056]
First, a semiconductor layer and a gate insulating film 33 are formed on a substrate 31 by a process similar to that of the first embodiment. After forming the gate insulating film 33, an electrode film lower layer 34c 'is formed using, for example, a TaN film. An upper electrode film layer is formed on the lower electrode film layer 34c 'using, for example, a W film. Next, after forming a photoresist, the lower layer of the electrode film is etched to form an upper layer 34d of the main gate electrode film which covers a portion to be a channel region of the semiconductor layer. Using the upper electrode film layer 34d as a mask, impurity (for example, phosphorus) doping is performed at a low dose to form the LDD region 36 in the semiconductor layer (FIG. 3A). For example, when the thickness of the gate insulating film 33 is 100 nm and the thickness of the electrode film lower layer 34 c ′ is 20 nm or more and 40 nm or less, the phosphorous doping is performed at 90 kV and 5 × 10 5 ^Thirteen atoms / cm ² 5 × 10 or more ¹⁴ atoms / cm ² The following dose can be used. When phosphorus doping is performed under the above conditions, an LDD region 36 having excellent hot carrier deterioration resistance can be formed.
[0057]
Next, as shown in FIG. 3B, a side wall 50 is formed on the side wall of the main gate electrode upper layer 34d. The sidewall 50 may be an insulating film or a conductive film. The sidewall 50 is made of, for example, SiO ₂ After the film is formed by the CVD method, ₂ It can be formed by etching back the film. Thereafter, using the upper layer 34d of the main gate electrode and the sidewalls 50 as a mask, the lower layer 34c 'of the electrode film is etched to form the lower layer 34c of the main gate electrode. The length of the obtained main gate electrode lower layer 34c in the channel direction becomes larger than the length of the main gate electrode upper layer 34d in the channel direction. The difference between these lengths is determined by the width of the sidewall 50. For example, when the thickness of the main gate electrode upper layer 34d made of a W film is 300 nm, a 300 nm thick SiO ₂ When the film is formed, a sidewall 50 having a width of about 0.25 μm is formed. Therefore, the main gate electrode lower layer 34c is longer by 0.25 μm at both ends than the main gate electrode upper layer 34d. This length is the overlapping dimension of the main gate electrode 34a (main gate electrode lower layer 34c) and the LDD region 36.
[0058]
Thereafter, as shown in FIG. 3C, a photoresist 30 is formed, and a high dose (for example, 1 × 10 ^Fifteen atoms / cm ² More than 1 × 10 ^Fifteen atoms / cm ² In the following, doping of impurities (for example, phosphorus) is performed. As a result, the region of the semiconductor layer overlapping the photoresist 30 remains as the LDD region 36 or the channel region, and the source region and the drain region 35 are formed in the region not overlapping the photoresist 30. In the present embodiment, the LDD regions 36 that do not overlap the main gate electrode lower layer 34c are formed on both the source side and the drain side, but may be formed only on one side.
[0059]
Next, as shown in FIG. 3D and FIG. 3E, similarly to the first embodiment, after forming the first and second interlayer insulating films 37a and 37b, on the second interlayer insulating film 37b. The source and drain electrodes 39 and the sub-gate electrode 34b are formed from the conductive film formed as described above. The sub-gate electrode 34b is formed so as to overlap at least a part of the LDD region 36 which does not overlap with the main gate electrode 34a.
[0060]
In the present embodiment, it is preferable that the main gate electrode 34a overlaps from 0.2 μm to 0.5 μm from the channel end of the LDD region 36 in the channel direction. If it is 0.2 μm or more, more excellent hot carrier deterioration resistance can be obtained, and if it is 0.5 μm or less, the gate / drain overlap capacitance and off-leak current can be further reduced. For example, when the length of the LDD region 36 in the channel direction is 0.5 μm or more and 2 μm or less, the overlap dimension between the main gate electrode 34 a and the LDD region 36 is preferably 0.1 μm or more and 0.5 μm or less, more preferably. Is 0.2 μm or more and 0.3 μm or less. Note that the area or the size of the overlapping portion of the main gate electrode 34a and the LDD region 36 can be adjusted by the width 30 of the sidewall as described above. On the other hand, it is desirable that the sub-gate electrode 34d overlaps with an area of not less than ４ and not more than ／ of the area of the LDD region 36 as in the other embodiments. In other words, it is desirable that the area of not less than 1/4 and not more than 4/5 of the area of the LDD region 36 is overlapped by the main gate electrode 34a or the sub-gate electrode 34b.
[0061]
Note that the device of the present embodiment may further include the thin film transistor 3 and another thin film transistor different from the thin film transistor 3 on the same support (substrate 31). For example, another thin film transistor may have the same structure as the thin film transistor 3, except that the main gate electrode lower layer 34c substantially overlaps the entire LDD region 36. In this case, as shown in FIG. 3C, of the plurality of main gate electrodes 34a provided on the same substrate, the main gate electrode 34a constituting the thin film transistor 3 is selectively covered with the photoresist 30, thereby achieving the same as the above. In this process, the thin film transistor 2 and another thin film transistor can be formed on the same substrate.
[0062]
As described above, in the device including the thin film transistor of the present embodiment, the main gate electrode 34a (the main gate electrode lower layer 34c) partially overlaps the LDD region 36. Can be produced. In addition, since the sub-gate electrode 34b overlaps at least a part of the LDD region 36 which does not overlap with the main gate electrode 34a, a TFT having a structure in which only the main gate electrode overlaps the LDD region (conventional TFT). In this case, the off-leak current and the gate / drain overlap capacitance, which are problems in the GOLD structure TFT, can be reduced.
[0063]
Further, according to the method for manufacturing a device including the thin film transistor of the present embodiment, it is possible to easily form different types of thin film transistors at desired positions according to a power supply voltage to be used and a circuit to be used.
[0064]
(Fourth embodiment)
Next, a fourth embodiment of the device according to the present invention will be described.
[0065]
As shown in FIGS. 4A and 4B, after the main gate electrode 44a is formed on the gate insulating film 43 provided on the semiconductor layer by the same method as in the first embodiment, The LDD region 46 and the source and drain regions 45 are formed in the semiconductor layer. Next, as shown in FIG. 4C, a first interlayer insulating film 47a is formed on the main gate electrode 44a, and a second interlayer insulating film 47b is formed thereon. Thereafter, a portion including a region where the sub-gate electrode 44b is formed in the second interlayer insulating film 47b is selectively removed by, for example, a photolithography method and an etching method. For example, a first interlayer insulating film 47a is formed using a SiN film, ₂ If the second interlayer insulating film 47b is formed using a film, only the second interlayer insulating film 47b can be relatively easily removed. The interlayer insulating film 47 may be formed so that the thickness of the region where the sub-gate electrode 44b is formed in the interlayer insulating film 47 is smaller than the thickness of the other regions. Multiple layers may be used.
[0066]
Next, as shown in FIGS. 4D and 4E, the first interlayer insulating film 47a and the second interlayer insulating film 47b are contacted to reach the source and drain regions 45 and the main gate electrode 44a, respectively. Holes 48s, 48d and 48g are formed. Subsequently, as in the other embodiments, a conductive film is formed on the interlayer insulating film 47 (including the inside of the contact hole 48), and the source and drain electrodes 49 and the sub-gate electrode 44b are formed from the conductive film. I do. The sub-gate electrode 44b is formed so as to overlap at least a part of the LDD region 46.
[0067]
In the present embodiment, the thickness d1 of the interlayer insulating film 47 sandwiched between the sub-gate electrode 44b and the LDD region 46 is larger than the thickness d2 of the interlayer insulating film 47 sandwiched between the source or drain electrode 49 and the semiconductor layer. Is also small. In the present embodiment, the relative dielectric constant of the first interlayer insulating film 47a is SiO. ₂ Since the SiN film, which is about twice as large as the film, is used, the effect of inducing carriers in the LDD region 46 by the sub-gate electrode 44b is particularly large. As a result, it is possible to obtain a current driving force as high as that of a TFT having a GOLD structure. On the other hand, since the sub-gate electrode 44b and the LDD region 46 overlap with each other not only through the gate insulating film 43 but also through the insulating film 44a, the distance between the gate and the drain is large. Therefore, the overlap capacitance with the gate / drain, which has been a problem in the GOLD structure TFT, can be reduced, and the off leak current can be reduced. For example, if the overlapping dimension between the sub-gate electrode 44b of the thin film transistor 4 and the LDD region 46 is the same as the overlapping dimension between the gate electrode of the TFT having the conventional GOLD structure and the LDD region, the gate insulating film 43 is set to 100 nm and the first interlayer is formed. When the thickness of the insulating film 47a is 300 nm, the overlapping capacity of the thin film transistor 4 is about 40% of the overlapping capacity of the TFT having the conventional GOLD structure. The thickness d1 of the interlayer insulating film 47 is preferably 200 nm or more and 500 nm or less. When the thickness d1 is within this range, the current driving force can be increased while suppressing the gate / drain overlap capacitance.
[0068]
As described above, in the thin film transistor 4 in the device of the present embodiment, the thickness d1 of the interlayer insulating film 47 sandwiched between the LDD region 46 and the sub-gate electrode 44b is sandwiched between the source or drain electrode 49 and the semiconductor layer. The thickness d2 of the interlayer insulating film 47 is smaller than the thickness d2. Therefore, the current driving force can be improved as compared with a thin film transistor having a structure in which the thickness d1 and the thickness d2 of the interlayer insulating film 47 are equal. In the present embodiment, the thin film transistor 4 is manufactured by reducing the thickness d1 of the interlayer insulating film of the thin film transistor 1 of the first embodiment. However, the thin film transistor 2 of the second and third embodiments and 3, it is also possible to apply a structure in which the thickness d1 of the interlayer insulating film is reduced.
[0069]
【The invention's effect】
As described above, the TFT in the device of the present invention has better hot carrier deterioration resistance and current driving power than the TFT having the conventional LDD structure. Further, as compared with a TFT having a conventional GOLD structure, an off-leak current can be suppressed and a gate / drain overlap capacitance can be reduced. Further, a plurality of thin film transistors having different structures can be formed over the same substrate depending on a power supply voltage and a circuit configuration of the device, so that circuit characteristics can be improved. Therefore, according to the present invention, it is possible to provide a device including a thin film transistor, such as a liquid crystal display device and an organic EL display device, which have higher performance and higher long-term reliability than conventional devices.
[0070]
Further, according to the present invention, it is possible to provide a simple method for manufacturing a device including the above-described thin film transistor without increasing the number of steps.
[Brief description of the drawings]
FIGS. 1A to 1D are schematic cross-sectional views illustrating a structure and a manufacturing method of a thin film transistor according to a first embodiment of the present invention.
FIGS. 2A to 2D are schematic cross-sectional views illustrating a structure and a manufacturing method of a thin film transistor according to a second embodiment of the present invention.
FIGS. 3A to 3E are schematic cross-sectional views illustrating a structure and a manufacturing method of a thin film transistor according to a third embodiment of the present invention.
FIGS. 4A to 4E are schematic cross-sectional views illustrating a structure and a manufacturing method of a thin film transistor according to a fourth embodiment of the present invention.
[Explanation of symbols]
1,2,3,4 thin film transistor
10, 20, 30, 40 photoresist
11, 21, 31, 41 substrate
12, 22, 32, 42 channel area
13, 23, 33, 43 Gate insulating film
14a, 24a, 34a, 44a Main gate electrode
14b, 24b, 34b, 44b Sub-gate electrode
34c Lower layer of main gate electrode
34d Main gate electrode upper layer
15, 25, 35, 45 source region or drain region
16, 26, 36, 46 LDD region
17a, 27a, 37a, 47a First interlayer insulating film
17b, 27b, 37b, 47b Second interlayer insulating film
18, 28, 38, 48 Contact hole
19, 29, 39, 49 Source electrode or drain electrode
50 Sidewall

Claims (13)

An apparatus including a plurality of thin film transistors, at least one of the plurality of thin film transistors,
A semiconductor layer having a channel region, a source region, and a drain region, the semiconductor layer being sandwiched between the channel region and at least one of the source region and the drain region, and having an impurity concentration lower than an impurity concentration of the source region and the drain region. A semiconductor layer having a low concentration impurity region having
A first insulating layer formed on the semiconductor layer;
A first gate electrode provided on the first insulating layer;
A second insulating layer formed on the first gate electrode;
A source electrode and a drain electrode formed of a conductive layer provided over the second insulating layer and electrically connected to the source region and the drain region, respectively;
A second gate electrode formed from a conductive layer provided over the second insulating layer and electrically connected to the first gate electrode;
The device, wherein at least a part of a region of the second gate electrode that does not overlap with the first gate electrode overlaps at least a part of the low-concentration impurity region. The device according to claim 1, wherein the low-concentration impurity region is formed in a self-aligned manner with respect to the first gate electrode. The area of a portion of the second gate electrode that does not overlap with the first gate electrode and the low-concentration impurity region overlaps with each other, and is equal to or more than ４ of the area of the low-concentration impurity region. Apparatus according to claim 1 or 2, wherein the number is 5 or less. The thickness of the portion of the second insulating layer where the second gate electrode is provided is larger than the thickness of the portion of the second insulating layer where the source electrode or the drain electrode is provided. Apparatus according to any of claims 1 to 3, which is small. The plurality of thin film transistors include another thin film transistor different from the at least one thin film transistor, wherein the at least one thin film transistor and the other thin film transistor are formed on the same support, and a gate of the other thin film transistor is formed. The device according to claim 1, wherein an electrode is provided below the second insulating layer of the at least one thin film transistor. A method for manufacturing a device including a thin film transistor,
(A) forming a first insulating layer on the semiconductor layer;
(B) providing a first gate electrode on the first insulating layer;
(C) forming a source region, a drain region, and a low-concentration impurity region having an impurity concentration lower than those of the source region and the drain region in the semiconductor layer;
(D) forming a second insulating layer on the first gate electrode;
(E) forming, in the second insulating layer, first, second, and third contact holes reaching respective surfaces of the first gate electrode, the source region, and the drain region;
(F) providing a conductive layer inside the first, second, and third contact holes and on the second insulating layer;
(G) forming, from the conductive layer, a source electrode and a drain electrode electrically connected to the source region and the drain region, respectively, and a second gate electrode electrically connected to the first gate electrode. Forming at least a part of the second gate electrode that does not overlap with the first gate electrode so as to overlap at least part of the low-concentration impurity region. Production method. 7. The method according to claim 6, wherein the step (c) includes a step of forming the low-concentration impurity region by doping the semiconductor layer with an impurity using the first gate electrode as a mask. The step (c) comprises:
(C-1) doping the semiconductor layer with an impurity at a first dose using the first gate electrode as a mask;
(C-2) a step of covering a part of the first insulating layer with a photoresist and doping the semiconductor layer with an impurity at a second dose using the first gate electrode and the photoresist as a mask; The method according to claim 7, wherein the second dose is higher than the first dose. The step (b) includes a step of forming a first electrode layer constituting a part of the first gate electrode, and a step of forming another part of the first gate electrode on the first electrode layer. Forming a second electrode layer to be formed, wherein the second electrode layer has a width in a channel direction smaller than a width of the first electrode layer in a channel direction. The manufacturing method according to claim 8, wherein -1) includes doping an impurity in a region of the semiconductor layer covered by the first electrode layer, the region not covered by the second electrode layer. The step (b) is a step of providing a first gate electrode having a first shape on the semiconductor layer,
The step (c) comprises:
(C1) doping the semiconductor layer with an impurity at a third dose using the first gate electrode having the first shape as a mask;
(C2) forming a first gate electrode having a second shape by etching the first gate electrode having the first shape, wherein the first gate electrode having the second shape is formed by etching the first gate electrode having the second shape; A step in which the width in the channel direction is smaller than the width in the channel direction of the first gate electrode having the first shape;
(C3) doping the semiconductor layer with an impurity at a fourth dose using the first gate electrode having the second shape as a mask, wherein the fourth dose is the third dose; The method according to claim 6, comprising lower steps. The step (d) includes:
(D-1) forming a first layer constituting a part of the second insulating layer on the first gate electrode;
(D-2) forming the second layer constituting another part of the second insulating layer on the first layer. Production method. In the step (d-2), the second layer is formed so as to cover a part of the first layer, and in the step (g), the source electrode and the drain electrode are formed of the second and third electrodes. The gate electrode is formed from the inside of the contact hole and the conductive layer formed on the second layer, and the gate electrode is formed from the inside of the first contact hole and the conductive layer formed on the first layer. The production method according to claim 11. A method for manufacturing a device including a first thin film transistor and a second thin film transistor,
(A) forming a first insulating layer on a semiconductor layer in each of a first transistor forming region in which the first thin film transistor is formed and a second transistor forming region in which the second thin film transistor is formed; When,
(B) providing a first gate electrode on the first insulating layer;
(C) forming a source region, a drain region, and a low-concentration impurity region having an impurity concentration lower than those of the source region and the drain region in the semiconductor layer;
(D) forming a second insulating layer on the first gate electrode;
(E) In the first transistor formation region, first, second, and third contact holes reaching respective surfaces of the first gate electrode, the source region, and the drain region are formed in the second insulating layer. Forming second and third contact holes respectively reaching the respective surfaces of the source region and the drain region in the second insulating layer in the second transistor formation region,
(F) providing a conductive layer inside the first, second, and third contact holes and on the second insulating layer;
(G1) in the first transistor formation region, from the conductive layer, a source electrode and a drain electrode electrically connected to the source region and the drain region, respectively, and an electrical connection to the first gate electrode. Forming a second gate electrode, wherein at least part of a region of the second gate electrode that does not overlap with the first gate electrode is at least part of the low-concentration impurity region. (G2) forming a source electrode and a drain electrode electrically connected to the source region and the drain region, respectively, from the conductive layer in the second transistor formation region. ,Production method.

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