JP2004235209A - IC wafer and method of manufacturing flip-chip type IC using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an IC wafer where an unnecessary solder bump formed on the IC wafer can easily be removed and to provide a manufacturing method of a flip-chip IC using the wafer. <P>SOLUTION: In the IC wafer, a plurality of barrier metal layers 3 are formed on an upper face of a semiconductor substrate 1, and a passivation layer 4 is bonded to a non-forming region of the barrier metal layer 3. An alignment mark 5 for positioning a printing mask is arranged on the semiconductor substrate 1. The alignment mark 5 is covered with the passivation layer 4. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an IC wafer provided with a plurality of barrier metal layers to which a printing paste is applied, and a method for manufacturing a flip-chip IC using the IC wafer.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, an IC is face-down bonded to an upper surface of a circuit board having circuit wiring, that is, the IC is mounted on the circuit board in such a manner that the surface on which the integrated circuit of the IC is formed faces the circuit board. That is being done.
[0003]
An IC used for such face-down bonding is called a flip-chip type IC, and its terminal is generally connected to circuit wiring on a circuit board via solder.
[0004]
As such a conventional flip-chip type IC, for example, a circuit pattern made of Al or a semiconductor element (not shown) is attached on the upper surface of a silicon substrate on which an insulating film (not shown) is attached, and Ni is placed on the circuit pattern. Structure in which a plurality of barrier metal layers made of a metal layer and an Au layer are applied, and a passivation layer made of silicon nitride or the like is applied to a region where no barrier metal layer is formed, and a substantially spherical solder bump is formed on the barrier metal layer. When such a flip-chip type IC is mounted on a circuit board, the flip-chip type IC is mounted on the circuit board such that the solder bumps of the flip-chip type IC face the corresponding circuit wiring on the circuit board. The flip-chip barrier metal layer is placed on a substrate and then heated and melted at a high temperature. It is soldered to the circuit wiring on the circuit board.
[0005]
The solder bump provided on the flip-chip type IC is usually formed by the following method. That is,
A circuit pattern and a semiconductor element (not shown) are formed on the upper surface of a semiconductor substrate made of single crystal silicon or the like on which an insulating film such as SiO ₂ is deposited, and a barrier metal layer is formed on the circuit pattern. Prepare an IC wafer having a passivation layer formed in a formation region, and a print mask having an opening corresponding to the barrier metal layer,
Next, the printing mask is disposed on the IC wafer such that the opening is located directly above the barrier metal layer on the IC wafer,
Next, after supplying the solder paste on the print mask, the supplied solder paste is printed and applied on the barrier metal layer through the opening,
Finally, a substantially spherical solder bump is formed on the barrier metal layer by reflowing the solder paste applied on the barrier metal layer.
[0006]
In order to accurately form solder bumps on the barrier metal layer by such a method, it is necessary to align the print mask with the IC wafer with high precision. An alignment mark for aligning the print mask is provided thereon, and a through hole corresponding to the alignment mark is provided in the print mask, and the alignment between the IC wafer and the print mask is performed with reference to the alignment mark and the through hole. I'm trying to do it.
[0007]
The alignment mark is formed of the same material as the circuit pattern, that is, a metal material such as Al, and the surface thereof is generally exposed (see Patent Documents 1 and 2).
[0008]
[Patent Document 1]
JP 2002-29034 A [Patent Document 2]
JP-A-9-323401
[Problems to be solved by the invention]
However, when the print mask and the IC wafer are aligned with respect to the through hole and the alignment mark, and then the solder paste supplied on the print mask is printed and applied on the IC wafer, a barrier metal layer is required. Solder paste adheres to the alignment mark used for alignment as well as the top through the through hole. When the solder paste printed and applied on the IC wafer is reflowed, it is added to the barrier metal layer and aligned. Unnecessary solder bumps are also formed on the marks. Since the alignment marks on which such unnecessary solder bumps are formed are made of a metal material such as Al having a relatively strong adhesive force to the solder, the unnecessary solder bumps can be removed individually by a solder removing device or the like. It must be removed, and the manufacturing process becomes complicated depending on the number of unnecessary solder bumps, and the productivity of the flip-chip type IC may be significantly reduced.
[0010]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and has as its object to manufacture an IC wafer capable of easily removing extra solder bumps formed on an IC wafer and to manufacture a flip-chip type IC using the same. It is to provide a method.
[0011]
[Means for Solving the Problems]
The present invention relates to an IC wafer comprising a plurality of barrier metal layers formed on an upper surface of a semiconductor substrate and a passivation layer applied to a region where the barrier metal layers are not formed. The alignment mark is provided on a substrate, and the alignment mark is covered with the passivation layer.
[0012]
Further, the invention is characterized in that two or more alignment marks are provided.
[0013]
Further, the present invention is characterized in that the alignment mark has a smaller area than the barrier metal layer.
[0014]
Further, the present invention is characterized in that an upper surface of the semiconductor substrate is divided into an IC formation region and an IC non-formation region, and the alignment mark is formed in the IC non-formation region.
[0015]
Still further, according to the present invention, a print mask having a plurality of openings corresponding to the plurality of barrier metal layers and a through hole corresponding to the alignment mark is provided on the IC wafer. And a paste containing a flux is supplied to the upper surface of the print mask provided in the step 1 through the opening and the through-hole. Step 2 of applying on the barrier metal layer and the alignment mark; Step 3 of forming a bump on the barrier metal layer and the alignment mark by reflowing the paste applied in Step 2; Cleaning the flux adhering to the obtained bumps to remove the bumps on the alignment marks. Than it is.
[0016]
According to the present invention, in an IC wafer formed by forming a plurality of barrier metal layers on an upper surface of a semiconductor substrate and applying a passivation layer to a region where the barrier metal layer is not formed, a print mask is positioned on the semiconductor substrate. Since the alignment mark is provided and the alignment mark is covered with the passivation layer, a print mask having a plurality of openings corresponding to the barrier metal layer and through holes corresponding to the alignment mark is formed on the alignment mark. When the bumps are formed by printing and applying a paste containing a flux on the IC wafer using the print mask on the IC wafer, the unnecessary bumps formed on the alignment marks may be formed. It becomes directly deposited on the passivation layer having poor wettability. The adhesion to the wafer can be significantly reduced. Therefore, when cleaning the flux adhering to the bump surface, unnecessary bumps on the alignment mark are easily removed together with the flux, thereby simplifying the manufacturing process of the flip-chip type IC and improving the productivity of the flip-chip type IC. Can be improved.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a plan view of an IC wafer according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line XX of the IC wafer shown in FIG. 1, and the IC wafer shown in FIG. 1 has a structure in which a circuit pattern 2, a barrier metal layer 3, a passivation layer 4, an alignment mark 5, and the like are provided on the upper surface.
[0018]
The semiconductor substrate 1 is formed in a substantially circular shape from a single crystal semiconductor such as single crystal silicon having an insulating film 1a made of an insulating material such as SiO _{2 on} the surface, and the upper surface thereof has an IC forming region A and an IC non-forming region. It is divided into an area B.
[0019]
The semiconductor substrate 1 has a semiconductor element or circuit pattern 2 (not shown), a barrier metal layer 3 and a passivation layer 4 attached to an IC formation region A on the upper surface thereof, and a passivation layer 4 and an alignment mark 5 attached to an IC non-formation region B. And functions as a supporting base material for supporting them. In the case where such a semiconductor substrate 1 is made of the above-described single crystal silicon, for example, an ingot made of single crystal silicon is formed by adopting a conventionally known Czochralski method (pulling method), and This is sliced into a plate shape using a diamond cutter or the like, and the surface is polished to obtain a plate having a predetermined thickness. Thereafter, a conventionally known thermal oxidation method or the like is applied to the plate, It is manufactured by oxidizing the plate body surface to a predetermined depth region (1.5 μm to 4.5 μm) from the surface.
[0020]
The circuit pattern 2 attached to the IC formation region A of the semiconductor substrate 1 is formed in a predetermined pattern from a metal material such as Al or Cu. It functions as a power supply wiring for supplying electric power and electric signals.
[0021]
Such a circuit pattern 2 is formed to a predetermined thickness (0.5 μm to 1.5 μm) by employing a conventionally known thin film forming technique, specifically, sputtering, photolithography, etching, or the like. You.
[0022]
Further, the barrier metal layer 3 provided on the circuit pattern 2 has, for example, a three-layer structure in which zinc (Zn), nickel (Ni), and gold (Au) are sequentially stacked from the semiconductor substrate 1 side. The thickness of the entire barrier metal layer is set to, for example, 0.5 μm to 7.0 μm.
[0023]
When the flip-chip type IC obtained by processing the IC wafer according to the present invention is mounted on a circuit board, when the solder bumps provided on the barrier metal layer 3 are melted, The effect of effectively preventing "erosion" of the aluminum or the like forming the circuit pattern 2 due to the solder formed is provided.
[0024]
Such a barrier metal layer 3 is formed on a circuit pattern 2 exposed in an opening of the passivation layer 4, that is, in a region where the passivation layer 4 does not exist, after a passivation layer 4 described later is formed. By adopting plating or the like and sequentially depositing Zn, Ni, and Au, the whole is formed to have a substantially columnar shape.
[0025]
Of the three layers constituting the barrier metal layer 3, the lowermost Zn layer is formed by subjecting a part of the Ni layer to a substitution reaction when the Ni layer is formed by conventionally known electroless plating or the like. The thickness is set to 0.01 μm to 0.05 μm, and the Ni layer serving as the intermediate layer is used to improve the wettability of the solder to the barrier metal layer 3. And the thickness thereof is set to 0.47 μm to 6.85 μm. The Au layer serving as the uppermost layer is for effectively preventing the oxidative corrosion of the Ni layer, and the thickness thereof is 0.02 μm to 0.1 μm. Is set to
[0026]
On the other hand, the alignment mark 5 attached to the IC non-formation region B of the semiconductor substrate 1 is formed of a material similar to the circuit pattern 2, for example, a metal material such as Al or Cu, for example, in a square shape. Are set to two or more (two in the present embodiment).
[0027]
The alignment mark 5 functions as a mark for aligning the two with high accuracy when a print mask is provided on the IC wafer in order to print and apply the solder paste on the barrier metal layer 3.
[0028]
The alignment marks 5 can be formed at the same time as the circuit pattern 2 by 0.5 .mu.m to 1. .mu.m by employing the same method as the circuit pattern 2 described above, that is, by employing a thin film forming technique such as sputtering, photolithography, and etching. It is formed to a thickness of 5 μm.
[0029]
On the upper surface of the semiconductor substrate 1 described above, a passivation layer 4 is applied to a region where the barrier metal layer 3 is not formed, and the passivation layer 4 covers the circuit pattern 2 and the alignment mark 5 in common. .
[0030]
The passivation layer 4 is formed of an electrically insulating material having an excellent sealing property such as silicon nitride (Si ₃ N ₄ ) or silicon oxide (SiO ₂ ), and has the above-described semiconductor element, circuit pattern 2 and alignment. The mark 5 is effectively shielded from the atmosphere, thereby effectively preventing the mark 5 from being corroded by contact with moisture or the like contained in the atmosphere. Acts to prevent the adhesion of
[0031]
Such a passivation layer 4 is formed by applying the above-mentioned electrically insulating material to the semiconductor substrate 1 on which the circuit pattern 2 and the like are provided by employing a conventionally known thin film forming technique, for example, a CVD method or a sputtering method. It is formed to a thickness of 5 μm to 1.5 μm, and then processed into a predetermined pattern by a conventionally well-known photolithography and etching technique, that is, by forming an opening at a position where the barrier metal layer 3 is formed. Is done.
[0032]
Next, a method of manufacturing a flip-chip type IC using the above-described IC wafer will be described in detail with reference to FIG. FIG. 3 is a sectional view of each step for explaining a method of manufacturing a flip-chip type IC using the IC wafer of FIG. 1, wherein 6 is a metal sheet, 7 is an opening, 8 is a through hole, and 9 'is a paste. 9a and 9b are solder bumps as bumps.
First, the above-described IC wafer W and print mask M are prepared (FIG. 3A).
[0033]
The print mask M is formed by forming an opening 7 corresponding to the barrier metal layer 3 and a through hole 8 corresponding to the alignment mark 5 in a metal sheet 6 formed in a plate shape from a metal material such as an aluminum alloy or a Ni alloy. When the print mask M is made of a Ni alloy, the print mask M is manufactured, for example, by employing a conventionally known additive method.
Next, an IC wafer W is disposed immediately below the print mask M (FIG. 3B).
[0034]
In order to dispose the IC wafer W directly below the print mask M, for example, the IC wafer W is placed and fixed on a stage of a screen printing machine on which the print mask M is disposed, and the IC wafer W is placed just above the alignment mark 5. This is performed by aligning the IC wafer W such that the through hole 8 is positioned at a position, whereby the print mask M and the IC wafer W are aligned with high accuracy, and the opening 7 of the print mask M is aligned with the IC wafer W. It is located right above the barrier metal layer 3.
[0035]
Since the alignment mark 5 is provided in the IC non-formed area B of the semiconductor substrate 1 as described above, the alignment mark 5 is used when the print mask M and the IC wafer W are aligned. It becomes easy to recognize, and it is possible to effectively prevent troubles such as misalignment of the alignment mark 5 with the barrier metal layer 3.
[0036]
Further, since the alignment mark 5 has a shape different from the barrier metal layer 3 in a plan view, the alignment mark 5 can be more easily recognized at the time of alignment. It is possible to effectively prevent a trouble such as a mistake.
(3) Next, a solder paste 9 'is prepared, and the solder paste 9' is supplied onto the print mask M.
[0037]
As the solder paste 9 ', one obtained by adding and mixing a rosin-based flux to a large number of solder particles and adjusting the viscosity to a predetermined viscosity is suitably used.
(4) Next, the solder paste 9 ′ on the print mask M is moved in a predetermined direction while pressing the squeegee toward the IC mask M, so that the solder paste 9 ′ is formed in the opening 7 and the through hole of the print mask M. Printing and application are performed on the barrier metal layer 3 and the alignment mark 5 through the interface 8 (FIG. 3C).
[0038]
At this time, as described above, since the alignment mark 5 is provided in the IC non-formation region B, the solder paste 9 ′ applied on the alignment mark and the solder paste applied on the barrier metal layer are different. There is an advantage that they can be sufficiently separated from each other, so that they can be effectively prevented from contacting and short-circuiting.
(5) Next, by reflowing the applied solder paste 9 ', the solder particles contained in the solder paste 9' are melted to bond the solder particles to each other, and this is cooled as it is. Solder bumps 9a and 9b are formed on the barrier metal layer 3 and the alignment marks 5 (FIG. 3D).
[0039]
At this time, although the solder bumps 9a on the barrier metal layer 3 are firmly attached to the barrier metal layer 3 by the action of the Ni layer forming the barrier metal layer 3, unnecessary solder bumps on the alignment mark 5 are formed. Since 9b is formed on the alignment mark 5 via the passivation layer 4 having poor solder wettability, the adhesive force of the solder bump 9b to the passivation layer 4 can be significantly reduced. Therefore, the solder bump 9b on the alignment mark 5 is in a state of being attached to the IC wafer W with extremely weak strength by the action of the flux (not shown) attached to the solder bump itself.
[0040]
The reflow of the solder paste 9 'is performed at a temperature of, for example, 230C to 260C.
(6) Next, the solder adhering to the solder bumps 9a and 9b is washed to remove the solder bump 9b on the alignment mark 5 (FIG. 3E).
[0041]
The cleaning of the flux is performed by swinging the IC wafer up and down while immersing the IC wafer in a quasi-aqueous solvent, whereby the flux residue attached to the bumps is washed away. Therefore, the unnecessary solder bumps 9b that have been deposited on the alignment marks 5 by the action of the flux are significantly removed from the alignment marks 5 by the flux cleaning because the adhesion to the passivation layer 4 is greatly reduced. Become. This eliminates the need to individually remove unnecessary solder bumps 9b with a semiconductor sucking device or the like, thereby simplifying the manufacturing process of the flip-chip IC and improving the productivity of the flip-chip IC. It becomes.
(7) Finally, the IC wafer W is processed into a predetermined shape using a diamond saw or the like, whereby a flip-chip type IC is manufactured.
[0042]
When the obtained flip-chip type IC is mounted on a circuit board, the flip-chip type IC is mounted on the circuit board such that the solder bumps of the flip-chip type IC face the corresponding circuit wiring on the circuit board. Then, the barrier metal layer of the flip chip is soldered to the circuit wiring on the circuit board by heating and melting the solder bump at a high temperature.
[0043]
The present invention is not limited to the above-described embodiment, and various changes and improvements can be made without departing from the gist of the present invention.
[0044]
For example, in the above-described embodiment, if the area of the alignment mark 5 is set to be smaller than the area of the barrier metal layer 3, it is possible to perform positioning with much higher precision than using the barrier metal layer 3 as a reference for positioning. It becomes possible. Further, at this time, if the opening area of the through hole 8 of the print mask M is set smaller than the opening 7, the amount of the solder paste 9 'applied from the through hole 8 can be reduced, and the solder paste 9' Waste can be reduced.
[0045]
In the above-described embodiment, a “metal mask” having a plurality of openings in the metal sheet 6 is used as a print mask. However, instead of this, various resin materials such as a polyimide resin, a polyester resin, and a polyethylene resin are used. The present invention is applicable to a mask made of.
[0046]
Further, in the above-described embodiment, the solder bumps 9a are formed using the solder paste 9 ', but instead, silver bumps or other conductive bumps may be formed using another conductive paste such as a silver paste. It may be formed.
[0047]
Further, in the above-described embodiment, the alignment mark 5 is provided in the IC non-forming area B of the semiconductor substrate 1, but may be provided in the IC forming area A instead. In the case A, if a dummy IC or a TEG (test group) IC is provided in the formation region, it is possible to effectively prevent troubles such as misalignment of an alignment mark with a barrier metal layer during alignment. In addition, there is an advantage that a short circuit between the solder paste 9 'applied on the alignment mark and the solder paste applied on the barrier metal layer is effectively prevented.
[0048]
Furthermore, in the above-described embodiment, the barrier metal layer 3 has a three-layer structure of Zn, Ni, and Au. Alternatively, the barrier metal layer 3 may have a two-layer structure. For example, a structure in which Ni and Au are sequentially stacked is considered as an example.
[0049]
Further, in the above-described embodiment, the alignment mark 5 is formed in a square shape. Alternatively, the alignment mark may be formed in various shapes such as a triangular shape, a circular shape, and a cross shape.
[0050]
【The invention's effect】
According to the present invention, in an IC wafer formed by forming a plurality of barrier metal layers on an upper surface of a semiconductor substrate and applying a passivation layer to a region where the barrier metal layer is not formed, a print mask is positioned on the semiconductor substrate. Since the alignment mark is provided and the alignment mark is covered with the passivation layer, a print mask having a plurality of openings corresponding to the barrier metal layer and a through hole corresponding to the alignment mark is formed on the alignment mark. When the bumps are formed by printing and applying a paste containing a flux on the IC wafer using the print mask and forming the bumps on the IC wafer, unnecessary bumps formed on the alignment marks are formed. It becomes directly deposited on the passivation layer having poor wettability. The adhesion to the wafer can be significantly reduced. Therefore, when cleaning the flux adhering to the bump surface, unnecessary bumps on the alignment mark are easily removed together with the flux, thereby simplifying the manufacturing process of the flip-chip type IC and improving the productivity of the flip-chip type IC. Can be improved.
[Brief description of the drawings]
FIG. 1 is a plan view of an IC wafer according to an embodiment of the present invention.
FIG. 2 is a sectional view taken along line XX of the IC wafer shown in FIG.
3 (a) to 3 (e) are cross-sectional views of respective steps for explaining a method of manufacturing a flip-chip type IC using the IC wafer shown in FIG.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 semiconductor substrate 2 circuit pattern 3 barrier metal layer 4 passivation layer 5 alignment mark 6 metal sheet 7 opening 8 through hole 9 ′ ... Solder paste 9a, 9b ... Solder bump M ... Print mask W ... IC wafer A ... IC formation area B ... IC non-formation area

Claims (5)

In an IC wafer formed by forming a plurality of barrier metal layers on an upper surface of a semiconductor substrate and applying a passivation layer to a region where the barrier metal layer is not formed, an alignment mark for aligning a print mask is provided on the semiconductor substrate. And an alignment mark covered with the passivation layer. 2. The IC wafer according to claim 1, wherein two or more alignment marks are provided. 3. The IC wafer according to claim 1, wherein the alignment mark has a smaller area than a barrier metal layer. 4. The semiconductor substrate according to claim 1, wherein an upper surface of the semiconductor substrate is divided into an IC formation region and an IC non-formation region, and the alignment mark is formed in the IC non-formation region. 2. The IC wafer according to 1. 5. A print mask having a plurality of openings corresponding to the plurality of barrier metal layers and a through-hole corresponding to the alignment mark, on the IC wafer according to any one of claims 1 to 4, comprising: A step 1 of arranging the through holes so that their positions substantially coincide with each other;
Supplying a paste containing a flux to the upper surface of the print mask provided in the step 1 and applying the supplied paste onto the barrier metal layer and the alignment mark through the opening and the through hole; When,
A step 3 of forming bumps on the barrier metal layer and the alignment marks by reflowing the paste applied in the step 2;
A step of removing the bumps on the alignment marks by cleaning the flux adhered to the bumps obtained in the step (3).

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