JP2004228922A - Optical communication device - Google Patents

Abstract

Provided is an optical communication device that achieves high performance with a simple configuration.
A deskew circuit adjusts a timing shift between serial input data of a plurality of systems based on a reference signal, and receives a plurality of input data corresponding to the plurality of systems, the timing of which is adjusted by a multiplexer, in parallel. The signal is converted into a serial signal to be transmitted to the transmission line, and the deskew circuit and the multiplexer are configured as a single sealed semiconductor device.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an optical communication device, and relates to a technology that is effective when used in an electrical circuit technology used for optical communication.
[0002]
[Prior art]
With an increase in the speed of optical communication, an improvement in the data transfer rate between an LSI that performs electrical signal processing and an optical module is also required. Japanese Patent Application Laid-Open No. 2002-208896 discloses a method of transferring a high-speed serial signal in parallel because an electric transmission unit is slower than light. Also, Serdes Framer Interface Level-5 (SFI-5) has been proposed as a standard that defines a parallel transfer method in an electronic circuit.
[0003]
[Patent Document 1]
JP-A-2002-208896
[Non-patent document 1]
Serdes Framer Interface Level-5 (SFI-5)
[0004]
[Problems to be solved by the invention]
[0005]
As a problem when transferring a high-speed serial signal in parallel, a phase shift occurs between the signals due to a difference in characteristics of a transmission path or the like. In a device that does not allow a phase shift between signals as disclosed in Japanese Patent Application Laid-Open No. 2002-208896, the data transfer rate between optical modules is limited by a signal transmission speed that does not allow a phase shift on the electronic circuit side. On the other hand, in the SFI-5 standard, the data transfer rate between the optical modules is not limited by the signal transmission speed on the electronic circuit side in order to allow and correct the phase shift, so that the data transfer rate is improved. Will be possible.
[0006]
In the SFI-5 standard as described above, in order to correct a phase shift, a deskew signal including a signal extracted from a part of each parallel data is defined in addition to signal parallel data. The phase difference is corrected by detecting the phase difference of the parallel data. The inventor of the present application requires a relatively large circuit scale such as a shift register and a barrel shifter for a circuit for correcting the above-described phase shift (hereinafter, referred to as a deskew circuit). A circuit that forms a high-speed serial signal transmitted to the optical transmission line is a high-speed circuit using high-speed elements such as bipolar transistors. These low-speed circuits and high-speed circuits are formed by separate ICs and connected. Thought about doing.
[0007]
However, when the low-speed circuit and the high-speed circuit are configured as separate ICs and connected on a mounting board, a signal whose phase shift has been corrected in the low-speed circuit is transmitted to the high-speed circuit through a signal transmission path on the mounting board. As a result, a problem has been noticed that a phase shift may be caused again in the connection path between the ICs. Therefore, as the output circuit of the low-speed circuit, a high-speed circuit that does not cause a timing shift is used, so that the current consumption increases, and the mounting board transmits the output signal with high quality. Expensive equipment with high performance wiring means is required.
[0008]
An object of the present invention is to provide an optical communication device that has achieved high performance with a simple configuration. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0009]
[Means for Solving the Problems]
The outline of a representative one of the inventions disclosed in the present application will be briefly described as follows. The timing shift between serial input data of a plurality of systems is adjusted by a deskew circuit on the basis of a reference signal, and a plurality of input data corresponding to the plurality of systems, the timing of which is adjusted by a multiplexer, is received in parallel to a photoelectric transmission line. The signal is converted into a serial signal to be provided, and the deskew circuit and the multiplexer are used as one sealed semiconductor device.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 13 is a schematic diagram showing one embodiment of a high-speed optical transmission system to which the present invention is applied. In the signal processing receiving LSI on the receiving side, an optical signal having a transfer rate A (eg, A = 40) Gbps is input to the optical module on the receiving side through an optical transmission line. In the optical module, the transfer rate is divided into K parallel data of A / K (eg, 2.5 when k = 16) Gbps. In this optical module, a deskew signal RD including data obtained by extracting a part of each parallel data in addition to the parallel data R0 to Rk is output and input to the signal processing LSI on the receiving side. The data transfer between the signal processing LSI and the optical module on the transmission side is the same as described above. In the optical module on the transmitting side, the deskew signal RD and R0 to Rk are converted into serial data and transmitted to the optical transmission line in the form of an optical signal, contrary to the receiving side.
[0011]
FIG. 1 shows a configuration diagram of an embodiment of a signal processing device on the transmission side used in an optical communication device according to the present invention. The signal processing device on the transmission side is configured such that the SFI-5 adapter and the multiplexer MUX are integrally sealed as one module. The internal SFI-5 adapter includes an input / output circuit and a deskew circuit, and is combined with a multiplexer MUX. That is, the deskew circuit of the SFI-5 adapter corrects a phase shift in the signal processing LSI and a signal path from the signal processing LSI to the optical module using the deskew signal RD, and converts the phase shift into a k-fold signal which is converted into an optical signal by the multiplexer MUX. (16 times) high-speed serial data.
[0012]
FIG. 2 shows a configuration diagram of an embodiment of a signal processing device on the receiving side used in the optical communication device according to the present invention. The signal processing device on the receiving side also has a form in which the SFI-5 adapter and the demultiplexer DMUX are integrally sealed as one module. The internal demultiplexer DMUX converts high-speed serial data corresponding to the optical signal into a relatively slow signal of 1 / k (1/16), contrary to the transmitting side. The parallel data is received, a deskew signal RD is generated therefrom, and a total of 17 parallel data are output in addition to the above 16 parallel data without correcting the phase shift in the signal path .
[0013]
Although not particularly limited, in this embodiment, the SFI-5 adapter has a deskew circuit for performing the phase correction and a deskew signal generation circuit (DSC-G) for forming the deskew signal RD, and is used on the transmission or reception circuit side. When this is done, either the deskew circuit or the deskew signal generation circuit is selectively activated. The multiplexer MUX and the demultiplexer DMUX perform a 1:16 multiplexer operation or a 16: 1 demultiplexer operation depending on the signal transmission direction. Therefore, an input / output circuit as an interface is provided on each input side and output side of the SFI-5 adapter and the multiplexer MUX (demultiplexer DMUX).
[0014]
Although the SFI-5 adapter shown in FIGS. 1 and 2 is relatively slow, it has a large circuit scale and can be constituted by a semiconductor chip having a CMOS circuit as a main circuit, whereas the multiplexer MUX (demultiplexer DMUX) In the example shown in FIG. 13, the signal is converted into a k-times ultra-high-speed signal, so that a high-speed bipolar transistor must be used. Therefore, it is difficult to form two circuits using circuit elements having greatly different element structures on a single semiconductor substrate using current technology. Therefore, prior to the present invention, a study was made on forming these circuits with two semiconductor devices as shown in FIGS. 15 and 16 and mounting them on a mounting substrate to form a circuit.
[0015]
In an electronic system, a plurality of semiconductor devices packaged by a normal package technology such as a QFP (Quad Flat Package), a CSP (Chip Size Package or Chip Scale Package), and a BGA (Ball Grid Array) are used. It is configured by being mounted on a mounting board such as a printed board. In this case, it is difficult to reduce the distance between the semiconductor chips and the wiring distance thereof, and the signal delay due to the wiring is large, which imposes restrictions on speeding up and miniaturizing the device.
[0016]
In FIG. 15, even if the phase is correctly corrected in the deskew circuit, the output signal is re-phased due to the relatively long distance between the semiconductor chips on the mounting board and the variation of the output circuit elements and the load as described above. There is a possibility that a shift may occur. In FIG. 16, when a phase shift occurs due to a relatively long distance in the path from the demultiplexer DMUX to the deskew circuit and variations in its output circuit elements and loads, there is no way to correct the phase shift and the deskew is performed without the phase shift. The signal RD is added.
[0017]
On the other hand, in a multi-chip module (Multi Chip Module) technology, a plurality of extremely small semiconductor chips called so-called bare chips are used as a semiconductor device in the form of one package. The wiring distance between the chips can be reduced, and the characteristics of the semiconductor device can be improved. In addition, by forming a plurality of chips into one package, the size of the semiconductor device can be reduced, and the mounting area can be reduced, so that the size of the semiconductor device can be reduced.
[0018]
Therefore, in comparison between FIGS. 1 and 15 and FIGS. 2 and 16, both use the same input / output circuit in terms of circuit function, but in the multichip module, the signal transmission distance between chips and the load Since this can be greatly reduced, the above-described phase shift problem can be substantially solved. In addition, when the above-described multi-chip module is premised, the current driving capability of the input / output circuit can be reduced, and low power consumption can be realized. In this embodiment, the SFI-5 adapter and the multiplexer (demultiplexer) which are closely related to each other are selected to form a multi-chip module, so that the features of the multi-chip module can be fully utilized.
[0019]
FIG. 3 shows a configuration diagram of an embodiment of a semiconductor chip corresponding to the signal processing device on the transmission side in FIG. The SFI-5 adapter includes an SFI-5 bus interface, a deskew circuit DSK (Deskew) and an output circuit, and includes a PLL circuit for generating a clock and a test circuit TEST. The SFI-5 bus interface, the deskew circuit DSK (Deskew), the PLL circuit and the test circuit TEST are constituted by CMOS circuits. On the other hand, the output circuit includes an ECL / CMOS converter. That is, the output circuit is constituted by a CMOS-bipolar composite circuit.
[0020]
The test circuit TEST and the clock generation circuit CMU are added to the multiplexer MUX. In particular, the multiplexer MUX handles high-speed serial data corresponding to the optical signal as described above. Therefore, the multiplexer MUX is composed of silicon-gallium germanium (Si-GaGe) together with the test circuit and the clock generation circuit CMU using transistors and the like. And the clock generation circuit CMU are configured by using general silicon-based bipolar transistors.
[0021]
FIG. 4 shows a configuration diagram of an embodiment of a semiconductor chip corresponding to the signal processing device on the receiving side in FIG. The SFI-5 adapter includes an SFI-5 bus interface, a deskew circuit DSK (DSC generate), and an input circuit, and includes a PLL circuit for generating a clock and a test circuit TEST. The SFI-5 bus interface, the deskew circuit (DSC generate), the PLL circuit and the test circuit TEST are constituted by CMOS circuits. On the other hand, the output circuit includes an ECL / CMOS converter. That is, the input circuit is constituted by a CMOS-bipolar composite circuit. The demultiplexer DMUX has a test circuit TEST and a clock generation circuit CMU added thereto. The demultiplexer DMUX, the test circuit and the clock generation circuit CMU are bipolar transistors such as silicon-gallium germanium (Si-GaGe) transistors. Be composed. A general silicon bipolar transistor is used for the test circuit and the clock generation circuit CMU.
[0022]
FIG. 5 is an external view of an embodiment of the signal processing device on the transmitting side in FIG. In the communication module, an IC chip forming the SFI-5 adapter and an IC chip forming the multiplexer are integrally sealed as one IC module. That is, as described above, the SFI-5 adapter and the multiplexer, which are formed in a remarkably small form such as a so-called bare chip, are formed into one package, and the connection between the two IC chips is formed on the mounting substrate. Connected by short wiring. The SFI-5 bus and the output terminal of the multiplexer exchange signals with other devices through solder bumps on the back surface of the module. The connector is provided for inputting a clock formed by a VCO and for outputting a high-speed signal such as 40 Gb / s corresponding to an optical signal such as 40-43 Gb / s.
[0023]
FIG. 6 is an external view of one embodiment of the signal processing device on the receiving side in FIG. The communication module is a module in which an IC chip constituting the demultiplexer DMUX and an IC chip constituting the SFI-5 adapter are integrally sealed as one IC module as in the embodiment of FIG. is there. Then, the connection between the two IC chips is connected by a short wiring formed on the mounting substrate. The input terminals of the SFI-5 bus and the demultiplexer are connected to other devices through solder bumps on the back surface of the module. The connectors are provided for inputting a clock formed by a VCO and for inputting a high-speed signal corresponding to an optical signal such as 40-43 Gb / s.
[0024]
FIG. 7 is a block diagram showing another embodiment of the signal processing device on the transmitting side in FIG. In this embodiment, the SFI-5 adapter and the multiplexer MUX are constituted by one chip. As a common substrate on which circuit elements constituting the SFIF-5 adapter and the multiplexer MUX can be formed, for example, an artificial sapphire substrate or an artificial diamond substrate can be used. In this embodiment, a VCO is also mounted, and a bump electrode provided on the back surface of the semiconductor integrated circuit device is used for a high-speed output signal. Thus, the connector as shown in FIG. 5 is not required, and the device can be downsized.
[0025]
FIG. 8 is a block diagram showing another embodiment of the signal processing device on the receiving side shown in FIG. Also in this embodiment, the SFI-5 adapter and the demultiplexer DMUX are constituted by one chip as in FIG. In this embodiment, a VCO is also mounted, and a high-speed input signal also uses a bump electrode provided on the back surface of the semiconductor integrated circuit device. Thus, the connector as shown in FIG. 6 is not required, and the device can be downsized.
[0026]
FIG. 9 is an operation explanatory diagram of an example of the signal processing device on the transmission side according to the present invention. Each of the parallel signals 00 to 0F (00 to 15) sent from the signal processing LSI shown in FIG. 1 has a phase shift within ΔT with respect to the deskew signal RD due to a difference in characteristics of an output circuit or a transmission line. . The deskew signal RD is composed of a signal obtained by extracting m bits of each of the parallel data signals 00 to 0F and a header code added to the head of the data. The SFI-5 adapter corrects the phase shift between the data 00 to 0F based on the deskew signal RD and transmits the corrected data to the multiplexer MUX. The multiplexer MUX serially arranges them in the order of 00 to 15 (0F) to generate high-speed data.
[0027]
Therefore, if a phase shift occurs in the parallel data 00 to 0F from the SFI-5 adapter transmitted to the input unit of the multiplexer MUX, the above-described correction operation becomes useless and correct data cannot be transmitted. For this reason, no phase shift is allowed between the SFI-5 adapter and the multiplexer MUX. In this embodiment, this problem can be solved by modularization or one chip as described above.
[0028]
FIG. 10 is an operation explanatory diagram of an example of the signal processing device on the receiving side according to the present invention. The high-speed serial data 00 to 15 (0F) sent from the optical module of FIG. 13 is expanded into 16-bit parallel data consisting of 00 to 0F (1:16) by the demultiplexer DMUX. This is transmitted to the SFI-5 adapter, and the deskew signal RD is generated and transmitted to the signal processing LSI on the receiving side as 17-bit parallel data. Even if a phase shift occurs between the SFI-5 adapter and the signal processing LSI, the phase shift of each of the data 00 to 0F can be corrected by using the deskew signal RD.
[0029]
However, a phase shift between the demultiplexer DMUX and the SFI-5 adapter cannot be corrected, and correct data cannot be received. For this reason, a phase shift between the demultiplexer DMUX and the SFI-5 adapter is not allowed. In this embodiment, this problem can be solved by modularization or one chip as described above.
[0030]
FIG. 11 is a block diagram showing one embodiment of the deskew circuit of FIG. In this embodiment, an outline of a case in which phase adjustment (bit shift correction) is performed after parallel development is shown. The shift register A is a register for recognizing a header code. After the data is developed into n bits in parallel by an S / P (serial / parallel) circuit, the data is held in a shift register B in order to compare the data of each bit. A phase shift between the deskew signal RD and the serial data signals R0 to Rk (k is, for example, 15) is compared by a comparison circuit, and a bit is shifted by a barrel shifter based on the comparison result to correct the phase (bit) shift.
[0031]
FIG. 12 is a block diagram showing another embodiment of the deskew circuit of FIG. In this embodiment, in adjusting the phase shift between data in the serial-to-parallel conversion operation, a shift register for holding serial data originally in the S / P circuit to reduce the circuit scale and shorten the latency. The data held in A is used. That is, each bit is compared between the deskew signal RD held in the register A and each of the parallel data signals R0 to Rk (k is, for example, 15) to detect a phase difference. The phase difference (bit shift) is corrected by the phase adjustment circuit according to the output result of the comparison circuit. In this embodiment, the phase difference is 0 before being input to the demultiplexer (De-Multiplexer (DEMUX)) provided in the S / P circuit, and the data of the correct sequence of the total AGbps is maintained after the S / P conversion. It becomes.
[0032]
The phase adjustment circuit corrects the phase difference (bit shift) from the deskew signal RD by adjusting the number of flip-flop circuits FF that shift serial data based on the output result of the comparison circuit. The phase adjustment may be performed only once at the start of the system operation, and thereafter, either the phase may be fixed or the phase may be adjusted again if the phase is shifted.
[0033]
In this embodiment, the detection and correction of the phase difference are performed not on the parallel data but on the serial data itself. The phase difference between the deskew signal and the serial data is detected to correct the phase difference, and the phase difference between the serial data is set to 0 before parallel development. Originally, an S / P circuit that converts serial data into parallel data has a built-in register that holds a serial data string. Therefore, there is no need to add a register for detecting a phase difference, and the circuit can be realized only with a comparison circuit for comparing data held in the register and a circuit for correcting a phase (bit) shift.
[0034]
FIG. 14 is a block diagram of a signal processing device used in an optical communication device studied prior to the present invention. In FIG. 14A, the SFI-5 adapter for transmission and the SFI-5 adapter for reception are each configured as one semiconductor device, and the multiplexer MUX and the demultiplexer DMUX are configured as one module. This configuration has the advantage that the multiplexer MUX and the demultiplexer DMUX are integrated, so that the output of the multiplexer MUX can be fed back to the input of the demultiplexer DMUX, so that the test can be performed by itself. In addition to the fact that the noise margin is reduced due to signal interference, the output of the multiplexer MUX and the demultiplexer DMUX, which consume large current, increase the heat generation in the demultiplexer DMUX, thereby increasing the cost for heat dissipation measures. . Further, the number of signal wirings on the mounting board for connecting the three semiconductor devices increases.
[0035]
In FIG. 14B, the SFI-5 adapter for transmission and the SFI-5 adapter for reception are modularized, and the multiplexer MUX and the demultiplexer DMUX are each configured by one semiconductor device. In this configuration, the number of wirings on the mounting board becomes large, and the power consumption of the connection IO increases.
[0036]
In FIG. 14C, the SFI-5 adapter for transmission, the SFI-5 adapter for reception, the multiplexer MUX, and the demultiplexer DMUX are each configured by one module. In this example, in addition to the problems of the noise margin and heat generation as described above, the number of wirings on the mounting board becomes large, and the power consumption of the connection IO increases. Further, the SFI-5bus I / O circuit of the SFI-5 adapter has a large area, and the area and shape of the chip depend on the area. Therefore, if the SFI-5 adapter for transmission and reception is made into one chip, the area becomes large. This causes an increase in cost and a decrease in yield.
[0037]
14 (A) to 14 (C) are, in comparison with the present invention, the phase shift of the parallel signal between the SFIIF-5 adapter and the multiplexer MUX, and the demultiplexer DMUX. The phase shift of the parallel signal between the SFIIF-5 adapter and the SFIIF-5 adapter is likely to be affected by variations in signal paths and output circuits on a mounting board for connecting the semiconductor devices, thereby increasing the cost for countermeasures. . Further, according to the present invention, the high-speed operation unit is provided in separate modules on the transmission side and the reception side, and there is an advantage that signal interference is suppressed and a noise margin can be increased.
[0038]
Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the spirit of the invention. Nor. For example, the specific configuration of the deskew circuit can employ various embodiments. The present invention is not limited to the above-described SFI-5, but also processes such high-speed serial data in parallel or parallel data in high-speed serial processing, and corrects the phase shift as described above. It can be widely applied to signal processing devices having functions.
[0039]
【The invention's effect】
The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application. The timing shift between serial input data of a plurality of systems is adjusted by a deskew circuit on the basis of a reference signal, and a plurality of input data corresponding to the plurality of systems, the timings of which are adjusted by a multiplexer, are received in parallel and sent to an optical transmission line. By converting these signals into serial signals to be performed and using the deskew circuit and the multiplexer as a single encapsulated semiconductor device, it is possible to realize an optical communication device with a simple configuration and high performance.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing an embodiment of a signal processing device on a transmission side used in an optical communication device according to the present invention.
FIG. 2 is a configuration diagram showing an embodiment of a signal processing device on the receiving side used in the optical communication device according to the present invention.
FIG. 3 is a configuration diagram showing one embodiment of a semiconductor chip corresponding to the signal processing device on the transmission side in FIG. 1;
4 is a configuration diagram showing one embodiment of a semiconductor chip corresponding to the signal processing device on the receiving side in FIG. 2;
FIG. 5 is an external view showing an embodiment of the signal processing device on the transmission side in FIG. 3;
FIG. 6 is an external view showing an embodiment of the signal processing device on the receiving side in FIG. 4;
FIG. 7 is a block diagram showing another embodiment of the signal processing device on the transmission side in FIG. 1;
FIG. 8 is a block diagram showing another embodiment of the signal processing device on the receiving side of FIG. 2;
FIG. 9 is an operation explanatory diagram showing one example of a signal processing device on the transmission side according to the present invention.
FIG. 10 is an operation explanatory diagram showing an example of a signal processing device on the receiving side according to the present invention.
FIG. 11 is a block diagram showing one embodiment of a deskew circuit of FIG. 1;
FIG. 12 is a block diagram showing another embodiment of the deskew circuit of FIG. 1;
FIG. 13 is a schematic diagram showing one embodiment of a high-speed optical transmission system to which the present invention is applied.
FIG. 14 is a block diagram of a signal processing device used in an optical communication device studied prior to the present invention.
FIG. 15 is a block diagram of a signal processing device used in an optical communication device studied prior to the present invention.
FIG. 16 is a block diagram of a signal processing device used in an optical communication device studied prior to the present invention.
[Explanation of symbols]
MUX: multiplexer, DMUX: demultiplexer, DSK: deskew circuit, PLL: phase synchronization circuit, CMU: clock generation circuit, TEST: test circuit, S / P: serial-parallel conversion circuit.

Claims (5)

A deskew circuit that performs timing adjustment based on a reference signal with respect to a timing deviation between serial input data of a plurality of systems;
A multiplexer that receives a plurality of input data corresponding to the plurality of systems, the timing of which is adjusted from the deskew circuit, in parallel, and converts the input data into a serial signal to be transmitted to a photoelectric transmission line;
An optical communication device, wherein the deskew circuit and the multiplexer are housed in one sealing body. Receiving a serial signal transmitted through an optical electrical transmission transmission line, a demultiplexer for converting the parallel signals corresponding to multiple systems,
Receiving the parallel signal corresponding to the plurality of systems, including a serial signal of a plurality of systems, a signal generation circuit for forming a reference timing signal used as a reference signal of the timing shift between the serial signals of the plurality of systems,
The optical communication device, wherein the demultiplexer and the signal generation circuit are housed in one sealing body. In claim 1,
The deskew circuit includes: a serial signal including a plurality of systems receiving a parallel signal; and a signal generation circuit forming a reference timing signal used as a reference signal for a timing shift between the plurality of serial signals. An optical communication device, which is used for both a signal receiving side and a signal receiving side. In any one of claims 1 to 3,
An optical communication device, wherein the deskew circuit and the multiplexer or the demultiplexer are each formed of one semiconductor chip, mounted on a module substrate, and integrally sealed. In claim 4,
The optical communication device, wherein the deskew circuit is an SFI-5 adapter conforming to the SFI-5 standard.

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