JP2004220584A - Image processing device and image processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing technique which can handle both CCD and CIS, excellent in memory efficiency, stores image data read by each device in a memory and controls reading the stored data with a rectangular area unit. <P>SOLUTION: An image processing device is provided with a memory area control unit which sets a rectangular area divided in a main scanning direction and in a sub scanning direction to the image data deployed on a first memory, an address generating unit which corresponds to the rectangular area thus set and generates address information for reading the image data corresponding to the rectangular area, a memory control unit which reads the image data corresponding to the rectangular area according to the address information thus generated and DMA-transfers the image data to a second memory, and an image processing part which processes the image data thus DMA-transferred in a rectangular area unit basis by making use of the second memory. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention is applicable to both image reading devices (CCD (Charged Coupled Device) and CIS (Contact Image Sensor)), and stores image data read by each device in a memory and reads out the stored data in units of rectangular areas. The present invention relates to an image processing technique to be controlled.

  FIG. 27 is a block diagram showing a configuration of a scanner image processing circuit in a conventional image processing apparatus. As the image reading device, an optical element such as a CCD 2010 or a CIS 2110 is used, and data according to a predetermined output format in a line unit in the main scanning direction is respectively transferred to a CCD interface (I / F) circuit 2000 and a CIS interface (I / F). ) A / D converted by the circuit 2100 and stored in the main controller c200. In this case, the CCD 2010 outputs the data corresponding to R, G, and B in parallel, while the signal output from the CIS 2110 outputs the R, G, and B data in serial according to the lighting order of the LEDs. Due to the difference in the characteristics of the output data, dedicated interface circuits are provided for each, and the read image data is stored in the main memory (SDRAM) 2200 through a predetermined A / D conversion process. .

  In FIG. 27, dedicated line buffers 2400a to 2400d are provided in each image processing block (such as shading correction (SHD) 2300, character determination processing 2320, and filter processing 2340). In such a circuit configuration, data stored in the main memory (SDRAM) 2200 is read out for a plurality of lines in the main scanning direction, stored in dedicated line buffers (2400a to 2400d), and subjected to individual image processing. The configuration was adopted.

As a prior art that discloses the configuration of the above conventional example, there is one disclosed in Patent Document 1, for example.
JP-A-7-170372

  However, in a circuit configuration in which dedicated line buffers 2400a to 2400d are provided for each processing unit, the maximum number of pixels in the main scanning direction that can perform processing depends on the memory capacity of the dedicated line buffer provided in each processing unit. This is a factor that limits the processing throughput.

Further, in the hardware configuration of the image processing circuit, an increase in the capacity of the line buffer increases the cost burden in order to improve the processing capability, which has been a factor that hinders the cost reduction of the entire image processing apparatus. For example, in order to improve the resolution and the main scanning width of the apparatus, it is necessary to increase the capacity of the line buffer.
Further, signals output from the CCD 2010 and the CIS 2110 as image reading devices have been processed by dedicated interface circuits (2000, 2100) suitable for the respective output formats. The development depends on which device (for example, CCD or CIS) is used, and it has become essential to specialize image data input processing. That is, the image processing circuit is customized depending on which image reading device is employed, and this is a factor that hinders generalization and cost reduction of the image processing circuit.

  In view of the above problems, an object of the present invention is to provide an image processing apparatus that can support various image reading devices, for example, both a CCD and a CIS. Alternatively, storing the image data read by each image reading device in the memory and processing in the image processing unit cuts out the data in the main memory into a predetermined unit adapted to the image processing mode without the intervention of an individual line buffer. It is another object of the present invention to provide an image processing device or the like for controlling data processing.

  Alternatively, an image processing apparatus or the like that sets a rectangular area corresponding to an image processing mode on a memory and switches the unit of the rectangular area to realize a resolution and high definition processing corresponding to each image processing mode is provided. With the goal.

  Alternatively, according to the image processing mode, a rectangular area including a predetermined surplus amount is set, and image processing is performed in units of the rectangular area, so that a predetermined image can be obtained without the intervention of an individual line buffer of each image processing unit. An object of the present invention is to provide an image processing device or the like that executes processing.

  Alternatively, it is another object of the present invention to provide an image processing apparatus and the like that can respond to changes in the main scanning width and resolution of the image processing apparatus regardless of an increase in the capacity of the line buffer.

  In order to achieve the above object, an image processing apparatus according to the present invention mainly has the following configuration.

That is, the image processing apparatus includes: a memory area control unit configured to set a rectangular area divided in the main scanning direction and the sub-scanning direction with respect to the image data developed on the first memory;
Address generation means for generating address information corresponding to the set rectangular area and reading image data corresponding to the rectangular area;
Memory control means for reading image data corresponding to the rectangular area in accordance with the generated address information and performing DMA transfer to a second memory;
Image processing means for performing image processing on the DMA-transferred data in units of rectangular areas using the second memory.

Alternatively, the image processing device may correspond to a rectangular area divided in the main scanning direction and the sub-scanning direction with respect to the image data expanded on the first memory, and read an image data corresponding to the rectangular area. Address generation means for generating information;
Memory control means for reading image data corresponding to the rectangular area according to the generated address information and transferring the image data to a second memory;
A plurality of image processing means for executing image processing as a series of image processing on the image data transferred to the second memory,
The rectangular area has at least a maximum rectangular size required to execute the series of image processing.

  ADVANTAGE OF THE INVENTION According to this invention, it is possible to implement | achieve the resolution and the high definition processing according to each image processing mode by setting the rectangular area according to an image processing mode on a memory, and switching the unit of this rectangular area. Become.

  Alternatively, according to the image processing mode, a rectangular area including a predetermined surplus amount is set, and image processing is performed in units of the rectangular area, so that a predetermined image can be obtained without the intervention of an individual line buffer of each image processing unit. Processing can be performed.

  Alternatively, since no line buffer is required, even if the main scanning width and resolution of the image processing apparatus are flexibly changed, it is possible to cope with the extremely simple configuration.

  FIG. 1 is a block diagram illustrating a schematic configuration of an image processing apparatus 200 according to an embodiment of the present invention. A CCD 17 and a CIS 18 are connected to a scanner interface (hereinafter, referred to as a “scanner I / F”) section 10 via an analog front end (AFE) 15, and read data of the CCD 17 without an intervening dedicated circuit. Can be taken into the image processing apparatus 200. The data processing of the scanner I / F unit 10 will be described later in detail.

Reference numeral 20 denotes a scanner image processing unit which sets an image processing operation mode (color copy, monochrome copy, color scan, monochrome scan, etc.) for the image data developed in the main memory 100 by the processing of the scanner I / F unit 10. This is a processing unit that executes the corresponding image processing. Details of the scanner image processing unit 20 will be described later.

  The printer image processing unit 30 is a processing unit for outputting image data obtained as a result of image processing to a printer, and outputs the image data to a laser beam printer (LBP) 45 connected via an LBP interface (I / F) 40. Execute processing for outputting the processing result.

  Reference numerals 50 and 60 denote JPEG and JBIG modules, which are processing units for executing compression and decompression processing of image data conforming to a predetermined standard.

  Reference numeral 70 denotes a memory control unit which is connected to the first BUS 80 of the image processing system and the second BUS 85 of the computer system, and executes processing units (LDMAC_A to F (105a) which execute DMA control for writing and reading data to and from the main memory (SDRAM) 100. To 105f)). Here, "DMA (Direct Memory Access)" refers to a process of directly moving data between a main storage device and a peripheral device.

  The above-described scanner I / F unit 10, scanner image processing unit 20, printer image processing unit 30, LBPI / F unit 40, JPEG processing unit 50 and JBIG processing unit 60, and each processing unit ( 10 to 60), and processing units (LDMAC_A to F (105a to 105f) for executing DMA control of image data are connected thereto.

  Each of the LDMAC_A to F (105a to 105f) generates predetermined address information for executing DMA control with respect to data transfer between each of the image processing units (10 to 60) and the main memory 100. The DMA is controlled based on the DMA. For example, the LDMAC_A (105 a) stores address information (DMA data) for DMA-transferring image data read by the scanner I / F unit 10 to the main memory 100 in accordance with the type of image reading device, the CCD 17, and the CIS 18. A start address to start, offset information for switching a memory address, etc.) are generated for each DMA channel. The LDMAC_B (105b) generates address information for reading out image data expanded on the main memory 100 according to the channel of the DMA.

  Similarly, predetermined address information can be generated for LDMAC_C to F (105c to 105f), and DMA control for data transfer with the main memory 100 can be executed based on the information. That is, the LDMAC_C to 105F (105c to 105f) have channels corresponding to data writing and data reading, and generate DMA address information corresponding to these channels to control DMA.

  Reference numeral 80 denotes a first BUS capable of exchanging data between the processing units (10 to 60) of the image processing system. Reference numeral 85 denotes a CPU 180, a communication and user interface control unit 170, a mechatronic system control unit 125, and a ROM 95. Is a computer-based second BUS to be connected. The CPU 180 can control the above-described LDMAC_A to F (105a to 105f) based on control parameters and control programs stored in the ROM 95.

  The mechatronics system control unit 125 includes a motor control unit 110 and an interrupt timer control unit 120 that controls the drive timing of the motor and the timing control for controlling the synchronization of the processing of the image processing system.

  The LCD control unit 130 is a unit that performs display control for displaying various settings and processing status of the image processing apparatus on the LCD 135.

  USB interface units 140 and 150 enable connection with peripheral devices. FIG. 1 shows a state in which a BJ-printer 175 is connected.

  Reference numeral 160 denotes a media access control (MAC) unit, which controls at what timing data should be sent to a connected device (access).

  A CPU 180 controls the overall operation of the image processing apparatus 200.

<Configuration of Scanner I / F Unit 10>
The scanner I / F unit 10 includes a CCD 17 and a CI as image reading devices.
It can respond to S18, and performs input processing of signals from both image reading devices. The input image data is DMA-transferred by the LDMAC_A (105a) and developed on the main memory 100.

  FIG. 2 is a block diagram showing a schematic configuration of the scanner I / F unit 10. For the CCD 17 / CIS 18, the timing control unit 11a generates and outputs a control signal of a reading device according to the reading speed. The device control signal is synchronized with a synchronization signal generated in the scanner I / F unit 10, and thereby, it is possible to synchronize the reading timing in the main scanning direction with the reading process.

  The LED lighting control unit 11b is a unit that controls lighting of the LED 19 serving as a light source of the CCD 17 / CIS 18, and a synchronization signal (TG, SP, FIG. 8) for sequentially lighting LEDs corresponding to R, G, and B color elements. 3 (a), see FIG. 4), a clock signal (CLK, see FIG. 4 and the like), dimming control corresponding to the CCD 17 / CIS 18, start of lighting, and control of turning off. This control timing is based on the synchronization signal received from the above-described timing control unit, and controls the lighting of the LED 19 in synchronization with the driving of the image reading device.

  FIGS. 3A to 3D are diagrams illustrating output signals from the CCD 17. The light emitted from the LED 19 illuminates the original surface, and the reflected light is guided to the CCD 17 to be photoelectrically converted. For example, while the reading position is moved at a constant speed in the direction (sub-scanning direction) perpendicular to the line direction of the CCD 17 which is the main scanning direction, the original surface is sequentially scanned for each line in the main scanning direction, and the image on the entire original surface is Can be read. As shown in FIG. 3A, signals corresponding to the R, G, and B elements for one line of the CCD 17 are output in parallel based on the synchronization signal (TG) output from the timing control unit 11a (FIG. 3). (See (b), (c) and (d)).

  On the other hand, FIG. 4 is a timing chart relating to the lighting control of the LED 19 with respect to the CIS 18, and based on the synchronization signal (SP) and the clock (CLK) generated by the LED lighting control unit 11b, the lighting of each R, G, B LED. Start and turn-off timings are controlled. The cycle of the synchronization signal (SP) is indicated by Tstg, and within this time, the lighting of the LED is controlled by one of the colors (R, G, B) or a combination thereof. Tled indicates the LED lighting time in one cycle (Tstg) of the synchronization signal (SP).

  FIG. 5A shows the lighting ((a) to (d)) of the LEDs corresponding to R, G, and B according to the timing chart of FIG. 4 described above, and the reflected light of the LEDs accumulated during the lighting time. 6 is a timing chart showing an output (e) obtained by photoelectric conversion. As is clear from FIG. 5A (e), the output of the signals corresponding to each of the R, G, and B colors is output as R output, G output, and B output, respectively, as serial data. It is different from the output signal.

  FIG. 5B is a diagram related to the control of the CIS 18 and shows the timing when the R, G, and B LEDs 19 are sequentially turned on within one cycle of the synchronization signal (SP). In this case, the input of the image reading device in this case can be taken into the image processing apparatus 200 as monochrome image data.

  FIG. 5C is a diagram illustrating an output when two channels are provided in the main scanning direction in the CIS 18. The output of channel 1 ((c) in FIG. 5C) is synchronized with the falling edge of the N-th CLK signal (see (b) in FIG. 5C) to generate an arbitrary dummy bit string ((c) in FIG. 5C). In this case, 22 bits are output, and then a signal for the effective bit number of 3254 bits is output ((c) in FIG. 5C). On the other hand, the output of channel 2 ((d) in FIG. 5C) is synchronized with the falling edge of the N-th CLK signal from the 3255th effective bit (the bit following the last bit 3254 of the sensor output of channel 1). 2794 bits are output as valid bits.

  The data for one line in the main scanning direction can be divided and read by the sensor outputs of the two channels. The configuration of the CIS is not limited to a maximum of two channels. For example, even if a configuration of three channels is used, only the number of outputs of the number of effective bits changes, and the gist of the present invention is not limited.

  Returning to the block diagram of FIG. 2, an output signal of the image reading device (CCD 17 / CIS 18) is input to an AFE (analog front end) 15. As shown in FIG. 6, the AFE 15 performs gain adjustment (15a, 15d) and A / D conversion processing (15b, c, e) on the output signals of the CCD 17 and the CIS 18, and outputs the signals from the respective image reading devices. The output analog signal is converted into a digital signal and input to the scanner I / F unit 10. Further, the AFE 15 can convert parallel data output from the image reading device into serial data and output it.

  The synchronization control unit 11c in FIG. 2 sets a predetermined threshold level for the AFE 15 according to the analog signal of each device (17, 18), and adjusts the output signal level depending on the difference between the image reading devices. Further, it generates and outputs a synchronization clock for controlling the sampling of an analog signal and outputting a digital signal to the AFE 15, and receives read image data based on a predetermined digital signal from the AFE 15. This data is input to the output data control unit 11d via the synchronization control unit 11c, and the output data control unit 11d buffers the image data received from the AFE 15 in accordance with the output mode of the scanner I / F unit 10 (11e). , F, g).

  The output mode of the scanner I / F unit 10 can be switched between a single mode, a two-channel (ch) mode, and a three-channel (ch) mode, depending on the image reading device to be connected.

  The single mode is a mode selected when data in the main scanning direction is serially input from the AFE 15, and in this case, only one buffer can be used.

  The 2ch mode is a mode selected when data input from the AFE 15 is input at the same timing as information for two channels of the image reading device. In this case, two buffers (for example, 11e, 11e, 11f) is set to a usable state.

  The 3ch mode is a mode selected when image data received from the AFE 15 is input at the same timing as R, G, and B outputs. In this case, three buffers (11e, f, g) are used. It is set to a usable state.

  When the color image data is read by the CIS 18 in the single mode, the data received from the AFE 15 is, as shown in (e) of FIG. The output data control unit 11d stores the data in one buffer (for example, the first buffer (11e)) according to this arrangement. The same applies when monochrome image data is read by the CIS 18, and monochrome image data is stored in one buffer.

  When the color image data is read by the 2-channel CIS 18, the above-described 2ch mode is set. The data received from the AFE 15 is data for each area divided into two in the main scanning direction as shown in (c) and (d) of FIG. 5C, and an output data control unit is used to store the data for each of these areas. 11d stores the received data in two buffers (for example, a first buffer (11e) and a second buffer (11f)). This process is the same even when monochrome image data is read by the CIS2 channel.

  When the color image data is read by the CCD 17, the output data control unit 11d converts the data received from the AFE 15 into three buffers (first, second, and third buffers) for each of R, G, and B data in the above-described 3ch mode. (11e, f, g)).

  Next, a process of performing a DMA transfer of the image data stored in the predetermined buffer (11e, f, g) to the main memory (SDRAM) 100 by the process of the scanner I / F unit 10 and storing the image data will be described. The process of DMA-transferring and storing the image data in the main memory 100 is controlled by the LDMAC_A (105a).

  FIG. 7 shows a DMA transfer between the LDMAC_A (105a) for transferring the image data read by the image reading devices (17, 18) to the main memory (SDRAM) 100 by DMA and the main memory 100 and the scanner image processing unit 20. It is a figure which shows the schematic structure of LDMAC_B (105b) which controls this.

  Reference numeral 75 denotes a buffer controller, which controls the LDMAC_A (105a) and the LDMAC_B (105b) in order to arbitrate data writing and reading when the main memory 100 is used as a ring buffer.

<Configuration of LDMAC_A (105a)>
Here, the LDMAC_A (105a) has a data arbitration unit 71a, a first write data interface (I / F) unit 71b, and an I / O interface unit 71c.

  The I / O interface unit 71c sets predetermined address information generated by the LDMAC_A in the first write data I / F unit 71b in order to store data in the main memory 100. Further, it receives image data from the scanner I / F unit 10 and stores the data in each buffer channel (hereinafter referred to as “channel”) (ch0 to ch2) in the LDMAC_A (105a).

  The first write data I / F unit 71b is connected to a third BUS 73 for writing data to the main memory 100, and the data stored in each channel (ch0 to ch2) according to the generated predetermined address information. Is transferred to the main memory 100 by DMA. The data arbitration unit 71a reads data stored in each channel, and transfers data of each channel in accordance with the write processing of the first write data I / F unit 71b.

  The first write data I / F unit 71b is connected to the buffer controller 75, and is controlled so that memory access does not conflict with data reading or writing by the LDMAC_B (105b) described later. By controlling access to the main memory 100, even when the main memory 100 is used as a ring buffer, data may be overwritten to the same memory address before reading data stored in the main memory 100. Trouble can be prevented, and memory resources can be used effectively.

<(1) Storage of data of one channel>
FIGS. 8A and 8B are diagrams illustrating a process in which the LDMAC_A 105a writes data for one channel to the main memory (SDRAM) 100. FIG. As shown in the output example shown in (e) of FIG. 5A, R, G, and B data for one line in the main scanning direction are serially output, and one buffer (11 in FIG. 2) of the scanner I / F unit 10 is used. When data is stored in (e)), the data is transferred to one corresponding channel (ch0, see FIG. 7) in LDMAC_A (105a). Here, in FIGS. 8A, 8B, 9A, 9B, and 10, the data of the channel (ch0) is transferred to the data arbitration unit 71a and the first write data I / F unit 71b. The configuration for performing DMA transfer and storing in the main memory 100 is denoted as “first LDMAC”, the configuration for processing channel (ch1) data is “second LDMAC”, and the channel (ch2) data is processed. The configuration for performing this operation is referred to as “third LDMAC”.

  FIG. 8A is a diagram illustrating a process of separating and storing one-channel color image data into R, G, and B data. The first LDMAC writes the R data of one line (R1 to R2) in the main scanning direction among the R, G, and B data in the line order in the R area (1000a) of the main memory 100, and G as the next write area. The write address is switched to the start address (G1) of the area (1000b). Then, the first LDMAC writes the G data of one line (G1 to G2) in the main scanning direction among the R, G, and B data in the G area (1000b) of the main memory 100, and then writes the B area as the next write area The write address is switched to the head address (B1) of (1000c). Then, the first LDMAC writes the B data for one line (B1 to B2) in the main scanning direction into the B area (1000c) of the main memory 100, and then sets the address to the start address (R2) of the second line of the R area (1000a). Switch to Hereinafter, similarly, data writing is performed on the G data and B data by shifting the data write address to the second line in the sub-scanning direction.

  In the DMA control for writing data by the first LDMAC, an address of a memory as a storage destination of data corresponding to R data, G data, and B data is given as offset information (A, B), and a storage area for each color data is switched. Thus, the R, G, and B data in the line order can be stored in the main memory 100 separately from the R, G, and B data.

  The start address (R1 in FIG. 8A) for starting the DMA transfer, the offset information (A, B), and the like are based on the generation of the LDMAC_A (105a) described above.

  FIG. 8B is a diagram for explaining the monochrome image data writing processing by the CIS 18 obtained at the LED lighting timing shown in FIG. 5B. In the case of monochrome image data, there is no need to separate the data for each of R, G, and B. Therefore, monochrome image data of the line order is converted into data of one line (M1 to M2) in the main scanning direction of the main memory 100. Writing, the write address is shifted in the sub-scanning direction of the area (1000d), and the data of the next second line (M3 to M4) is written. Thereafter, by performing the same processing sequentially, the monochrome image data can be stored in the area (1000d) of the main memory.

<(2) Data storage by CIS2 channel>
FIG. 9A is a diagram illustrating a process of separating and storing color image data of two channels into R, G, and B data as shown in FIG. 5C. The memory area in the main scanning direction is divided corresponding to two channels.

  Image data read by the two-channel CIS 18 (chip0, chip1) is stored in two buffers (11e, 11f) of the scanner I / F unit 10, and under control of the LDMAC_A 105a, two buffers (11e, 11f). Are transferred to the channels (ch0, ch1) in 105a.

  The first LDMAC stores the data (chip0_data) of the channel (ch0) in areas indicated as a first R area (1100a), a first G area (1200a), and a first B area (1300a) in FIG. 9A.

  In FIG. 9A, the first LDMAC writes R data (RA1 to RA2) of the R, G, and B data input from chip0 into the first R area (1100a) of the main memory, and writes the R data in the next write area. The write address is switched to the start address (GA1) of a certain first G area (1200a) (offset information C). The first LDMAC writes the G data (GA1 to GA2) of the R, G, and B data into the first G area (1200a) of the main memory, and starts the first address (BA1) of the first write area B (1300a) as the next write area. ) Is switched (offset information C). Then, the first LDMAC writes the B data (BA1 to BA2) of the R, G, and B data in the B area (1300a) of the main memory, and after the processing is completed, sets the address in the sub-scanning direction of the R area (1100a). Is switched to the start address (RA3) of the second line (offset information D). Hereinafter, similarly, data writing is performed on the G data and B data by shifting the data write address to the second line in the sub-scanning direction.

  The first LDMAC serves as a data storage area of the main memory for each of the areas shown as a first R area (1100a), a first G area (1200a), and a first B area (1300a) in FIG. The address of the memory can be arbitrarily set based on the offset information (C, D), and the data stored in the channel (ch0) is stored in the main memory 100 according to the setting.

  The second LDMAC stores the data (chip1_data) of the channel (ch1) in the areas shown as the second R area (1100b), the second G area (1200b), and the second B area (1300b) in aj.

  In FIG. 9A, the second LDMAC writes the R data (RB1 to RB2) of the R, G, and B data input from the chip 1 into the second R area (1100b) of the main memory, and writes the R data in the next write area. The write address is switched to the start address (GB1) of a certain second G area (1200b) (offset information E). The second LDMAC writes the G data (GB1 to GB2) of the R, G, and B data into the second G area (1200b) of the main memory 100, and starts the next address (the first address of the second B area (1300b)). The write address is switched to BB1) (offset information E). Then, the second LDMAC writes the B data (BB1 to BB2) of the R, G, and B data into the second B area (1300b) of the main memory 100, and after the processing is completed, sets the address of the second R area (1100b). Switching to the start address (RB3) of the second line in the sub-scanning direction (offset information F). Hereinafter, similarly, data writing is performed on the G data and B data by shifting the data write address to the second line in the sub-scanning direction.

  In the DMA control in which the first and second LDMACs write data, the address of a memory in which data corresponding to R data, G data, and B data is stored is given as offset information (C, D, E, F), and each color data By switching the storage area for each, the R, G, and B data in the line order can be stored in the main memory 100 separately from the R, G, and B data.

  The start address (RA1, RB1 in FIG. 8A) for starting the DMA transfer, the offset information (C, D, E, F) and the like are based on the generation of the LDMAC_A (105a) described above.

  FIG. 9B is a diagram illustrating a process of writing monochrome image data by the two-channel CIS obtained at the lighting timing of the LED shown in FIG. 5B. In the case of monochrome image data, unlike the above-described color image data, it is not necessary to separate the data for each of R, G, and B. The data for the lines (MA1 to MA2, MB1 to MB2) is written, and the write address is shifted in the sub-scanning direction of the same area (1400a, 1400b), and the next second line (MA3 to MA4, MB3 to MB4) Write data. Thereafter, by performing similar processing sequentially, monochrome image data can be stored in the areas (1400a, 1400b) of the main memory.

<(3) Storage of data of three channels>
FIG. 10 shows a case where the output data control unit 11d of the scanner I / F unit 10 processes the image data read by the CCD 17 as data of three channels (R data, G data, and B data). FIG. 3 is a diagram illustrating a process in which first to third LDMACs write data to a main memory 100.

The data stored in the three buffers (11e, 11f, 11g in FIG. 2) is transferred to the channels (ch0, ch2, ch3) in the 105a under the control of the LDMAC_A (105a). The data transferred to ch0 is written in the main memory 100 by the first LDMAC, the data transferred to ch1 is the data written to the main memory 100 by the second LDMAC, and the data transferred to ch2 is Data is written to the main memory 100 by the third LDMAC. The first to third LDMACs are located in the R area (1500) of the main memory 100.
a) By writing data in areas corresponding to the G area (1500b) and the B area (1500c), R, G, and B data can be separated and stored on the main memory 100.

  In this case, the start addresses (SA1, SA2, and SA3 in FIG. 10) at which the DMA transfer starts are based on the generation of the LDMAC_A (105a) described above.

  As described above, the image data read by the image reading devices (CCD 17 and CIS 18) are allocated to the channels for controlling the DMA transfer according to the output format, and the address information and the offset for controlling the DMA for the allocated data. By generating information, it is possible to support various image reading devices.

  In the present embodiment, the image data is stored on the main memory 100 by separating the R, G, and B data regardless of the output format of the image reading device (CCD 17, CIS 18). For this reason, it is not necessary to perform a DMA transfer according to the output format of the image reading device (CCD 17 or CIS 18) to a later-described image processing unit, but only to perform a DMA transfer according to required image processing. Therefore, it is possible to provide an image processing apparatus compatible with the output format of the image reading device (CCD 17, CIS 18) with a very simple configuration / control.

<Setting of area on main memory and DMA transfer>
To transfer image data to the main memory 100 by DMA, the LDMAC_A (105a) generates address information for the main memory 100 and controls DMA transfer according to the address information. FIG. 11A is a diagram showing a state where the main memory 100 is divided into predetermined rectangular areas (blocks), and FIG. 11B is a diagram showing a case where the main memory 100 is used as a ring buffer. In order to perform image processing on the image data stored in the main memory 100 on a rectangular area basis, address information for defining a rectangular area is set according to an image processing mode (copy mode or scanner mode). You. In FIG. 11A, SA indicates a DMA start address, and an area in the main scanning direction (X-axis direction) is divided by a predetermined byte length (XA, XB). The area in the sub-scanning direction (Y-axis direction) is divided by a predetermined number of lines (YA, YB). When used as a ring buffer (FIG. 11B), the hatched areas 101a and 101b are the same memory area.

  The DMA for the rectangular area (0, 0) starts from a start address SA, and when data for XA is transferred in the main scanning direction, a transfer address shifted by one line in the sub-scanning direction is used as offset data (OFF1A). The indicated address is set. Similarly, when the transfer in the main scanning direction and the shift of the address by the offset data (OFF1A) are controlled and the DMA for the rectangular area (0, 0) is completed, the processing shifts to the DMA for the next rectangular area (1, 0).

  The DMA for the rectangular area (1, 0) jumps to the address indicated by the offset address (OFF2A), and thereafter transfers the data in the main scanning direction and the offset data (OFF1A) as in the case of the rectangular area (0, 0). When the DMA for the rectangular area (1, 0) ends, the process proceeds to the next rectangular area (2, 0). Similarly, when the DMA for the YA line is completed up to the area (n, 0), the next DMA is jumped to the address indicated by the offset data (OFF3), and the processing moves to the rectangular area (0, 1). . Similarly, the DMA for the areas (1, 1), (2, 1),... Is controlled. For example, when the size of the rectangular area is different (defined by XB and YB) depending on the memory capacity, offset data (OFF1B and OFF2B) according to the area size is further set to control DMA.

  The rectangular area described above is defined as an area (overlap area) between the rectangular areas based on the resolution in the main scanning direction according to the set image processing mode and the pixel area to be referred to. The number of lines in the sub-scanning direction is set, and the allocation (division) of the image data developed on the memory is controlled.

<Specific example>
FIG. 12 is a diagram exemplifying the capacity required for the main memory for each image processing mode, and is set as follows according to each processing mode.

(A) In case of color copy mode ・ Effective pixels: 600 dpi in the main scanning direction
・ Character judgment processing: 11 lines up and down, 12 pixels left and 13 pixels right ・ Color judgment filtering processing: 2 lines up and down, 2 pixels left and 2 pixels right (Depending on magnification)
(B) In the black and white copy mode ・ Effective pixels: 600 dpi in the main scanning direction
-Color judgment filtering processing: upper and lower two lines, left and right two pixels-Scaling processing: lower one line (c) In color scan mode mode-Effective pixels: 1200 dpi in the main scanning direction
-Variable magnification processing: lower one line

  Further, the setting of the amount of the paste affects not only the memory resources but also the transfer efficiency between the main memory 100 and the scanner image processing unit 20. The transfer efficiency is defined as the area ratio of the effective pixel area to the image area including the transfer margin area. As described above, in the copy mode, the transfer efficiency is low because the provision of the transfer clearance area is indispensable. In the scanner mode, the transfer efficiency is high because there is no overlap except for the scaling process.

  For example, in the case of the color copy mode shown in FIG. 12A, assuming that the rectangular area including the overlap margin area is 281 pixels × 46 lines, the effective area obtained by subtracting the maximum margin area (for character determination processing) is: There are 256 pixels × 24 lines, and the transfer efficiency is (256 pixels × 24 lines) / (281 pixels × 46 lines) ≒ 48%. On the other hand, in the scanner mode shown in FIG. 12C, if the scaling process is not performed, there is no margin, and the transfer efficiency is 100%.

  Since the content of the image processing is different between the scanner mode and the copy mode, the necessary memory area is appropriately set according to the content of the processing. For example, as shown in FIG. 12, in the color copy mode, the character determination processing and the color determination filtering processing are required, so that the amount of the surplus for extracting the effective pixel area (in the figure, it is secured around the effective pixels) Although this will be shown as an area), it is necessary to secure a resolution of about 600 dpi as the number of effective pixels in the main scanning direction. Therefore, the margin area is determined by a trade-off with the memory area.

  On the other hand, in the scanner mode, it is not necessary to secure a surplus amount other than the scaling process, but it is necessary to secure approximately 1200 dpi as the number of effective pixels in the main scanning direction. Therefore, when the memory allocation amount is substantially the same in the scanner mode and the copy mode, if the number of lines in the sub-scanning direction is, for example, 24 lines, the main memory allocation amount in the color copy mode and the scanner mode is reduced. It can be about the same. Hereinafter, the flow of the storage process for each image processing mode will be described with reference to FIGS.

<Storage processing in copy mode>
FIG. 13 is a diagram for explaining the flow of data storage processing in the copy mode. First, in step S10, it is determined whether or not the copy mode is color. If the color mode is color (S10-YES), the process proceeds to step S20, and address information for DMA transfer in the color copy mode is Set as follows.

(A) In the case of writing including the overlap allowance Effective pixels (for example, a resolution of 600 dpi in the main scanning direction) are secured from the head of the buffer, and the overlap allowance (upper and lower 11 lines, left 12 pixels, right 13 pixels) is further provided around the effective pixels. (See (a) of FIG. 12).

(B) When writing only valid pixels • Start address (SA)
= Start address of memory (BUFTOP)
+ Number of pixels of one-page image in the main scanning direction including the margin (TOTALWIDTH) x 11 (Major margin in sub-scanning direction (top)) + 12 (Major margin in main scanning direction (left))
(TOTALWIDTH = number of effective pixels in main scanning of one page image (IMAGEWIDTH)
+ Number of left glue pixels + number of right glue pixels)
UA = memory end address (BUFFBOTTOM) +1
= Return address of ring buffer-OFF1A = TOTALWIDTH-IMAGEWIDTH

  On the other hand, in the monochrome copy mode (step S30), address information for DMA transfer is set as follows.

(A) In the case of writing including the overlap allowance Effective pixels (for example, a resolution of 600 dpi in the main scanning direction) are secured from the head of the buffer, and further, the overlap allowance (upper and lower two lines, left and right two pixels) is set around the effective pixels ( (See FIG. 12B).

(B) When writing only valid pixels • Start address (SA)
= Start address of memory (BUFTOP)
+ Number of pixels of one page image in the main scanning direction including the margin (TOTALWIDTH) x 2 (Major margin in sub-scanning direction (top)) + 2 (Major margin in main scanning direction (left))
UA = memory end address (BUFFBOTTOM) +1
・ OFF1A = TOTALWIDTH-IMAGEWIDTH

  When the address information for the DMA transfer is set in steps S20 and S30, the process proceeds to step S40, and the transfer starts. The data stored in each channel in the LDMAC_A 105a is sequentially read and DMA-transferred according to predetermined address information (S50, 60). When the reading of the data stored in the channels (ch0 to ch2) ends (S70), the DMA transfer ends (S80).

<Storage processing in scanner mode>
FIG. 14 is a diagram for explaining the flow of data storage processing in the scanner mode. First, in step S100, address information for DMA transfer in the scanner mode is set as follows.

(A) In the case of writing including the overlap margin Effective pixels (for example, a resolution of 1200 dpi in the main scanning direction) are secured from the head of the buffer, and further, the overlap margin of the lower one line is set in the sub-scanning direction (( c)).

(B) When writing only valid pixels • Start address (SA) = top address of memory (BUFTOP)
UA = memory end address (BUFFBOTTOM) +1
= Return address of the ring buffer-OFF1A = 0 (TOTALWIDTH = IMAGEWIDTH)

  When the address information is set in step S100, the process proceeds to step S110, and DMA transfer starts. Data stored in each channel in the LDMAC_A 105a is sequentially read and DMA-transferred according to predetermined address information (S120, S130). When the reading of the data stored in the channels (ch0 to ch2) ends (S140), the DMA transfer ends (S150).

  As described above, the image data is expanded in the main memory 100 according to the set processing mode by the processing of FIGS. 13 and 14 are parameters that can be set arbitrarily, and the gist of the present invention is not limited by these conditions. For example, in color transmission of a photograph or the like, the character determination process may be omitted, and the amount of the overlap may be arbitrarily set according to the number of reference pixels of the image processing necessary to perform only the filter process.

<Reading data>
The image data expanded in the main memory 100 is loaded into the scanner image processing unit 20 as corresponding R, G, B data or monochrome image data for each predetermined rectangular area, and image processing is performed for each rectangular area. Is done. In order to perform image processing for each rectangular area, the CPU 180 stores shading (SHD) correction data in the main memory 100 for correcting variations in the sensitivity of the light receiving elements of the image reading devices (CCD 17 / CIS 18) and variations in the light amount of the LEDs 19, and the like. The prepared shading data of the rectangular area and the image data of the rectangular area are DMA-transferred to the scanner image processing unit 20 by LDMAC_B (105b) described later.

  FIGS. 15A and 15B are diagrams for explaining data reading when transferring image data of a rectangular area to the block buffer RAM 210 (FIG. 16) of the scanner image processing unit 20. Regarding the area (0, 0), a surplus area AB1CD1 is set for the effective pixel area (abcd) (FIG. 15A), and reading of image data is performed using A as a start address. Data is read up to the address B1 in the main scanning direction. When the reading of the data in the main scanning direction is completed, the address of the data to be read next is shifted to the A2 address in the figure, which is shifted by one line in the sub-scanning direction, and the data is read out to the pixel at the B3 address in the main scanning direction. . Thereafter, data is read out in the same manner, data is read out in the main scanning direction from the C address to the D1 address corresponding to the last line of the transfer area, and the reading of data in the area (0, 0) is completed. .

Regarding the area (0, 1), a surplus area B2ED2F is set for the effective pixel area (bedf) (FIG. 15B), and reading of image data is performed using B2 as a start address. Data is read up to the E address in the main scanning direction. When the reading of the data in the main scanning direction is completed, the address of the data to be read next is shifted to the B4 address in the figure shifted by one line in the sub-scanning direction, and the data is read out to the pixel at the B5 address in the main scanning direction. Then, the image data in the main scanning direction from the D2 address to the F address corresponding to the last line of the overlap area is read, and the reading of the data in the second area is completed. With the above processing, the data of the rectangular area including the paste allowance area is read. Hereinafter, similar processing is performed for each rectangular area.

<Configuration of LDMAC_B (105b)>
Reading of data stored in the main memory 100 is controlled by the LDMAC_B (105b) in FIG. The read data I / F unit 72a is connected to the main memory 100 via the fourth BUS 74 for reading data, and the read data I / F unit 72a refers to the address information generated by the LDMAC_B (105b) to refer to the main memory 100. 100 can read predetermined image data.

  The read data is set to a plurality of predetermined channels (ch3 to ch6) by the data setting unit 72b. For example, image data for shading correction is channel 3 (ch3), plane-sequential R data is channel 4 (ch4), plane-sequential G data is channel 5 (ch5), and plane-sequential B data is channel 6 (ch6). Then, each data is set.

  The data set for each channel (ch3 to ch6) is sequentially DMA-transferred through the I / P interface 72c under the control of the LDMAC_B (105b), and the block buffer RAM 210 of the scanner image processing unit 20 (FIG. 16). To be loaded.

  The channel 7 (ch7) in the LDMAC_B (105b) stores dot-sequential image data output from the scanner image processing unit 20 in order to store data on which predetermined image processing has been performed in the main memory 100. Channel. The scanner image processing unit 20 outputs address information (block end signal, line end signal) in accordance with the output of dot-sequential image data, and based on the address information, the second write data I / F 72d , The image data stored in the channel 7 is stored in the main memory 100. The details of this processing will be described later.

<Image processing>
FIG. 16 is a block diagram illustrating a schematic configuration of the scanner image processing unit 20, and processing according to each image processing mode is performed on data loaded in the block buffer RAM 210. FIG. 19 is a diagram schematically illustrating the size of a rectangular area required for each image processing. The scanner image processing unit 20 executes processing by switching a rectangular pixel area to be referred to a rectangular area according to the set image processing mode. Hereinafter, the contents of the image processing will be described with reference to FIG. 16, and the size of the rectangular area referred to in the processing will be described with reference to FIG.

  In FIG. 16, a shading correction block (SHD) 22 is a processing block for correcting variations in the light amount distribution of the light source (LED 19) in the main scanning direction, variations in the light receiving elements of the image reading device, and offsets in the dark output. In the shading data, correction data for one pixel is stored in the main memory 100 in the order of bright R, bright G, bright B, dark R, dark G, and dark B in a plane-sequential manner, and the number of pixels corresponding to the rectangular area ( XA pixels are input in the main scanning direction, and YA pixels (see FIG. 19A) in the sub-scanning direction. The input plane-sequential correction data is converted into dot-sequential data by the input data processing unit 21 and stored in the block buffer RAM 210 of the scanner image processing unit 20. Then, when the capturing of the shading data of the rectangular area is completed, the processing shifts to the transfer of the image data.

  The input data processing unit 21 is a processing unit that executes a process of reconstructing plane-sequential data separated into R, G, and B into point-sequential data. The data of one pixel is stored in the main memory 100 as plane-sequential data for each of R, G, and B colors. When these data are loaded into the block buffer RAM 210, the input data processing unit 21 Each pixel data is extracted and reconstructed as R, G, B data of one pixel. Reconstruction processing is performed for each pixel, and plane-sequential image data is converted into dot-sequential data. Here, the reconstruction process is performed on all pixels (XA pixels × YA pixels) in the rectangle.

  FIG. 17 is a diagram schematically showing a target area of image processing and a reference area (ABCD) for performing a filtering process or the like for executing the processing. In FIG. 17, an effective pixel area (abcd) is shown. Thus, “Na” and “Nb” pixels are set as the amount of overlap in the main scanning direction (X direction), and “Nc” and “Nd” pixels are set as the amount of overlap in the sub-scanning direction (Y direction). Have been.

  FIG. 18 is a diagram exemplifying a margin for each image processing mode (color copy mode, monochrome copy mode, scanner mode). The reference area is larger than at the time. In the case of the color copy mode, the largest reference area in the image processing mode is required to determine a black character. In order to detect a black character, it is necessary to reliably determine a halftone dot and a black character. Therefore, in order to determine the period of the halftone dot, pixels (24 + m) in the main scanning direction and (21 + n) pixels in the sub-scanning direction (variable) are used. 2 times) as a reference area. In the monochrome copy mode, the main scanning direction (4 + m) pixels and the sub-scanning direction (4 + n) pixels (at the time of zooming) are used as reference areas in order to perform edge enhancement on a character portion. In the scanner mode, a reference area is not required at the same magnification when performing the necessary image processing by a scanner driver or an application on the host computer. A reference area is set for n pixels in the scanning direction. Note that the gist of the present invention is not limited to the amount of glue shown here, and it is needless to say that it can be set arbitrarily.

  In the processing block 23, the averaging processing unit (SUBS) is a processing block that performs sub-sampling (simple thinning) for lowering the reading resolution in the main scanning direction or averaging processing, and the input masking processing unit (INPMSK) is , A processing block for calculating the color correction of the input R, G, B data. The γ correction processing unit (LUT) is a processing block that gives a predetermined gradation characteristic to input data.

  The character determination processing block 24 is a processing block that performs black character determination and pixel determination of a line drawing contour on input image data. In the black character discrimination processing, since it is necessary to refer to an area wider than the dot period as described above, pixels (lines) in the main scanning direction (24 + m) and pixels (lines) in the sub-scanning direction (21 + n) (“m”, “n”) Is dependent on the magnification of the scaling process.) It is desirable to refer to a considerable paste area. The input data of the character determination processing block 24 is, as in the case of the input of the shading correction block (SHD) 21, the data of the XA pixel (effective pixel + transfer margin) × the YA pixel (effective pixel + transfer margin) in the sub-scanning direction FIG. 19A is referred to. That is, all pixels (XA pixels × YA pixels) in the rectangle are referred to.

  In the processing block 25, the MTF correction processing unit is a processing unit that performs a filtering process in the main scanning direction to correct the MTF difference when the image reading device is changed and to reduce the moire at the time of reduction and magnification. On the other hand, this block is a block for multiplying and adding each coefficient for a predetermined pixel in the main scanning direction. In FIG. 19B, two pixels of the left hatched part (b1) and three pixels of the right hatched part (b2) are secured for the attention area G1, and the processing for the area G1 is executed. That is, the region of interest G1 and the regions of hatched portions b1 and b2 in the rectangle are read to obtain the region of interest G1.

  The (RGB → (L, Ca, Cb)) conversion processing unit (CTRN) performs multi-value processing of each of R, G, and B colors in the filtering (lightness enhancement, saturation enhancement, color determination) performed in the subsequent filter processing block 26. The image data is converted.

  The background density adjustment processing unit (ABC) executes processing for automatically recognizing the background density of the document and correcting the background density value to the white side to obtain binarized data suitable for facsimile communication or the like.

  The filter processing block 26 performs an edge strength process of the lightness component (L) and a saturation (Ca, Cb) of the image as processes for performing color determination and filtering on the obtained data in the previous CTRN process. Perform emphasis processing. Further, the color judgment of the input image is performed, and the result is output. Further, the parameter of the emphasis amount can be changed based on the character generated in the character determination processing block 24, the determination signal of the line drawing contour part, and the like. The data after the filter processing is converted from L, Ca, Cb to R, G, B data and output. This processing block functions as a 5 pixel × 5 pixel edge enhancement filter when processing monochrome image data.

  In FIG. 19 (c), the above-described filtering process is performed on the attention area G2 using two pixels (lines) in the upper and lower areas and two pixels in the left and right areas (hatched areas) as reference data. That is, an area G2 after filtering is obtained for the area G1 processed by the MTF correction processing unit.

  The scaling (LIP) block 27 is a processing block for performing linear interpolation scaling in the main scanning and sub-scanning directions. In FIG. 19D, the area G3 is an area obtained as a result of the linear interpolation scaling process, and is based on image data (d: (X− (Na + Nb) pixels) × (Y− (Nc + Nd) pixels)). The hatched area is scaled in the main scanning direction and the sub-scanning direction according to a predetermined magnification (main scanning direction (+ m pixels) and sub-scanning direction (+ n line)), and the area of the area G3 is determined. You. That is, the area G2 after scaling is obtained using the area G2 after the filter processing as an input.

  In FIGS. 19B to 19D, “Na” and “Nb” in FIG. 19 indicate the number of pixels set as the amount of overlap in the main scanning direction (X direction) as in FIG. And "Nd" indicate the number of pixels set as the amount of surplus in the sub-scanning direction (Y direction).

  The above image processing is performed on the image data in units of rectangular areas according to the set image processing mode (copy mode, scanner mode). By setting a rectangular area according to the image processing mode on the memory and switching the unit of the rectangular area, it is possible to realize a resolution and high definition processing according to each image processing mode. Also, since each rectangular area includes a margin necessary for image processing of each processing block, in order to process the end of the rectangular image data to be processed, the image data of the adjacent area is processed in units of rectangles. There is no need to read, and a further reduction in work memory can be achieved as compared with a method in which an image is simply divided into rectangular units and subjected to image processing.

  As described above, the maximum rectangular image data required in each image processing unit is pre-loaded into the block buffer RAM 210, and the image data in the RAM 210 is simply transferred between the image processing units in the required amount of image data. , A series of image processing necessary for each mode such as a color copy / monochrome copy / scanner mode can be realized. This eliminates the need for a dedicated line buffer in the image processing block. Further, since all image processing can be performed using the rectangular image data loaded in the block buffer RAM 210, image processing independent of the main scanning width and resolution can be performed. Therefore, it is not necessary to expand the capacity of the line buffer of each image processing unit according to the main scanning width and the resolution as in the related art. Further, it is possible to provide a device such as a copy and a scanner for performing necessary image processing at an appropriate time with an extremely simple configuration.

  FIG. 20 is a diagram for explaining a start point in the DMA main scanning direction for DMA transfer of image data of the next rectangular data after processing of one rectangular data is completed. When the DMA of the first rectangular area ABCD is completed and the transfer to the pixel at the point D is completed, the start point in the main scanning direction is a position (point S1 in the drawing) returned by Na + Nb pixels in the main scanning direction. Thereafter, the DMA of the rectangular data of one column is sequentially completed, and when the DMA at the point E corresponding to the last rectangular data of the first column is transferred, the sub-scan is performed to transfer the rectangular data of the next column. The starting point of shifting in the direction is a position (S2 in the figure) returned by Nc + Nd pixels.

  FIGS. 21 and 22 are flowcharts illustrating the flow of the DMA transfer process and the image process for each image processing mode. The address information described with reference to FIGS. 21 and 22 uses specific numerical values as examples, but is not limited to these numerical values, and can be set arbitrarily.

<Process in copy mode>
FIG. 21 is a flowchart illustrating the flow of data reading and image processing in the copy mode. First, in step S200, it is determined whether the mode is the color mode or the monochrome mode. If the mode is the color mode (S200-YES), the process proceeds to step S210. If the mode is the monochrome mode (S200-NO), the process proceeds to step S220.

  In step S210, address information for reading in the color copy mode is set as follows. This address information is generated by LDMAC_B (105b) (the same applies to step S220), and based on this address information, LDMAC_B (105b) controls DMA.

-Start address (SA) = top address of memory (BUFTOP)
UA = memory end address (BUFFBOTTOM) +1
XA = rectangular effective main scanning pixel
+ Glue allowance (number of left glue pixels (12 pixels), number of right glue pixels (13 pixels))
YA = rectangular effective sub-scanning pixel (line)
+ Glue allowance (number of upper surrogate pixels (11 pixels (line)), number of lower surrogate pixels (11 pixels (line))
・ OFF1A = TOTALWIDTH-XA
・ OFF2A =-(TOTALWIDTH × YA + glue allowance (12 pixels on the left, 13 pixels on the right))
・ OFF3A =-(TOTALWIDTH × (paste allowance (upper 11 pixels, lower 11 pixels)
+ Effective main scanning pixel + Negative margin (Left 12 pixels, Right 13 pixels))
(TOTALWIDTH = number of effective pixels in main scanning of one page image (IMAGEWIDTH)
+ Number of left glue pixels + number of right glue pixels)
XANUM = effective main scanning pixel / rectangular effective main scanning pixel

  In step S220, address information for reading in the monochrome copy mode is set as follows.

-Start address (SA) = top address of memory (BUFTOP)
• Memory end address (BUFFBOTTOM) + 1
XA = rectangular effective main scanning pixel + gap (number of left-gap pixels (2 pixels), right-gap pixel (2 pixels))
YA = Rectangular effective sub-scanning pixel (line) + overlap (number of upside pixels (2 pixels (line)), downover pixel (2 pixels (line)))
・ OFF1A = TOTALWIDTH-XA
・ OFF2A =-(TOTALWIDTH × YA + glue allowance (left 2 pixels, right 2 pixels))
・ OFF3A =-(TOTALWIDTH × (Glue allowance (upper 2 pixels, lower 2 pixels)
+ Effective main scanning pixel + Negative margin (Left 12 pixels, Right 13 pixels))
(TOTALWIDTH = number of effective pixels in main scanning of one page image (IMAGEWIDTH)
+ Number of left glue pixels + number of right glue pixels)
XANUM = effective main scanning pixel / rectangular effective main scanning pixel

  When the address information is set in the read data I / F unit 72a in steps S210 and S220, the process proceeds to step S230, and it is determined whether or not the LDMAC_B (105b) is in a state where data can be read. For example, if the buffer controller 75 is in a state in which buffer reading is prohibited, the process waits until the state is released (S230-NO), and if buffer reading is possible (S230-YES), the process proceeds to step S240. Proceed to

  In step S240, the read data I / F unit 72a reads data according to the set address information, and the data setting unit 72b sets the data to a predetermined channel (ch3 to ch6). Then, the LDMAC_B (105b) performs DMA transfer of the data set for each channel to the buffer RAM 210 of the scanner image processing unit 20. Here, the data that has been DMA-transferred is loaded into a buffer of the scanner image processing unit 20, and image processing is performed according to each image processing mode. Since the contents of the individual image processing have been described above, the detailed description thereof is omitted here.

  The loaded shading correction data and image data are converted from frame-sequential data to dot-sequential data by the above-described input data processing unit 21 and subjected to the following image processing.

  In step S250, it is determined whether the mode is the color copy mode or the monochrome copy mode. If the mode is the color copy mode (S250-YES), the process proceeds to step S260 to execute the character determination process. In the case of the monochrome copy mode (S250-NO), the process skips step S260 (character determination process), executes the filter process in step S270, and executes the scaling process in step S280.

  The above processing is executed for each data of the rectangular area. In step S290, the dot-sequential image data on which the image processing has been performed is further DMA-transferred to a predetermined memory area for storing the image-processed data and stored. This storing process will be described later in detail.

  In step S300, it is determined whether or not the image processing of the rectangular area and the processing of storing the data have been completed. If the processing has not been completed, the process returns to step S250, and the same processing is performed. When the processing of the rectangular area is completed (S300-YES), the process proceeds to step S310, and it is determined whether the processing of the rectangular area constituting the entire page is completed (S310). If the processing for the entire page has not been completed (S310-NO), the processing returns to step S230, the subsequent image data is read from the main memory 100, and image processing (steps after S230) is performed on the data.

  On the other hand, if the page processing has been completed (S310-YES), the process proceeds to step S320, where the DMA transfer to the scanner image processing unit 20 (S320) and the process of writing data to the buffer of the scanner image processing unit 20 are completed. (S330), the image processing in the scanner image processing unit 20 ends (S340).

  With the above processing, the image processing for the data read in the copy mode is completed.

<Processing in scanner mode>
FIG. 22 is a flowchart illustrating the flow of data reading and image processing in the scanner mode. First, in step S400, address information for reading data from the main memory 100 is set as follows. The address information is generated by the LDMAC_B (105b), and the LDMAC_B (105b) controls the DMA based on the address information.

-Start address (SA) = top address of memory (BUFTOP)
UA = memory end address (BUFFBOTTOM) +1
XA = rectangular effective main scanning pixel YA = rectangular effective sub-scanning pixel (line)
+ Glue allowance (number of pixels for the lower glue (1 pixel (line)))
・ OFF1A = TOTALWIDTH-XA
・ OFF2A =-(TOTALWIDTH × YA)
・ OFF3A =-(TOTALWIDTH × (Normal margin (number of lower margin pixels (1 pixel))
+ Effective main scanning pixel)
(TOTALWIDTH = number of effective pixels in main scanning of one page image (IMAGEWIDTH)
+ Number of left glue pixels + number of right glue pixels)
XANUM = effective main scanning pixel / rectangular effective main scanning pixel

  When the address information is set in the read data I / F unit 72a in step S400, the process proceeds to step S410, and it is determined whether the LDMAC_B (105b) is in a state where data can be read. For example, if the buffer controller 75 is in a state in which data reading is prohibited, the process waits until the state is released (S230-NO), and if buffer reading is possible (S230-YES), the process is performed in step S230. Proceed to S420.

  In step S420, the read data I / F unit 72a reads data according to the set address information, and the data setting unit 72b sets the data on a predetermined channel (ch3 to ch6). The LDMAC_B (105b) performs DMA transfer of the data set for each channel to the buffer of the scanner image processing unit 20. Here, the data that has been DMA-transferred is loaded into a buffer of the scanner image processing unit, and image processing corresponding to each image processing mode is executed. Since the content of the image processing has been described above, a detailed description thereof will be omitted.

  The loaded image data is converted from frame-sequential data to dot-sequential data by the input data processing unit 21 described above, and a scaling process is performed in step S430.

  In step S440, the dot-sequential image data after the image processing is further DMA-transferred and stored in a predetermined memory area for storing the image-processed data. This storing process will be described later in detail.

  In step S450, it is determined whether or not the image processing of the rectangular area and the storage processing of the data have been completed. If the processing has not been completed, the processing returns to step S430 again, and the same processing is executed. When the processing of the rectangular area is completed (S450-YES), the processing proceeds to step S460, and it is determined whether the processing of the entire page is completed (S460). If the processing of the entire page has not been completed (S460-NO), the processing returns to step S410, the subsequent image data is read from the main memory 100, and image processing is performed on the data.

  On the other hand, if the page processing has been completed (S460-YES), the process proceeds to step S470, where the DMA transfer to the scanner image processing unit 20 (S470) and the process of writing data to the buffer of the scanner image processing unit 20 are completed. (S480), the image processing in the scanner image processing unit 20 ends (S490).

  With the above processing, the image processing for the image data read in the scanner mode is completed.

  According to the image processing mode, a rectangular area including a predetermined surplus amount is set, and the image processing is performed in units of the rectangular area, so that the predetermined image processing can be performed without the intervention of an individual line buffer of each image processing unit. It is possible to execute.

<Storage of image processed data>
FIG. 23 is a diagram illustrating a process of transferring rectangular data that has been subjected to scaling processing from the scaling processing block (LIP) 27 to the main memory 100. For example, when reducing rectangular data of 256 pixels × 256 pixels to 70%, 256 pixels × 0.7 = 179.2 pixels, and it is necessary to create rectangular data of 179.2 pixels × 179.2 pixels in numerical calculation. is there. However, since it is impossible to generate pixel data reflecting the numerical value below the decimal point, the appearance probability of 180 pixels and 179 pixels in the main scanning direction and the sub-scanning direction is controlled to 2: 8, and overall reduction is performed. 179.2 pixels corresponding to a magnification of 70% are generated. In FIG. 23, the size of the rectangular area is different from the area B11 (XA1 = 180 pixels) and B12 (XA2 = 179 pixels) in the number of pixels in the main scanning direction, and B11 (YA1 = 180 pixels) and B21 (YA2 = 179 pixels). And the size of the rectangular area differs in the sub-scanning direction. Appearance probabilities of rectangular regions having different sizes are controlled in accordance with the result of the scaling process, so that predetermined scaled image data can be obtained. Then, in order to return the image-processed data to the main memory 100, a signal for controlling the DMA is notified from the scaling processing block (LIP) 27 to the LDMAC_B (105b) (FIG. 24).

  Next, processing in step S290 in FIG. 21 and step S440 in FIG. 22 will be described. FIG. 25 is a timing chart showing the relationship between data and signals sent from the scaling processing block (LIP) 27 to the LDMAC_B (105b) in order to DMA-transfer image-processed data to the main memory 100.

  When storing the image-processed data in the main memory 100, the LDMAC_B (105b) starts the DMA transfer with the rectangular main scanning length and sub-scanning length unknown. When the final data (XA1, XA2) of the main scanning width within one rectangle is transferred from the scaling processing block 27, a line end signal is output, and the main scanning length of the rectangle is changed by the line end signal. To LDMAC_B (105b).

  A block end signal is output to the LDMAC_B (105b) at the time of the final data transfer within one rectangle from the scaling processing block 27, whereby the sub-scanning length can be recognized. When all the data in the sub-scanning direction YA1 has been processed, the DMA transfer is shifted to the areas B21 and B22 (see FIG. 23), and the data XA in the main scanning direction is transmitted similarly. DMA is controlled by a line end signal and a block end signal. As a result, the rectangular area of the DMA can be dynamically switched according to the operation result of the scaling processing block 27.

  The above-described line end signal, block end signal, and dot-sequential image data are input to the interface unit 72c of the LDMAC_B (105b), and the image data is stored in the channel (ch) 7. The line end signal and the block end signal are used as address information when data stored in the channel (ch) 7 is expanded on the main memory 100, and the second write data I / F unit 72d uses these addresses. The data of ch7 is read based on the information, and the data is stored in the main memory 100.

  FIG. 26 is a diagram illustrating a state where data is expanded in the main memory 100 in accordance with the line end signal and the block end signal. In the figure, SA indicates a start address of DMA transfer, and from this address, dot-sequential RGB data is stored in the main scanning direction. Based on the line end signal, the address of the DMA transfer is switched by the offset information (OFF1A), and data is similarly stored in the main scanning direction from the address shifted by one pixel (line) in the sub-scanning direction. Then, based on the block end signal of the rectangular area (0, 0), the processing shifts to storing data in the next rectangular area (1, 0). The address of the DMA transfer is switched by the offset information (OFF2A). OFF2A in this case is switched as an address shifted by one pixel in the main scanning direction with respect to the area (0, 0) and jumped to the first line in the sub-scanning direction.

  Hereinafter, similarly, data is stored in the areas (2, 0),... (N−1), (n, 0), and when the storage of n blocks is completed, the offset information (OFF3) Switches the address of the DMA transfer. OFF3 in this case is shifted by one pixel (line) in the sub-scanning direction with respect to the pixel on the last line of the area (0, 0), and is switched as the address jumped to the first pixel in the main scanning direction.

  As described above, the image-processed data is DMA-transferred to a predetermined area of the main memory 100 by dynamically switching the offset information (OFF1A, OFF2A, OFF3) according to the line end signal and the block end signal. , Can be stored.

  Further, according to the above-described embodiment, it is possible to provide an image processing apparatus that can support various image reading devices. That is, various kinds of image data read by the image reading device are allocated to channels for controlling DMA transfer according to the output format, and address information and offset information for controlling DMA are generated for the allocated data. It is possible to support an image reading device.

<Other embodiments>
In the above-described embodiment, the present invention has been described as a composite image processing apparatus having various image input / output functions. However, the present invention is not limited to this, and a single-function scanner, The present invention is also applicable to an option card or the like for extended connection to a device. Also, the unit configuration of the device according to the present invention is not limited. For example, the device or system according to the present invention may be configured to be achieved by a plurality of devices connected via a network. .

  An object of the present invention is to execute a computer program (or CPU or MPU) of a system or apparatus by reading a program code stored in a storage medium storing program codes of software for realizing the functions of the above-described embodiments, and executing the program. It is also achieved by doing In this case, the program code itself read from the storage medium realizes the function of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

  As a storage medium for supplying the program code, for example, a floppy (registered trademark) disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD-R, magnetic tape, nonvolatile memory card, ROM, or the like is used. be able to.

  When the computer executes the readout program code, not only the functions of the above-described embodiments are realized, but also an OS (Operating System) running on the computer based on the instruction of the program code. This also includes a case where some or all of the actual processing is performed and the functions of the above-described embodiments are realized by the processing.

  Furthermore, after the program code read from the storage medium is written into a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion board is written based on the instructions of the program code. Also, there is a case where the CPU or the like provided in the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

FIG. 1 is a block diagram illustrating a schematic configuration of an image processing device 200 according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a schematic configuration of a scanner I / F unit 10. FIG. 3 is a diagram illustrating an output signal from a CCD 17; 5 is a timing chart related to lighting control of an LED 19 with respect to a CIS 18; 5 is a timing chart showing a relationship between lighting of LEDs corresponding to R, G, and B, ((a) to (d)), and output (e) according to the timing chart of FIG. 4. FIG. 9 is a diagram showing timings when the R, G, and B LEDs 19 are sequentially turned on within one cycle of a synchronization signal (SP) in relation to the control of the CIS 18. FIG. 5 is a diagram illustrating an output when two channels are provided in the main scanning direction in the CIS 18; FIG. 3 is a block diagram illustrating processing of the AFE 15; FIG. 3 is a diagram illustrating a schematic configuration of an LDMAC_A for performing DMA transfer of image data read by an image reading device to a main memory, and an LDMAC_B for controlling DMA between the main memory and a scanner image processing unit. FIG. 4 is a diagram illustrating a process in which an LDMAC_A 105a writes data for one channel to a main memory 100. FIG. 4 is a diagram illustrating a process in which LDMAC_A 105a writes data for two channels to main memory 100. FIG. 9 is a diagram illustrating a process in which LDMAC_A 105a writes data for three channels to main memory 100. FIG. 3 is a diagram showing a state in which the main memory 100 is divided into predetermined rectangular areas (blocks). FIG. 2 is a diagram illustrating a capacity required for a main memory for each image processing mode. FIG. 9 is a diagram for explaining the flow of data storage processing in a copy mode. FIG. 4 is a diagram illustrating a flow of a data storage process in a scanner mode. FIG. 4 is a diagram for describing data reading when image data in a rectangular area is transferred to a block buffer RAM of a scanner image processing unit 20. FIG. 2 is a block diagram illustrating a schematic configuration of a scanner image processing unit 20. FIG. 3 is a diagram schematically illustrating a target region of image processing and a reference region for performing a filter process for executing the process. FIG. 6 is a diagram illustrating an example of a margin for each image processing mode (color copy mode, monochrome copy mode, scanner mode). FIG. 4 is a diagram schematically illustrating the size of a rectangular area required for each image processing. FIG. 9 is a diagram illustrating a start point in the DMA main scanning direction for DMA transfer of image data of the next rectangular data after processing of one rectangular data is completed. FIG. 4 is a diagram for explaining the flow of data reading and image processing in a copy mode. FIG. 4 is a diagram illustrating a flow of data reading and image processing in a scanner mode. FIG. 4 is a diagram illustrating a process of transferring rectangular data subjected to scaling processing from a scaling processing block (LIP) 27 to a main memory 100. It is a figure which shows the connection of the variable magnification processing block (LIP) 27 and LDMAC_B (105b). 6 is a timing chart showing the relationship between data and signals transmitted from the scaling processing block (LIP) 27 to the LDMAC_B (105b) in order to DMA-transfer image-processed data to the main memory 100. FIG. 3 is a diagram illustrating a state where data is expanded in a main memory 100 in accordance with a line end signal and a block end signal. FIG. 9 is a block diagram illustrating a configuration of a scanner image processing circuit in a conventional image processing apparatus.

Claims (31)

Memory area control means for setting a rectangular area divided in the main scanning direction and the sub-scanning direction for image data developed on the first memory;
Address generation means for generating address information corresponding to the set rectangular area and reading image data corresponding to the rectangular area;
Memory control means for reading image data corresponding to the rectangular area in accordance with the generated address information and performing DMA transfer to a second memory;
Image processing means for performing image processing on the DMA-transferred data in units of rectangular areas using the second memory;
An image processing apparatus comprising: 2. The image processing apparatus according to claim 1, wherein the memory control unit allocates the image data read from the first memory to each channel capable of DMA transfer. The address generation means, wherein the memory control means reads data from the first memory,
Read start address,
First offset information for controlling DMA transfer within the set rectangular area;
Second offset information for controlling a DMA transfer from a first rectangular area to a second rectangular area adjacent in the main scanning direction;
The image according to claim 1, wherein the first rectangular area is shifted in the sub-scanning direction, and third offset information for controlling DMA transfer to an adjacent third rectangular area is generated. Processing equipment. 2. The image processing apparatus according to claim 1, wherein the image processing unit generates a control signal for DMA-transferring the processed image data of the rectangular area to the first memory. The image processing apparatus according to claim 4, wherein the control signal includes a signal for specifying a main scanning length and a sub scanning length of the rectangular area. 2. The image processing apparatus according to claim 1, wherein the memory control unit DMA-transfers the image data processed by the image processing unit to the first memory based on the control signal, and stores the image data in the first memory. The image processing device according to claim 1, wherein the first memory is a ring buffer. 2. The image processing apparatus according to claim 1, further comprising a buffer control unit for controlling writing of data to the first memory and reading of data. Further comprising mode setting means for setting an image processing mode,
2. The image processing apparatus according to claim 1, wherein the memory area control unit sets a rectangular area for the image data according to the set image processing mode. The image processing unit is a plurality of image processing units each having a predetermined image processing function. Each of the image processing units uses the second memory as a shared memory, and performs processing on the DMA-transferred data. The image processing apparatus according to claim 1, wherein the image processing is performed. 2. The image processing apparatus according to claim 1, wherein the memory area control unit sets a rectangular area to which the image processing unit adds adjacent image areas necessary for processing an image to be processed. 3. apparatus. A memory area control step of setting a rectangular area divided in the main scanning direction and the sub-scanning direction with respect to the image data developed on the first memory;
An address generation step of generating address information corresponding to the set rectangular area and reading out image data corresponding to the rectangular area;
A memory control step of reading image data corresponding to the rectangular area in accordance with the generated address information and DMA-transferring the image data to a second memory;
An image processing step of performing image processing on the DMA-transferred data in units of rectangular areas using the second memory;
An image processing method comprising: A program for causing a computer to execute the image processing method,
A memory area control module for setting a rectangular area divided in the main scanning direction and the sub scanning direction with respect to image data developed on the first memory;
An address generation module that corresponds to the set rectangular area and generates address information for reading image data corresponding to the rectangular area;
A memory control module for reading image data corresponding to the rectangular area according to the generated address information and performing DMA transfer to a second memory;
An image processing module that uses the second memory to cause an image processing unit to execute image processing on the DMA-transferred data in units of rectangular regions;
A program characterized by comprising: A computer-readable storage medium storing an image processing program code, wherein the image processing program code is:
A memory area control code for setting a rectangular area divided in the main scanning direction and the sub scanning direction with respect to image data developed on the first memory;
An address generation code corresponding to the set rectangular area and generating address information for reading image data corresponding to the rectangular area;
A memory control code for reading image data corresponding to the rectangular area according to the generated address information and performing DMA transfer to a second memory;
An image processing code for causing the image processing unit to execute image processing on the DMA-transferred data in units of rectangular areas using the second memory;
A storage medium comprising: a storage medium; An image processing apparatus that divides image data developed on a first memory into rectangular regions and processes the image data.
Mode setting means for setting an image processing mode;
For the image data, a rectangular area setting means for setting a rectangular area according to the set image processing mode,
Expanding means for reading image data corresponding to the set rectangular area and expanding the image data of the rectangular area on a second memory;
Image processing means for executing image processing according to the set image processing mode with respect to image data of a rectangular area developed on the second memory;
An image processing apparatus comprising: The image processing apparatus according to claim 15, wherein the rectangular area setting unit sets a rectangular area overlapping between adjacent areas. The rectangular area set by the rectangular area setting means includes:
An effective pixel area for processing by the image processing means;
16. The image processing apparatus according to claim 15, wherein a pixel area referred to for processing the effective pixel area is included. 16. The image processing apparatus according to claim 15, wherein the image processing unit switches a pixel area to be referred to within the rectangular area according to the set image processing mode. The rectangular area setting means controls division of the first memory in the main scanning direction and the sub-scanning direction on the basis of the resolution in the main scanning direction according to the set image processing mode and the pixel area to be referred to. The image processing apparatus according to claim 15, wherein: An image processing method for dividing image data developed on a first memory for each rectangular area and processing the divided image data.
A mode setting step of setting an image processing mode;
For the image data, a rectangular area setting step of setting a rectangular area according to the set image processing mode,
A developing step of reading image data corresponding to the set rectangular area and developing the image data on a sharable second memory;
An image processing step of performing image processing on the image data of the rectangular area developed on the second memory according to the set image processing mode;
An image processing method comprising: A program for executing, by a computer, an image processing method of dividing image data developed on a first memory into rectangular regions and processing the image data.
A mode setting module for setting an image processing mode;
For the image data, a rectangular area setting module that sets a rectangular area according to the set image processing mode,
A developing module for reading image data corresponding to the set rectangular area and developing the image data on a sharable second memory;
An image processing module for executing image processing by an image processing unit in accordance with the set image processing mode with respect to image data of a rectangular area expanded on the second memory;
A program characterized by comprising: A computer-readable storage medium storing an image processing program code, wherein the image processing program code is:
A mode setting code for setting an image processing mode;
A rectangular area setting code for setting a rectangular area according to the set image processing mode for the image data;
Expansion code for reading image data corresponding to the set rectangular area and expanding the image data on a sharable second memory;
Image processing code for executing image processing in image processing according to the set image processing mode for image data of a rectangular area developed on the second memory;
A storage medium comprising: An image processing device,
Address generation means for generating, in the image data developed on the first memory, address information corresponding to a rectangular area divided in the main scanning direction and the sub-scanning direction and reading out image data corresponding to the rectangular area; When,
Memory control means for reading image data corresponding to the rectangular area according to the generated address information and transferring the image data to a second memory;
A plurality of image processing means for executing image processing as a series of image processing on the image data transferred to the second memory,
The image processing apparatus according to claim 1, wherein the rectangular area has at least a maximum rectangular size required to execute the series of image processing. The image processing apparatus according to claim 23, wherein the rectangular area is a rectangular area to which an adjacent image area necessary for performing the series of image processing is added. Mode setting means for setting an image processing mode;
24. The image forming apparatus according to claim 23, further comprising: a rectangular area setting unit configured to set a rectangular area according to the set image processing mode for the image data. An image processing method,
Address generation that corresponds to a rectangular area divided in the main scanning direction and the sub-scanning direction with respect to the image data expanded on the first memory and generates address information for reading out the image data corresponding to the rectangular area Process and
A memory control step of reading image data corresponding to the rectangular area according to the generated address information and transferring the image data to a second memory;
An image processing step of executing a plurality of image processes as a series of image processes on the image data transferred to the second memory;
The image processing method according to claim 1, wherein the rectangular area has at least a maximum rectangular size required to execute the series of image processing. The image processing method according to claim 26, wherein the rectangular area is a rectangular area to which an adjacent image area necessary for executing the series of image processing is added. A mode setting step of setting an image processing mode;
The image processing method according to claim 26, further comprising: a rectangular area setting step of setting a rectangular area according to the set image processing mode for the image data. A program for executing, by a computer, an image processing method of dividing image data developed on a first memory into rectangular regions and processing the image data.
Address generation that corresponds to a rectangular area divided in the main scanning direction and the sub-scanning direction with respect to the image data expanded on the first memory and generates address information for reading out the image data corresponding to the rectangular area Modules and
A memory control module that reads image data corresponding to the rectangular area according to the generated address information and transfers the read image data to a second memory;
An image processing module that executes a plurality of image processes as a series of image processes on the image data transferred to the second memory;
The program, wherein the rectangular area has at least a maximum rectangular size required to execute the series of image processing. 30. The program according to claim 29, wherein the rectangular area is a rectangular area to which an adjacent image area necessary for executing the series of image processing is added. A mode setting module for setting an image processing mode;
30. The program according to claim 29, further comprising: a rectangular area setting module configured to set a rectangular area according to the set image processing mode for the image data.

Images