JP2004200520A - Tape carrier for semiconductor device and method of manufacturing the same - Google Patents

Abstract

An object of the present invention is to provide a tape carrier for a semiconductor device and a method for manufacturing the same, in which the uniformity of the plating thickness of a metal conductive layer in each blind via can be improved, and the tape carrier is less likely to warp.
In a tape carrier for a semiconductor device having a plurality of blind vias in which a metal conductive layer is formed by electrolytic plating, an opening having a metal conductive layer formed therein by electrolytic plating is provided around the blind via. Tape carrier for semiconductor device having section.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device tape carrier and a method of manufacturing the same, and more particularly to a semiconductor device tape carrier suitable for a BGA (Ball Grid Array) type package and a method of manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art As electronic devices have become smaller and higher in density, the pitch and diameter of solder balls in BGA type packages have been reduced. Dropping or breakage of the solder ball has become a more serious problem as the diameter of the solder ball has been reduced. As one means for improving the reliability of solder balls of a BGA type package, it has been proposed to form a conductive layer of a predetermined thickness in a blind via for mounting a solder ball on a wiring board used as an interposer of a BGA type package. For forming the conductive layer, a method of filling a conductive material such as a conductive paste, and a method of forming a metal conductive layer in a brand via by electrolytic plating are known (for example, Patent Document 1).
[0003]
[Patent Document 1]
JP-A-10-041356
[Problems to be solved by the invention]
A metal conductive layer formed by electrolytic plating has higher conductivity than that formed by filling a conductive paste or the like, and has an advantage that it can be applied to fine blind vias. Further, since the thickness of the conductive metal layer can be changed depending on the length of the electrolysis time, the degree of freedom of the thickness of the metal conductive layer is high.
[0005]
However, in the case of electrolytic plating, if the current distribution of each via is different, the deposition rate of the plating varies, and it is difficult to make the plating thickness uniform for each via. It is required to increase the quality. Further, there is a problem that the wiring board is warped due to a difference in thermal expansion coefficient between the insulating layer and the conductive layer, a stress generated during the manufacturing process, and the like, which causes a defect in a later process and a reduction in dimensional accuracy.
[0006]
The present invention has been made based on the above, and it is an object of the present invention to improve the uniformity of the plating thickness of the metal conductive layer in each blind via, and furthermore, it is possible to reduce the warpage of the tape carrier. To provide a tape carrier for use and a method for manufacturing the same.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a tape carrier for a semiconductor device having a plurality of blind vias in which a metal conductive layer is formed by electrolytic plating. Provided is a tape carrier for a semiconductor device having an opening in which a layer is formed.
[0008]
Further, the present invention provides a method of forming a plurality of holes to be blind vias in an insulating tape base, forming holes to be openings around the plurality of holes to be blind vias, and forming a metal conductive material by electroplating inside the blind vias. Provided is a method for manufacturing a tape carrier for a semiconductor device, in which a metal conductive layer is formed by electrolytic plating inside an opening at the same time as forming a layer.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of a tape carrier for a semiconductor device and a method of manufacturing the same according to the present invention will be described with reference to the accompanying drawings.
[0010]
FIG. 1 is an explanatory view of an embodiment of a tape carrier for a semiconductor device according to the present invention, as viewed from an insulating layer side. Reference numeral 1 denotes an insulating layer. The insulating layer 1 is provided with a blind via 3 and an opening 4 formed around the blind via 3. Although not shown, a metal conductive layer described later is formed inside the blind via 3 and the opening 4 by electrolytic plating.
[0011]
When electrolytic plating is performed on the blind via 3, when the opening 4 does not exist, the current concentrates on the brand via 3 located on the outer peripheral portion, the deposition speed increases, and the plating thickness becomes larger than other portions. However, as in the present invention, the openings 4 are formed around the blind vias 3 and electrolytic plating is performed on the openings 4 as well, so that the blind vias 3 can be uniformly formed. It is possible to perform a large plating thickness.
[0012]
Generally, as shown in FIG. 1, a plurality of blind vias 3 are arranged in a lattice pattern. By forming openings 4 around the blind vias 3, current concentration is reduced and the metal conductive layer is formed. The thickness can be made uniform. In addition, by arranging the openings 4 in which the metal conductive layers are formed, the rigidity of the insulating layer is increased, and the effect of suppressing the warpage of the semiconductor carrier tape is also achieved.
[0013]
FIG. 2 is an explanatory diagram of one embodiment of a method of manufacturing a carrier tape for a semiconductor device according to the present invention.
[0014]
First, as shown in (a), a blind via and a hole 2 serving as an opening are formed in an insulating layer 1 by press working.
[0015]
As shown in (b), a copper foil 5 is laminated on the insulating layer 1 to form a blind via 3 and an opening 4.
[0016]
As shown in (c), a masking tape 6 is laminated on the surface of the copper foil 5.
[0017]
As shown in (d), the tape material is immersed in a plating solution and a current is applied to the copper foil 5 to deposit a metal conductive layer 7 in the blind via 3 and the opening 4.
[0018]
As shown in (e), the masking tape 6 is peeled off to expose the copper foil 5.
[0019]
As shown in (f), a wiring pattern 9 as shown in (g) is formed by applying an etching resist 8 on the surface of the copper foil 5 and performing exposure and development.
[0020]
Finally, as shown in (h), the etching resist 8 is peeled off to obtain a semiconductor device carrier tape.
[0021]
(Example)
A plurality of through-holes having a diameter of 300 μm are formed in a position corresponding to a solder ball mounting position of a BGA package using a mold on an insulating tape base material (insulating layer) obtained by applying a 12 μm-thick adhesive to a 50 μm-thick polyimide tape. Simultaneously with the formation, a plurality of through holes having a width of 100 μm and a length of 400 μm were formed around the through holes. Subsequently, a copper foil having a thickness of 18 μm was attached to close one of the through holes to form a blind via having a diameter of 300 μm and an opening having a width of 100 μm and a length of 400 μm. The blind vias were arranged in a grid at equal intervals, and the periphery thereof was arranged so that the opening surrounded the opening. A masking tape is stuck so as to cover the entire surface of the copper foil, immersed in a copper sulfate plating solution in this state, and subjected to electrolytic copper plating at a cathode current density of 5 A / cm ² for 27 minutes. A copper plating layer (metal conductive layer) having a thickness of 30 μm was formed. Thereafter, the masking tape is peeled off, a photosensitive liquid resist for etching is applied to the copper foil surface with a thickness of 3 μm, a wiring pattern is formed using a wiring pattern mask, and the liquid resist is removed with an alkaline resist stripper. Thus, an intended tape carrier for a semiconductor device was obtained.
[0022]
3 and 4 show other embodiments of the semiconductor carrier tape of the present invention, respectively. FIG. 3 shows a blind via 3 surrounded by a circular opening 10 and FIG. , The periphery of the blind via 3 is continuously surrounded by a rectangular opening 44.
[0023]
【The invention's effect】
As described above, the present invention relates to a tape carrier for a semiconductor device having a plurality of blind vias in each of which a metal conductive layer is formed by electrolytic plating. The present invention provides a tape carrier for a semiconductor device having openings formed with holes, whereby the uniformity of the plating thickness of the metal conductive layer in each brand via can be increased, and the tape carrier is warped. It is possible to realize a semiconductor device tape carrier that is difficult to perform.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of one embodiment of a tape carrier for a semiconductor device of the present invention.
FIG. 2 is an explanatory view of one embodiment of a method for manufacturing a tape carrier for a semiconductor device of the present invention.
FIG. 3 is an explanatory view of another embodiment of the tape carrier for a semiconductor device of the present invention.
FIG. 4 is an explanatory view of another embodiment of the tape carrier for a semiconductor device of the present invention.
[Explanation of symbols]
1: insulating layer 2: hole 3: blind via 4: opening 5: copper foil 6: masking tape 7: metal conductive layer 8: resist 9: wiring pattern

Claims (5)

In a tape carrier for a semiconductor device having a plurality of blind vias in which a metal conductive layer is formed by electrolytic plating, a peripheral portion of the blind via having an opening in which a metal conductive layer is formed by electrolytic plating. Characteristic tape carriers for semiconductor devices. The tape carrier for a semiconductor device according to claim 1, wherein the blind vias are arranged in a grid. 2. The tape carrier for a semiconductor device according to claim 1, wherein the metal conductive layer formed in the blind via and the metal conductive layer formed in the opening are formed by electrolytic plating at the same time. A plurality of holes serving as blind vias are formed in the insulating tape base material, and holes serving as openings are formed around the plurality of holes serving as the blind vias. A method for manufacturing a tape carrier for a semiconductor device, comprising forming a metal conductive layer inside a portion by electrolytic plating. 5. The method according to claim 4, wherein a plurality of holes serving as the blind vias are arranged in a lattice.

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